TWI651819B - Substrate structure and its preparation method - Google Patents

Abstract

A substrate structure includes: a substrate body having an outer surface and an electrical contact pad exposed on the outer surface, an insulating layer formed on the substrate body and exposing the electrical contact pad, and formed on the electrical contact pad The conductive element and the buffer layer formed on the insulating layer, so that the buffer layer surrounds the conductive element, and makes the end of the conductive element protrude from the buffer layer, so the buffer layer can be dispersed due to high temperature operation The stress generated by the heat is concentrated on the conductive element to prevent the conductive element from cracking.

Description

   Substrate structure and its manufacturing method   

The invention relates to a semiconductor manufacturing process, in particular to a substrate structure applied to a semiconductor package and a manufacturing method thereof.

With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multi-function and high performance. There are many technologies currently used in the field of chip packaging, such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (Multi-Chip Module, abbreviation) MCM) and other flip-chip packaging modules, or integrating the three-dimensional stacking of chips into a three-dimensional integrated circuit (3D IC) chip stacking technology.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1 stacked in a three-dimensional integrated circuit chip. As shown in the figure, a through silicon interposer (TSI) 10 is provided. The silicon interposer 10 has opposite sides 10b and a transfer side 10a, and connects the side 10b and the transfer side 10a A plurality of through-silicon vias (TSV) 100, and a redistribution layer (RDL) 11 on the crystal placement side 10b for the electrode pads of the semiconductor wafer 6 with a smaller pitch 60 is electrically coupled to the circuit redistribution structure 11 by a plurality of solder bumps 61, and then the solder bumps 61 are covered with a primer 62, and a plurality of solder bumps are formed on the conductive silicon through-hole 100 The conductive elements 17 are electrically combined with the bonding pads 70 of the package substrate 7 with a larger pitch, and then a packaging gel 8 is formed on the package substrate 7 to cover the semiconductor chip 6 and the silicon interposer 10.

However, in the conventional silicon interposer 10 or the package substrate 7, when the high temperature operation is performed, for example, the conductive element 17 is reflowed, then the residual stress due to heat will be concentrated in the conductive element 17, such as the first The stress concentration k shown in the figure causes the conductive elements 17 to crack or even extend to the circuit to which they are bonded (such as the circuit of the packaging substrate 7 or the conductive silicon through-hole 100, etc.), thus Reduce the reliability of the semiconductor package 1 and the yield of products.

Furthermore, the same problem may also occur on the solder bump 61 between the semiconductor chip 6 and the circuit redistribution structure 11, causing cracks between the solder bump 61 and the circuit redistribution structure 11, such as The stress concentration k shown in FIG. 1 even breaks to the circuit to which it is bonded (such as the circuit redistribution structure 11 or the electrode pad 60 of the semiconductor chip 6 etc.), thereby reducing the reliability and product of the semiconductor package 1 The yield.

Therefore, how to overcome the various problems of the above-mentioned conventional technologies has become an urgent issue to be solved.

In view of the above-mentioned defects of the prior art, the present invention provides a substrate structure including: a substrate body having an outer surface and at least one electrical contact pad exposed on the outer surface; an insulating layer formed on the substrate The entire outer surface of the body, and the electrical contact pad is exposed to the insulating layer; the conductive element is formed on the electrical contact pad; and the buffer layer is formed on the insulating layer to surround the conductive element , And make the end of the conductive element protrude from the buffer layer.

The invention also provides a method for manufacturing a substrate structure, which includes: providing a substrate body having an outer surface and at least one electrical contact pad exposed on the outer surface; forming an insulating layer on all outer surfaces of the substrate body, And the electrical contact pad is exposed to the insulating layer; a conductive element is formed on the electrical contact pad; and a buffer layer is formed on the insulating layer, so that the buffer layer surrounds the conductive element and the end of the conductive element Part protrudes the buffer layer.

In the aforementioned substrate structure and its manufacturing method, before forming the conductive element, a conductive pillar is formed on the electrical contact pad, so that the electrical contact pad is combined with the conductive element through the conductive pillar. For example, the end of the conductive post is a connection pad to join the conductive element.

In the foregoing substrate structure and its manufacturing method, it includes an insulating protective layer formed on a part of the surface of the insulating layer or on a part of the surface of the buffer layer.

In the aforementioned substrate structure and its manufacturing method, it further includes forming a metal layer between the conductive element and the electrical contact pad.

In the aforementioned substrate structure and manufacturing method thereof, the material of the insulating layer and the material of the buffer layer are different.

It can be seen from the above that in the substrate structure and the manufacturing method of the present invention, the conductive element is mainly surrounded by the buffer layer, so that the buffer layer can disperse the stress generated by heat and concentrate on the high temperature operation such as the reflow process The conductive element provides a buffering effect to suppress the stress. Compared with the conventional technology, the substrate structure of the present invention can prevent the conductive element from cracking, thereby improving the reliability of the substrate structure and the yield of the product.

1‧‧‧Semiconductor package

10‧‧‧Silicon Intermediate Board

10a‧‧‧Transfer side

10b‧‧‧ Place crystal side

100‧‧‧Perforated conductive silicon

11‧‧‧ Line redistribution structure

2,3,4‧‧‧Substrate structure

20,40‧‧‧Substrate body

20a, 40a, 40b ‧‧‧ outer surface

200‧‧‧Electrical contact pad

21,21a, 21b‧‧‧Insulation

210‧‧‧opening

22‧‧‧buffer layer

26‧‧‧Metal layer

17,27,37‧‧‧Conducting element

33‧‧‧conductive column

330‧‧‧ connection pad

35‧‧‧Insulation protective layer

350‧‧‧ opening

6‧‧‧Semiconductor chip

60‧‧‧electrode pad

61‧‧‧Solder bump

62‧‧‧ Primer

7‧‧‧Package substrate

70‧‧‧solder pad

8‧‧‧Packing colloid

k‧‧‧Stress concentration

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor package; Figs. 2A and 2B are schematic cross-sectional views of the manufacturing method of the first embodiment of the substrate structure of the present invention; Fig. 2C is another embodiment of Fig. 2B Figure 3A is a schematic cross-sectional view of the manufacturing method of the second embodiment of the substrate structure of the present invention; Figures 3B and 3C are different embodiments of Figure 3A; and Figure 4 is the first of the substrate structure of the present invention A schematic cross-sectional view of the manufacturing method of the third embodiment.

The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the contents disclosed in the specification, for those familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions, so it does not have the technical significance, any modification of structure, change of proportional relationship or adjustment of size, should not fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "上" and "一" quoted in this specification are only for the convenience of description, not to limit the scope of the invention can be implemented, and the relative relationship is changed or adjusted. Substantially changing the technical content should also be regarded as the scope of the invention.

2A to 2B are schematic cross-sectional views of the first embodiment of the method for manufacturing the substrate structure 2 of the present invention.

As shown in FIG. 2A, a substrate body 20 is provided, which has an outer surface 20a and at least one electrical contact pad 200 exposed on the outer surface 20a. Next, at least one insulating layer 21 is formed on all outer surfaces 20 a of the substrate body 20, and the electrical contact pad 200 is exposed on the insulating layer 21. After that, a conductive element 27 is formed on the exposed electrical contact pad 200.

In this embodiment, the substrate body 20 is an insulating plate, a metal plate, or a semiconductor plate such as a wafer, chip, silicon interposer, silicon material, glass, etc. The substrate body 20 has a circuit structure, which includes a dielectric layer and a circuit layer provided on the dielectric layer, such as a fan out redistribution layer (RDL), and forms the The material of the circuit layer is copper, and the material forming the dielectric layer is, for example, polybenzoxazole (Polybenzoxazole, PBO), polyimide (Polyimide, PI), prepreg (Prepreg, PP) ) Dielectric materials. Specifically, the outermost circuit layer of the substrate body 20 has the electrical contact pad 200.

Furthermore, the insulating layer 21 is sequentially formed on all outer surfaces 20a of the substrate body 20 and formed with openings 210 that expose the electrical contact pad 200 in common. For example, the material of the insulating layer 21 may be an oxide layer or a nitride layer, such as silicon oxide (SiO ₂ ) or silicon nitride (Si _x N _y ). It should be understood that multiple insulating layers 21a, 21b may also be formed on all outer surfaces 20a of the substrate body 20, and the materials of the insulating layers 21a, 21b may be the same or different.

Furthermore, the outer surface 20a of the substrate body 20 is used as the crystal placement side of the bonded wafer, and the conductive element 27 is a conductive bump such as a metal bump (copper bump) or a solder bump, such as a micro bump (μ -bump) specifications. In addition, a metal layer 26 may be formed between the conductive element 27 and the electrical contact pad 200. Specifically, the metal layer 26 is formed on the electrical contact pad 200 in the opening 210 and extends to a part of the surface of the insulating layer 21 b for bonding the conductive element 27.

In addition, the metal layer 26 is an under bump metal layer (UBM), and the material forming the metal layer 26 is, for example, titanium / copper / nickel or titanium / nickel vanadium / copper, which can be splashed A patterning process is carried out by sputtering or plating in conjunction with exposure and development to form the metal layer 26. However, the structure and material of the metal layer 26 are various, and are not limited to the above.

As shown in FIG. 2B, a buffer layer 22 is formed on the insulating layer 21 (or insulating layer 21b) on the entire outer surface 20a of the substrate body 20 so that the buffer layer 22 covers the conductive element 27, so that the conductive element 27 partially (ends) protrudes from the buffer layer 22, so as to be combined with an electronic device such as a semiconductor element, a package substrate or a circuit board.

In this embodiment, the insulating material buffer layer 22 is first coated on the top of the conductive element 27 by coating or lamination, and then etched, lasered, polished, exposed, or developed. A part of the buffer layer 22 is removed so that the end of the conductive element 27 protrudes from the buffer layer 22.

Furthermore, the materials for forming the buffer layer 22 are, for example, polybenzoxazole (PBO), polyimide (PI), and prepreg (PP).

Furthermore, in other manufacturing methods, as shown in FIG. 2C, the buffer layer 22 may be formed on the insulating layer 21 and the electrical contact pad 200 is exposed, and then the metal layer 26 and the conductive element 27 may be formed.

The manufacturing method of the substrate structure 2 of the present invention is to cover the periphery of the conductive element 27 with the buffer layer 22, so that when the high temperature operation is performed (for example, when the conductive element 27 is soldered to a semiconductor chip after reflow), the buffer The layer 22 can disperse the stress generated by the heat and concentrate it in the conductive element 27, and provide a buffering effect to suppress the stress. Therefore, compared with the conventional technology, the substrate structure 2 of the present invention can prevent the conductive element 27 from cracking. In this case, the reliability of the substrate structure 2 and the yield of the product are further improved.

3A to 3C are schematic cross-sectional views of the second embodiment of the substrate structure 3 of the present invention. The difference between this embodiment and the first embodiment lies in the connection structure between the electrical contact pad and the conductive element, and the other structures are substantially the same, so the details are not repeated below.

As shown in FIG. 3A, a conductive pillar 33 may be first formed on the electrical contact pad 200. The conductive pillar 33 is a metal pillar (such as a copper pillar) formed in the opening 210 of the insulating layers 21a, 21b In addition, the end of the conductive pillar 33 is extended and formed on the insulating layer 21b to serve as the connection pad 330. Next, an insulating protective layer 35 exposing the connection pad 330 is formed on a part of the surface of the insulating layer 21b corresponding to the conductive pillar 33, so that the electrical contact pad 200 is combined with the conductive pillar 33 (connection pad 330) Metal layer 26 and the conductive element 37. After that, the buffer layer 22 is formed on the insulating layer 21b and the insulating protective layer 35, so that the buffer layer 22 covers the conductive element 37, and the conductive element 37 partially protrudes from the buffer layer 22 for Electronic devices incorporating semiconductor components, package substrates, circuit boards, etc.

Furthermore, the insulating protection layer 35 is formed with an opening 350 to expose the connection pad 330 to the opening 350 of the insulating protection layer 35 to join the conductive element 37 (or the metal layer 26). For example, the insulating protective layer 35 is polybenzoxazole (Polybenzoxazole, PBO for short), polyimide (Polyimide, PI for short), or benzocyclobutene (Benzocyclclobutene, BCB for short).

It should be understood that, as shown in FIG. 3B, the buffer layer 22 may be formed on the insulating layer 21 b and the insulating protective layer 35 before forming the metal layer 26 and the conductive element 37.

In addition, the insulating protective layer 35 is used to prevent the delamination of the metal layer 26 (or the conductive element 37). Therefore, as shown in FIG. 3C, the buffer layer 22 may be first formed on the insulating layer 21b, and then the insulating protective layer 35 may be formed on a partial surface of the buffer layer 22, and then the metal layer 26 may be formed on the On the insulating protective layer 35.

In addition, the outer surface 20a of the substrate body 20 is used as the non-crystalline side, such as the bumping side or the transfer side, and the conductive element 37 is a solder ball, such as the C4 bump specification.

The manufacturing method of the substrate structure 3 of the present invention is to cover the conductive element 37 with the buffer layer 22, so that when the high temperature operation is performed (for example, when the conductive element 37 is soldered to the package substrate after reflow), the buffer layer 22 It can disperse the stress generated by the heat and concentrate it in the conductive element 37, and provide a buffering effect to suppress the stress. Therefore, compared with the conventional technology, the substrate structure 3 of the present invention can avoid the occurrence of cracking of the conductive element 37. Furthermore, the reliability of the substrate structure 3 and the yield of products are improved.

FIG. 4 is a schematic cross-sectional view of a third embodiment of the method for manufacturing the substrate structure 4 of the present invention. This embodiment is a combination of the first embodiment and the second embodiment, so the same points are not repeated below.

As shown in FIG. 4, the substrate body 40 has two opposite outer surfaces 40a, 40b, which serve as a crystal placement side and a non-crystal placement side, respectively.

In this embodiment, the manufacturing method of the substrate structure 4 is, for example, to first complete the conductive element 27 and the buffer layer 22 on the outer surface 40a (crystal placement side) of the substrate body 40, as shown in FIG. 2B, to For bonding electronic components (figure omitted) such as a semiconductor wafer (such as the semiconductor wafer 6 of FIG. 1) on the conductive element 27; then, on the other outer surface 40b (non-crystal placement side) of the substrate body 40 The manufacturing process is to form the conductive pillar 33, the insulating protective layer 35, the conductive element 37 and another buffer layer 22, as shown in FIG. 3A, for combining external devices such as package substrates.

Through the foregoing manufacturing method, the present invention provides a substrate structure 2, 3, 4 including: a substrate body 20, 40, at least one insulating layer 21, 21a, 21b, a conductive element 27, 37, and a buffer layer 22.

The substrate body 20, 40 has an outer surface 20a, 40a, 40b and at least one electrical contact pad 200 exposed on the outer surface 20a, 40a, 40b.

The insulating layers 21, 21a, 21b are formed on all outer surfaces 20a, 40a, 40b of the substrate bodies 20, 40, and the electrical contact pad 200 is exposed to the insulating layers 21, 21a, 21b.

The conductive elements 27 and 37 are formed on the electrical contact pad 200.

The buffer layer 22 is formed on the insulating layer 21b on all the outer surfaces 20a, 40a, 40b of the substrate body 20, 40 to surround the conductive elements 27, 37 and make the conductive elements 27, 37 The buffer layer 22 protrudes locally (end).

In one embodiment, the electrical contact pad 200 is coupled to the conductive element 37 through at least one conductive post 33. For example, the end of the conductive pillar 33 is a connection pad 330 to join the conductive element 37.

In one embodiment, an insulating protective layer 35 is formed on a part of the surfaces of the insulating layers 21 and 21b or a part of the surface of the buffer layer 22.

In one embodiment, the substrate structures 2, 3, and 4 include a metal layer 26 formed between the conductive elements 27, 37 and the electrical contact pad 200.

In an embodiment, the materials of the insulating layers 21, 21a, 21b and the material of the buffer layer 22 are different.

In summary, the substrate structure of the present invention is designed to surround the conductive element by the buffer layer, so as to avoid the concentration of thermal stress and cause the conductive element to crack, so the reliability of the substrate structure and the product can be improved Yield.

The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

Claims (10)

A substrate structure includes: a substrate body having an outer surface and at least one electrical contact pad exposed on the outer surface; an insulating layer is formed on all outer surfaces of the substrate body and makes the electrical contact The pad is exposed to the insulating layer; the conductive element is formed on the electrical contact pad, and the conductive element is a solder bump or a copper bump; the metal layer is formed between the conductive element and the electrical contact pad , As an under bump metal layer (Under Bump Metal), so that the insulating layer is exposed to the metal layer; and a buffer layer is formed on the insulating layer to cover all the exposed surface of the insulating layer above and surround the Around the conductive element and extending the conductive element from the buffer layer so that the end of the conductive element protrudes from the surface of the buffer layer. The substrate structure as described in item 1 of the patent application range, wherein the electrical contact pad is combined with the conductive element by a conductive post. The substrate structure as described in item 2 of the patent application scope, wherein the end of the conductive pillar is a connection pad for bonding the conductive element. The substrate structure as described in item 1 of the scope of the patent application includes an insulating protective layer formed on a part of the surface of the insulating layer or on a part of the surface of the buffer layer. The substrate structure as described in item 1 of the patent application scope, wherein the material of the insulating layer and the material of the buffer layer are different. A method for manufacturing a substrate structure includes: providing a substrate body having an outer surface and at least one electrical contact pad exposed on the outer surface; forming an insulating layer on all outer surfaces of the substrate body and enabling the electric Sexual contact pad is exposed on the insulating layer; a conductive element is formed on the electrical contact pad, and a metal layer is formed between the conductive element and the electrical contact pad to serve as an under bump metal layer (Under Bump Metal), wherein , The conductive element is a solder bump or a copper bump; and a buffer layer is formed on all exposed surfaces of the insulating layer, so that the buffer layer surrounds the conductive element, and the conductive element is outward from the buffer layer Extending so that the end of the conductive element protrudes from the surface of the buffer layer. The manufacturing method of the substrate structure as described in item 6 of the patent application scope includes forming a conductive post on the electrical contact pad before forming the conductive element, so that the electrical contact pad is combined with the conductive element through the conductive post . The method for manufacturing a substrate structure as described in item 7 of the patent application scope, wherein the end of the conductive post is a connection pad for bonding the conductive element. The method for manufacturing a substrate structure as described in item 6 of the patent application scope includes forming an insulating protective layer on a part of the surface of the insulating layer or a part of the surface of the buffer layer. The manufacturing method of the substrate structure as described in item 6 of the patent application scope, wherein the material of the insulating layer and the material of the buffer layer are different.