TWI651851B - Semiconductor device and method of manufacturing same - Google Patents

Abstract

A semiconductor device includes an n-type gate structure disposed on a first semiconductor fin, wherein the n-type gate structure is combined with fluorine, and includes an n-type work function metal disposed on a first high-k dielectric layer. Floor. The n-type work function metal layer includes a titanium aluminum (TiAl) alloy, wherein the atomic ratio of titanium to aluminum is substantially between 1 and 3. The semiconductor device further includes a p-type gate structure disposed on the second semiconductor fin, wherein the p-type gate structure is combined with fluorine and includes a p-type work function metal layer disposed on the second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), wherein the atomic ratio of titanium to nitrogen is substantially between 1: 0.9 and 1: 1.1.

Description

   Semiconductor device and manufacturing method thereof   

The present disclosure relates to a semiconductor device, and more particularly to a gate structure of a Fin-like Field Effect Transistor (FinFET) and a method for manufacturing the same.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. During the evolution of ICs, the functional density (defined as the number of interconnected components on each wafer area) generally decreases with the geometric size (meaning the smallest component or circuit that can be made using the process) While increasing. A scaled-down process can generally provide the advantages of increased yields and associated costs. However, such a reduction will increase the complexity of the process and production IC. To achieve these advances, similar developments in IC production are necessary.

When the semiconductor IC industry entered the nanotechnology process generation to pursue higher component density, higher efficiency, and lower cost, at the same time, manufacturing and design challenges led to the development of 3D devices such as FinFETs. development of. The advantages of FinFET devices include reduced short-channel effects and higher current levels. As its feature size continues to decrease, there has been a demand for FinFET devices using gate dielectric layers and metal gates with high dielectric constants to improve device performance. The gate structures of n-type metal-oxide-semiconductor (NMOS) devices and p-type metal-oxide-semiconductor (PMOS) devices require different work functions, respectively. The conventional FinFET device with a high dielectric constant metal gate and its manufacturing method cannot satisfy all aspects, especially the NMOS device and the PMOS device are manufactured together.

One aspect of the present disclosure is to provide a semiconductor device including a semiconductor substrate; a first semiconductor fin on the semiconductor substrate; and an n-type gate structure disposed on the first semiconductor fin. The barrier metal layer includes titanium nitride (TiN). The n-type gate structure is combined with fluorine, and the n-type gate structure includes a first initial layer disposed on the first semiconductor fin; and a first high dielectric layer disposed on the first initial layer and surrounded by the first gate gap Dielectric constant dielectric layer; an n-type work function metal layer disposed on a first high-dielectric constant dielectric layer, wherein the n-type work function metal layer contains a titanium aluminum (TiAl) alloy, and the atomic ratio of titanium to aluminum is substantially From 1 to 3; a barrier metal layer disposed on the n-type work function metal layer; and a first metal filling layer surrounded by the barrier metal layer so that the first metal filling layer is surrounded by the first stacked structure, wherein The sidewall of the first stacked structure includes a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and the bottom of the first stacked structure includes a fluorine concentration substantially from 1 atomic percent to 15 atomic percent.

Another aspect of the present disclosure is to provide a semiconductor device including a semiconductor substrate; a first semiconductor fin and a second semiconductor fin, an n-type gate structure, and a p-type gate structure on the semiconductor substrate. The first semiconductor fin and the second semiconductor fin are separated by an isolation structure. The n-type gate structure is combined with fluorine and includes a first initial layer disposed on the first semiconductor fin and is surrounded by the first gate gap. The p-type gate structure is combined with fluorine and includes a first A second initial layer on the two semiconductor fins and surrounded by a second gate spacer. Each of the n-type gate structure and the p-type gate structure includes a high dielectric constant dielectric layer disposed on the first initial layer and the second initial layer; and a first nitrogen disposed on the high dielectric constant dielectric layer. A titanium nitride layer; a tantalum nitride (TaN) layer provided on the first titanium nitride layer; a second titanium nitride layer provided on the tantalum nitride layer; a titanium aluminum alloy provided on the second titanium nitride layer A third titanium nitride layer disposed on the titanium aluminum alloy layer; and a metal filling layer surrounded by the third titanium nitride layer so that the metal filling layer is surrounded by the stacked structure, wherein the sidewall of the stacked structure includes a substantial Is a fluorine concentration from 5 atomic percent to 20 atomic percent, and the bottom of the second stacked structure includes a fluorine concentration substantially from 1 atomic percent to 15 atomic percent. The titanium aluminum alloy layer surrounded by the first gate gap wall is used as an n-type work function metal layer, and its atomic ratio of titanium to aluminum is substantially between 1 and 3. The second titanium nitride layer surrounded by the second gate gap wall is used as a p-type work function metal layer, and its atomic ratio of titanium to nitrogen is substantially between 1: 0.9 and 1: 1.1.

Another aspect of the present disclosure is to provide a method for forming a semiconductor device. In this method, a first semiconductor fin and a second semiconductor fin are formed on a semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure. The first initial layer is surrounded by the first gate spacer and formed on the first semiconductor fin, and the second initial layer is surrounded by the second gate spacer and formed on the second semiconductor fin. A high-k dielectric layer is deposited on the first and second initial layers. A first titanium nitride layer is deposited on the high-k dielectric layer. A tantalum nitride layer is deposited on the first titanium nitride layer. A second titanium nitride layer is deposited on the tantalum nitride layer. A titanium aluminum alloy layer is deposited on the second titanium nitride layer. A third titanium nitride layer is deposited on the titanium aluminum alloy layer. A metal-filled layer surrounded by a third titanium nitride layer is deposited by using a fluorine-containing precursor (for example, WF ₆ ). Then, for example, by performing a thermal process, the fluorine system diffuses to the stacked structure surrounding the metal filling layer, so that the sidewall of the stacked structure contains a fluorine concentration substantially from 5 atomic percent to 15 atomic percent, and the bottom of the stacked structure contains substantial It is a fluorine concentration from 1 atomic percent to 15 atomic percent. The titanium aluminum alloy layer surrounded by the first gate gap wall is used as the n-type work function metal layer, and the range of the atomic ratio of titanium to aluminum is substantially from 1 to 3. The second titanium nitride layer surrounded by the second gate gap wall is used as the p-type work function metal layer, and the range of the atomic ratio of titanium to nitrogen is substantially from 1: 0.9 to 1: 1.1.

100a / 100b‧‧‧n / p gate structure

102‧‧‧ semiconductor substrate

104‧‧‧Isolated structure

110a / 110b‧‧‧Semiconductor Fin

112a / 114a‧‧‧Source / Drain

112b / 114b‧‧‧Source / Drain

120‧‧‧ Etching stop layer

122a / 122b‧‧‧Gate wall

130a / 130b‧‧‧Initial layer

140a / 140b‧‧‧High dielectric constant dielectric layer

142a / 142b‧‧‧ metal overlay

144a / 144b‧‧‧ barrier metal layer

146a‧‧‧Titanium nitride (TiN) layer

146b‧‧‧p-type work function metal layer

148a‧‧‧n type work function metal layer

148b‧‧‧TiAl alloy layer

150a / 150b‧‧‧ barrier metal layer

160a / 160b‧‧‧ metal filling layer

170‧‧‧Inner dielectric layer

180a / 180b‧‧‧ stacked structure

200a / 200b‧‧‧n / p gate structure

202‧‧‧Semiconductor substrate

204‧‧‧Isolated structure

210a / 210b‧‧‧Semiconductor Fin

212a / 214a‧‧‧Source / Drain

212b / 214b‧‧‧Source / Drain

220‧‧‧ Etching stop layer

222a / 222b‧‧‧Gate

230a / 230b‧‧‧Initial layer

240‧‧‧ high dielectric constant dielectric layer

242‧‧‧TiN layer

244‧‧‧TaN layer

246‧‧‧TiN layer

248‧‧‧TiAl layer

250‧‧‧TiN layer

260‧‧‧ metal filling layer

270‧‧‧Inner dielectric layer

280‧‧‧ stacked structure

300a / 300b‧‧‧n / p gate structure

302‧‧‧Semiconductor substrate

304‧‧‧Isolation structure

310a / 310b‧‧‧Semiconductor Fin

312a / 314a‧‧‧Source / Drain

312b / 314b‧‧‧Source / Drain

320‧‧‧ Etching stop layer

322a / 322b‧‧‧Gate

330a / 330b‧‧‧Initial layer

340‧‧‧High dielectric constant dielectric layer

342‧‧‧TiN layer

344‧‧‧TaN layer

346‧‧‧TiN layer

348‧‧‧TiAl layer

350‧‧‧TiN layer

360‧‧‧ metal filling layer

370‧‧‧Inner dielectric layer

380a / 380b‧‧‧Polycrystalline silicon gate

390‧‧‧ stacked structure

400‧‧‧ forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate

410‧‧‧ forming a first initial layer and a second initial layer on a first semiconductor fin on a second semiconductor fin

420‧‧‧ forming a high-k dielectric layer

430‧‧‧ forming the first TiN layer on the high dielectric constant dielectric layer

440‧‧‧ forms a TaN layer on the first TiN layer

450‧‧‧ forming a second TiN layer on the TaN layer

460‧‧‧ forms a TiAl layer on the second TiN layer

470‧‧‧ forms a third TiN layer on the TiAl layer

480‧‧‧ forming a metal filling layer surrounded by a third TiN layer by using a fluorine-containing precursor

490‧‧‧ diffuses fluorine to the stacked structure surrounding the metal filling layer

The aspect of the disclosure can be best understood from the following detailed description and reading the accompanying drawings. It should be noted that, as in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

2A and 2B are schematic cross-sectional views illustrating a semiconductor device according to some embodiments of the present disclosure.

[FIG. 3A] to [FIG. 3G] are schematic cross-sectional views illustrating an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments of the disclosure.

4 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

The following summary provides many different embodiments or specific examples to implement the various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the following description, the formation of the first feature on or above the second feature may include an embodiment in which the first feature and the second feature are in direct contact, or may include between the first feature and the second feature. Embodiments of additional features are formed so that the first and second features are not in direct contact.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of patent applications. For example: unless otherwise restricted, the singular forms "a" or "the" can be used to refer to plural forms. In addition, the disclosure may repeat element symbols and / or letters in various specific examples. This repetition is for simplicity and clarity, and does not in itself indicate any relationship between the various embodiments and / or configurations discussed. The term spatial relativity is used to explain the different orientations of components when they are used or operated, and is not limited to the direction shown in the illustration. Elements can also be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptors used here can be interpreted as such.

Understandably, although the terms "first," "second," and "third" can be used in the scope of patent applications to describe different elements, these elements should not be limited by these terms. These elements described correspondingly in the embodiments are represented by different element symbols. These terms are used to distinguish different elements. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the embodiments. The term "and / or" as used thus includes any or all combinations of one or more of the associated listed items.

The embodiment disclosed in this disclosure is directed to a semiconductor device on which a p-type metal oxide semiconductor fin field-effect transistor (PMOS FinFET) device with a metal gate structure and an n-type metal oxide semiconductor fin-type field effect transistor are simultaneously formed. (NMOS FinFET) devices to simplify the manufacturing process. According to the analysis by Energy Dispersive Spectroscopy (EDS), the NMOS FinFET device includes an n-type work function metal layer. The n-type work function metal layer includes a titanium aluminum (TiAl) alloy, in which the atomic ratio of Ti to Al is substantially between 1 and 3, and the two surfaces of the n-type work function metal layer contain substantially less than 10 atomic percent (at%). ) Oxygen concentration. The PMOS FinFET device includes a p-type work function metal layer on a second high-k dielectric layer. The p-type work function metal layer includes titanium nitride (TiN), where the atomic ratio of Ti to N is substantially between 1 and 1. : 0.9 to 1: 1.1, and the p-type work function metal layer contains an oxygen concentration of less than 10 atomic percent (at%). Oxygen causes the work function of the work function metal layer to change, so lower oxygen concentrations can lead to better work function metal layer quality. Therefore, the disclosed embodiments provide a work function metal layer having excellent properties.

By reducing the threshold voltage offset of bias-temperature instabiliy (BTI) and stress induced leakage current (SILC), fluorine improves high dielectric constant / metal gate (High- k / Metal Gate, HKMG) candidate for overall reliability. For example, a high-dielectric material (eg, zirconia, HfO ₂ ) incorporating fluorine should be able to replace the disappearing oxygen in the vacancies and lead to more stable bonding. It should be noted that from the elemental analysis obtained by EDS, the aforementioned composition, atomic ratio, and concentration of oxygen and fluorine are important. In addition, higher fluorine concentrations can lead to the adverse consequences of device shifting, while too low fluorine concentrations result in less efficient device performance.

Please refer to FIG. 1, which is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. This semiconductor device includes a semiconductor substrate 102, a first semiconductor fin 110a, a second semiconductor fin 110b, an n-type gate structure 100a, and a p-type gate structure 100b. The n-type gate structure 100a and / or the p-type gate structure 100b are bonded to fluorine. The semiconductor fin 110 a and the semiconductor fin 110 b are disposed above the semiconductor substrate 102 and are separated by the isolation structure 104. In some embodiments, the isolation structure 104 is Shallow Trench Isolation (STI). The semiconductor substrate 102 may be defined as any structure containing a semiconductor material, including, but not limited to, a bulk silicon (Bulk Silicon), a semiconductor wafer, or a silicon germanium substrate. Other semiconductor materials containing Group III, Group IV, and Group V elements can also be used. The semiconductor fins 110 a and 110 b project from the semiconductor substrate 102. The gate spacer 122a is formed on a side wall of the n-type gate structure 100a, and the gate spacer 122b is formed on a side wall of the p-type gate structure 100b. The gate spacers 122a and 122b may include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The source / drain portions 112a and 114a are disposed on the semiconductor fins 110a adjacent to both sides of the gate gap wall 122a, so the source / drain portions 112a and 114a and the n-type gate structure 100a together form an NMOS FinFET Device. The source / drain portions 112b and 114b are disposed on the semiconductor fins 110b adjacent to both sides of the gate gap wall 122b, so the source / drain portions 112b and 114b and the p-type gate structure 100b together form a PMOS FinFET Device. In some examples, the source / drain portions 112a and 114a contain silicon phosphide (SiP), and the source / drain portions 112b and 114b contain SiGe.

In some embodiments, the etch stop layer 120 is disposed on the gate spacer 122a, the source / drain portions 112a and 114a, the isolation structure 104, the gate spacer 122b, and the source / drain portions 112b and 114b. An inter-layer dielectric (ILD) 170 is disposed on the etching stop layer 120. The inner dielectric layer 170 may include silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and the like.

The n-type gate structure 100a includes an initial layer 130a, a high-k dielectric layer 140a, a metal cap layer 142a, a barrier metal layer 144a, a TiN layer 146a, an n-type work function metal layer 148a, a barrier metal layer 150a, and a metal fill. Layer 160a. The initial layer 130a is provided on the semiconductor fin 110a. In some examples, the initial layer 130a includes a silicon oxide layer. The high-permittivity dielectric layer 140a is disposed on the initial layer 130a and is surrounded by the gate spacer 122a. The thickness of the high-k dielectric layer 140a is between about 10 angstroms and about 20 angstroms. In some embodiments, the high dielectric constant dielectric layer 140a contains a high dielectric constant material, such as: HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof.

The metal capping layer 142a is on the high-k dielectric layer 140a, and is disposed between the high-k dielectric layer 140a and the n-type work function metal layer 148a. The metal cap layer 142a contains TiN and may have a thickness between about 10 Angstroms and about 30 Angstroms. The barrier metal layer 144a is on the metal capping layer 142a and is disposed between the metal capping layer 142a and the n-type work function metal layer 148a. The barrier metal layer 144a includes tantalum nitride (TaN) and may have a thickness between about 10 angstroms and about 30 angstroms. The TiN layer 146a is on the barrier metal layer 144a and is disposed between the barrier metal layer 144a and the n-type work function metal layer 148a, and may have a thickness between about 5 angstroms and about 20 angstroms. The metal capping layer 142a, the barrier metal layer 144a, and the TiN layer 146a are material layers for preventing impurities from entering below it. In a specific embodiment, only one or more of the metal capping layer 142a, the barrier metal layer 144a, and the TiN layer 146a are disposed between the high-k dielectric layer 140a and the n-type work function metal layer 148a. . It should be noted that the order of the metal capping layer 142a, the barrier metal layer 144a, and the TiN layer 146a can be changed without affecting their purpose.

The n-type work function metal layer 148a is on the TiN layer 146a and the high dielectric constant dielectric layer 140a, and may have a thickness between about 30 angstroms and about 100 angstroms. The n-type work function metal layer 148a includes a TiAl alloy or a TaAl alloy, and two surfaces of the n-type work function metal layer 148a are adjacent to the TiN layer 146a and the barrier metal layer 150a, respectively. From the results of EDS line scanning, it is known that for an n-type work function metal layer 148a containing a TiAl alloy, the atomic ratio of Ti to Al is substantially between 1 and 3. For an n-type work function metal layer 148a containing a TiAl alloy or a tantalum aluminum (TaAl) alloy, both surfaces of the n-type work function metal layer 148a contain an oxygen concentration of less than about 10 atomic percent (at%), and are close to or at The concentration of aluminum atoms on the two surfaces of the n-type work function metal layer 148a is higher than the concentration of aluminum atoms on the other portions of the n-type work function metal layer 148a. A large amount of aluminum separation (Al Segregation), thereby providing a work function metal layer with excellent properties. Oxygen causes a change in the work function of the n-type work function metal layer 148a, so a lower oxygen concentration can result in better quality of the n-type work function metal layer 148a.

The barrier metal layer 150a is on the n-type work function metal layer 148a to protect the n-type work function metal layer 148a. The barrier metal layer 150a includes TiN and may have a thickness between about 10 Angstroms and about 30 Angstroms. . The metal filling layer 160a fills a trench (not labeled), and its periphery is surrounded by the barrier metal layer 150a. The metal filling layer 160a may have a thickness between about 1000 angstroms and about 5000 angstroms. The metal filling layer 160a is configured to provide current transmission. In some embodiments, the metal filling layer 160a may be formed of, for example, tungsten, copper, or other suitable materials, and / or combinations thereof. The metal filling layer 160a is formed by using a fluorine-containing precursor, and the metal filling layer 160a is surrounded by a (first) stacked structure 180a, where the (first) stacked structure 180a includes a high-k dielectric layer 140a , Metal cover layer 142a, barrier metal layer 144a, TiN layer 146a, n-type work function metal layer 148a and barrier metal layer 150a, and it is known from the results of EDS line scanning that the sidewall of the stacked structure 180a contains substantially from 5 atomic percent To a fluorine concentration of 20 atomic percent, and the bottom of the stacked structure 180a contains a fluorine concentration of substantially 1 to 15 atomic percent. If the fluorine concentration in the sidewall of the stacked structure 180a is higher than about 20 atomic percent, a significant device shift may be caused. If the fluorine concentration in the sidewall of the stacked structure 180a is lower than about 5 atomic percent, the device performance will be less effective. Similarly, if the fluorine concentration at the bottom of the stacked structure 180a is higher than about 15 atomic percent, a significant device shift may be caused. If the fluorine concentration at the bottom of the stacked structure 180a is lower than about 1 atomic percent, the device performance will be less effective.

The p-type gate structure 100b includes an initial layer 130b, a high-k dielectric layer 140b, a metal cap layer 142b, a barrier metal layer 144b, a p-type work function metal layer 146b, a TiAl layer 148b, a barrier metal layer 150b, and a metal fill. Layer 160b. In some embodiments, a TaAl layer may be used in place of the TiAl layer 148b. The initial layer 130b is disposed on the semiconductor fin 110b. In some examples, the initial layer 130b includes a silicon oxide layer. The high-permittivity dielectric layer 140b is disposed on the initial layer 130b and is surrounded by the gate spacer 122b. The high-k dielectric layer 140b may have a thickness between about 10 Angstroms and about 20 Angstroms. In some embodiments, the high-k dielectric layer 140a contains a high-dielectric material, such as: HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof.

The metal capping layer 142b is on the high-k dielectric layer 140b, and is disposed between the high-k dielectric layer 140b and the p-type work function metal layer 146b. The metal cap layer 142b includes TiN and may have a thickness between about 10 angstroms and about 30 angstroms. The barrier metal layer 144b is on the metal capping layer 142b and is disposed between the metal capping layer 142b and the p-type work function metal layer 146b. The barrier metal layer 144b includes TaN and may have a thickness between about 10 Angstroms and about 30 Angstroms. The metal capping layer 142b and the barrier metal layer 144b are material layers for preventing impurities from entering below. In a specific embodiment, only one or more of the metal capping layer 142b and the barrier metal layer 144b are disposed between the high-k dielectric layer 140b and the p-type work function metal layer 146b. It should be noted that the order of the metal capping layer 142b and the barrier metal layer 144b can be changed without affecting their purpose.

The p-type work function metal layer 146b is on the barrier metal layer 144b and may have a thickness between about 5 angstroms and about 20 angstroms. The p-type work function metal layer 146b contains TiN. It is known from the EDS scanning that the atomic ratio of Ti to N is substantially between 1: 0.9 and 1: 1.1, and the p-type work function metal layer 146b contains less than about An oxygen concentration of 10 atomic percent (at%) can provide a work function metal layer having excellent properties. Oxygen causes the work function of the p-type work function metal layer 146b to change, so a lower oxygen concentration can lead to better quality of the p-type work function metal layer 146b.

The TiAl layer 148b is on the p-type work function metal layer 146b and is disposed between the p-type work function metal layer 146b and the barrier metal layer 150b, and the TiAl layer 148b may have a thickness between about 30 angstroms and about 100 angstroms. . The barrier metal layer 150b is on the TiAl layer 148b to protect the TiAl layer 148b and the p-type work function metal layer 146b. The barrier metal layer 150b includes TiN and may have a thickness between about 10 angstroms and about 30 angstroms. . The metal filling layer 160b fills a trench (not labeled), the periphery of the trench is surrounded by the barrier metal layer 150b, and the metal filling layer 160b may have a thickness between about 1000 angstroms and about 5000 angstroms. The metal filling layer 160b is configured to provide current transmission. In some embodiments, the metal filling layer 160b may be formed of tungsten, copper, or other suitable materials, and / or a combination thereof. The metal filling layer 160b is formed by using a fluorine-containing precursor (for example, tungsten hexafluoride (WF ₆ )), and the metal filling layer 160b is surrounded by a (second) stack structure 180b, in which the (second) stack The structure 180b includes a high-k dielectric layer 140b, a metal capping layer 142b, a barrier metal layer 144b, a TiN layer 146b, an n-type work function metal layer 148b, and a barrier metal layer 150b. According to the EDS line scan, the stacked structure The sidewall of 180b contains a fluorine concentration of substantially from 5 to 20 atomic percent, and the bottom of the stacked structure 180b contains a fluorine concentration of substantially from 1 to 15 atomic percent. If the fluorine concentration of the sidewall of the stacked structure 180b is higher than about 20 atomic percent, a significant device shift may be caused. If the fluorine concentration in the sidewall of the stacked structure 180b is lower than about 5 atomic percent, the device performance will be less effective. Similarly, if the fluorine concentration at the bottom of the stacked structure 180b is higher than about 15 atomic percent, a significant device shift may be caused. If the fluorine concentration at the bottom of the stacked structure 180b is lower than about 1 atomic percent, the device performance will be less effective.

The high-k dielectric layer 140a and the high-k dielectric layer 140b may be formed of the same material layer; the metal capping layer 142a and the metal capping layer 142b may be formed of the same material layer; the barrier metal layer described above 144a and barrier metal layer 144b may be formed of the same material layer; the aforementioned TiN layer 146a and p-type work function metal layer 146b may be formed of the same material layer; the aforementioned n-type work function metal layer 148a and TiAl layer 148b may be formed of the same material The metal barrier layer 150a and the metal barrier layer 150b may be formed of the same material layer; and the metal filler layer 160a and the metal filler layer 160b may be formed of the same material layer.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A and FIG. 2B are cross-sectional views illustrating a semiconductor device according to some embodiments of the present disclosure. This semiconductor device includes a semiconductor substrate 202, a semiconductor fin 210a, a semiconductor fin 210b, an n-type gate structure 200a, and a p-type gate structure 200b. The semiconductor fin 210 a and the semiconductor fin 210 b are disposed on the semiconductor substrate 202 and separated by an isolation structure 204. In some embodiments, the isolation structure 204 is shallow trench isolation (STI). The semiconductor substrate 202 is defined as any structure containing a semiconductor material, including, but not limited to, a bulk silicon, a semiconductor wafer, or a silicon germanium substrate. Other semiconductor materials containing Group III, Group IV, and Group V elements can be used. The semiconductor fins 210 a and 210 b protrude from the semiconductor substrate 202. The gate spacer 222a is formed on a side wall of the n-type gate structure 200a, and the gate spacer 222b is formed on a side wall of the p-type gate structure 200b. The gate spacer 222a and the gate spacer 222b include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The source / drain portions 212a and 214a are disposed on the semiconductor fin 210a and are adjacent to both sides of the gate spacer 222a, so the source / drain portions 212a and 214a are formed together with the n-type gate structure 200a An NMOS FinFET device. The source / drain portions 212b and 214b are disposed on the semiconductor fin 210b and are adjacent to both sides of the gate spacer 222b. Therefore, the source / drain portions 212b and 214b are formed with the p-type gate structure 200b A PMOS FinFET device. In some examples, the source / drain portions 212a and 214a include SiP, and the source / drain portions 212b and 214b include SiGe.

In some embodiments, the etch stop layer 220 is disposed on the gate spacer 222a, the source / drain portions 212a and 214a, the isolation structure 204, the gate spacer 222b, and the source / drain portions 212b and 214b. The inner dielectric layer 270 is disposed on the etch stop layer 220. The inner dielectric layer 270 includes silicon oxide, phosphosilicate glass, borophosphosilicate glass, and the like.

The n-type gate structure 200a includes an initial layer 230a surrounded by a gate spacer 222a, and the p-type gate structure 200b includes an initial layer 230b surrounded by a gate spacer 222b. Each of the n-type gate structure 200a and the p-type gate structure 200b includes an initial layer 230a, a high-k dielectric layer 240, a TiN layer 242, a TaN layer 244, a TiN layer 246, a TiAl layer 248, and a TiN layer 250. And metal fill layer 260. The initial layer 230a is disposed on the semiconductor fin 210a, and the initial layer 230b is disposed on the semiconductor fin 210b. Each of the initial layer 230a and the initial layer 230b includes a silicon oxide layer. The high-k dielectric layer 240 may have a thickness between about 10 Angstroms and about 20 Angstroms. In some embodiments, the high-k dielectric layer 240 contains a high-dielectric material, such as: HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof.

The TiN layer 242 is on the high dielectric constant dielectric layer 240 and may have a thickness between about 10 angstroms and about 30 angstroms. The TaN layer 244 is on the TiN layer and may have a thickness between about 10 Angstroms and about 30 Angstroms. The TiN layer 246 is on the TaN layer 244 and may have a thickness between about 5 Angstroms and about 20 Angstroms. The TiN layer 242 and the TaN layer 244 are material layers used to prevent impurities from entering below. In a specific embodiment, only one or more of the TiN layer 242 and the TaN layer 244 are disposed on the high-k dielectric layer 240. It should be noted that the order of the TiN layer 242 and the TaN layer 244 can be changed without affecting their purpose.

The TiAl layer 248 is on the TiN layer 246 and the high-k dielectric layer 240, and the TiAl layer 248 may have a thickness between about 30 angstroms and about 100 angstroms. The TiN layer 250 is on the TiAl layer 248 to protect the underlying material layer, and the TiN layer 250 may have a thickness between about 10 angstroms and about 30 angstroms. The metal filling layer 260 fills the trench (not labeled), and its periphery is surrounded by the TiN layer 250, and the metal filling layer 260 may have a thickness between about 1000 angstroms and about 5000 angstroms. The metal filling layer 260 is formed by using a fluorine-containing precursor (for example, WF ₆ ), and the metal filling layer 260 is surrounded by a stacked structure 280, where the stacked structure 280 includes a high-k dielectric layer 240 and a TiN layer. 242, TaN layer 244, TiN layer 246, TiAl layer 248, and TiN layer 250, and it is known from the EDS line scan that the sidewall of the stacked structure 280 contains a fluorine concentration that is substantially from 5 to 20 atomic percent, and the stacked structure 280 The bottom contains a fluorine concentration of substantially from 1 atomic percent to 15 atomic percent. If the fluorine concentration on the sidewall of the stacked structure 280 is higher than about 20 atomic percent, it may cause a significant device shift. If the fluorine concentration of the sidewall of the stacked structure 280 is less than about 5 atomic percent, the device performance will be less effective. Similarly, if the fluorine concentration at the bottom of the stacked structure 280 is higher than about 15 atomic percent, a significant device shift may result. If the fluorine concentration at the bottom of the stacked structure 280 is less than about 1 atomic percent, the device performance will be less effective. The metal fill layer 260 is configured to provide current transmission. In some embodiments, the metal filling layer 260 may be formed of tungsten, copper, or other suitable materials, and / or combinations thereof. Chemical mechanical polishing (CMP) is performed on the metal filling layer 260 shown in FIG. 2A until the gate spacer 222a and the gate spacer 222b are exposed, as shown in FIG. 2B. Therefore, NMOS FinFET devices (source / drain portions 212a and 214a and n-type gate structure 200a) and PMOS FinFET devices (source / drain portions 212b and 214b and p-type gate structure 200b) can be formed simultaneously, This simplifies the manufacturing process.

The TiAl layer 248 surrounded by the gate spacer 222a is an n-type work function metal layer, and two surfaces of the n-type work function metal layer are adjacent to the TiN layer 246 and the TiN layer 250, respectively. From the results of the EDS scan line, it is known that the atomic ratio of Ti to Al is substantially between 1 and 3, and the two surfaces of the n-type work function metal layer contain an oxygen concentration substantially lower than 10 atomic percent (at%). And the aluminum atom concentration near or on the two surfaces of the n-type work function metal layer is higher than that of other parts of the n-type work function metal layer, that is, near or in the n-type work function metal layer There is more aluminum separation on the two surfaces. In some embodiments, the TaAl layer may replace the TiAl layer 248 as an n-type work function metal layer. The TiN layer 246 surrounded by the gate spacer 222b is a p-type work function metal layer, wherein the atomic ratio of Ti to N is substantially between 1: 0.9 to 1: 1.1, and the p-type work function metal layer contains substantially lower than An oxygen concentration of 10 atomic percent (at%). According to the above EDS characteristics, a work function metal layer having excellent properties can be provided.

Please refer to FIGS. 3A to 3G. FIGS. 3A to 3G are schematic cross-sectional views of an intermediate stage of manufacturing a semiconductor device according to some embodiments in the present disclosure.

As shown in FIG. 3A, a semiconductor substrate 302 is provided, and the semiconductor substrate 302 is patterned and etched using a lithography technique to form a semiconductor fin 310 a and a semiconductor fin 310 b separated by an isolation structure 304. The semiconductor substrate 310 is defined as any structure containing a semiconductor material, including, but not limited to, a bulk silicon, a semiconductor wafer, or a silicon germanium substrate. Other semiconductor materials including Group III, Group IV, and Group V elements can be used. In some embodiments, a photoresist material layer (not shown) is deposited on the semiconductor substrate 310, and the photoresist material layer is illuminated (exposed) according to a desired pattern. The photoresist material layer is developed to remove a portion of the light.阻 材料。 Resistance material. The remaining photoresist material protects the material below it from being damaged by subsequent processing operations, such as etching. It should be noted that other photomasks (such as oxide or silicon nitride photomasks) can also be used in the etching process. In other embodiments, semiconductor fins 310a and 310b can be epitaxially grown. For example, the exposed portion of the underlying material (for example, the exposed portion of the semiconductor substrate 210) can be used in an epitaxial process to form the semiconductor fins 310a and 310b. A mask may be used to control the shapes of the semiconductor fins 310a and 310b in the epitaxial growth process.

A polycrystalline silicon gate 380a is formed on the semiconductor fin 310a, and a polycrystalline silicon gate 380b is formed on the semiconductor fin 310b. A gate spacer 322a is formed on the side wall of the polycrystalline silicon gate 380a, and a gate spacer 322b is formed on the side wall of the polycrystalline silicon gate 380b. The gate spacer 322a and the gate spacer 322b may include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The source / drain portions 312a and 314a are formed on the semiconductor fin 310a and adjacent to both sides of the gate spacer 322a. The source / drain portions 312b and 314b are formed on the semiconductor fin 310b and adjacent to both sides of the gate spacer 322b. In some examples, the source / drain portions 312a and 314a include SiP, and the source / drain portions 312b and 314b include SiGe. In some embodiments, an etch stop layer 320 is formed on the gate spacers 322a, source / drain portions 312a and 314a, isolation structures 304, gate spacers 322b, and source / drain portions 312b and 314b. An inner dielectric layer 370 is formed on the etch stop layer 320. The ILD layer 370 includes silicon oxide, phosphosilicate glass, borophosphosilicate glass, and the like.

Then, as shown in FIG. 3B, a portion of the ILD layer 370 is removed using, for example, wet or dry etching to expose the etch stop layer 320. Next, as shown in FIG. 3C, the etching stop layer 320 and the polysilicon gate 380a and the polysilicon gate 380b are removed using, for example, wet or dry etching. Then, as shown in FIG. 3D, an initial layer 330a is formed on the semiconductor fin 310a, and an initial layer 330b is formed on the semiconductor fin 310b. In some examples, each of the initial layer 330a and the initial layer 330b contains a silicon oxide layer, which may be formed using chemical vapor deposition (CVD), thermal oxidation, ozone oxidation, or other processes. .

Then, as shown in FIG. 3E, a high dielectric constant dielectric layer 340 is deposited on the initial layer 330a and the initial layer 330b using atomic layer deposition (ALD) or other suitable techniques. The high-k dielectric layer 340 may have a thickness between about 10 Angstroms and about 20 Angstroms. In some embodiments, the high-k dielectric layer 340 includes a high-dielectric material, such as: HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof.

TiN layer 342 is deposited on high dielectric constant dielectric layer 340 using ALD or other suitable techniques, and TiN layer 342 may have a thickness between about 10 Angstroms and about 30 Angstroms. The TaN layer 344 is deposited on the TiN layer 342 using ALD or other suitable techniques, and the TaN layer 344 may have a thickness between about 10 Angstroms and about 30 Angstroms. TiN layer 346 is deposited on TaN layer 344 using ALD or other suitable techniques, and TiN layer 346 may have a thickness between about 5 angstroms and about 20 angstroms. The TiN layer 342 and the TaN layer 344 are material layers for preventing impurities from entering below. In a particular embodiment, only one or more of the TiN layer 342 and the TaN layer 344 are deposited on the high-k dielectric layer 340. It should be noted that the order of the TiN layer 342 and the TaN layer 344 can be changed without affecting its purpose. The TiAl layer 348 is deposited on the TiN layer 346 and the high-k dielectric layer 340 using ALD or other suitable techniques. The TiAl layer 348 may have a thickness between about 30 Angstroms and about 100 Angstroms. In some embodiments, a TaAl layer may be used in place of the TiAl layer 348. The TiN layer 350 is formed on the TiAl layer 348 using ALD or other suitable techniques to protect the material layer below it. The TiN layer 350 may have a thickness between about 10 Angstroms and about 30 Angstroms.

Then, as shown in FIG. 3F, the metal filling layer 360 is filled into the trenches (not labeled) by using CVD, ALD, Metal-organic Chemical Vapor Deposition (MOCVD) or other suitable techniques, wherein The trench is surrounded by a TiN layer 350. The metal filling layer 360 is formed by using a fluorine-containing precursor (for example, WF ₆ ). The metal fill layer 360 is configured to provide current transmission. In some embodiments, the metal fill layer 360 may be formed of tungsten, copper, or other suitable materials, and / or combinations thereof.

Then, as shown in FIG. 3G, the metal filling layer 360 is chemically and mechanically polished until the gate spacer 322a and the gate spacer 322b are exposed. The metal fill layer 360 may have a thickness between about 1000 Angstroms and about 5000 Angstroms. Therefore, both the NMOS FinFET device (source / drain portions 312a and 314a and the n-type gate structure 300a surrounded by the gate spacer 322a) and the PMOS FinFET device (source / drain portions 312b and 314b and The p-type gate structure 300b) surrounded by the gate gap wall simplifies the manufacturing process.

The TiAl layer 348 surrounded by the gate spacer 322a is an n-type work function metal layer, and two surfaces of the n-type work function metal layer are adjacent to the TiN layer 346 and the TiN layer 350, respectively. From the results of the EDS scan line, it is known that the atomic ratio of Ti to Al is substantially between 1 and 3, and the two surfaces of the n-type work function metal layer contain an oxygen concentration substantially lower than 10 atomic percent (at%). The aluminum atom concentration near or on the two surfaces of the TiAl layer 348 is higher than the aluminum atom concentration on the other parts of the TiAl layer 348, that is, there is more aluminum separation near or on the two surfaces of the TiAl layer 348. The TiN layer 346 surrounded by the gate spacer 322b is a p-type work function metal layer, in which the atomic ratio of Ti to N is substantially between 1: 0.9 and 1: 1.1, and the p-type work function metal layer contains oxygen The concentration is substantially less than 10 atomic percent (at%). According to the above EDS characteristics, a work function metal layer having excellent properties can be provided.

Please refer to FIG. 4 and FIG. 3G. FIG. 4 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. The method starts with operation 400, in which semiconductor fins 310 a (first semiconductor fins) and semiconductor fins 310 b (second semiconductor fins) are formed on a semiconductor substrate 302 and separated by an isolation structure 304. In operation 410, the initial layer 330a (the first initial layer) is surrounded by the gate gap wall 322a (the first gate gap wall) and is formed on the semiconductor fin 310a, and the initial layer 330b (the second initial layer) ) Is surrounded by the gate gap wall 322b (second gate gap wall), and is formed on the semiconductor fin 310b. In operation 420, a high-k dielectric layer 340 is deposited on the initial layers 330a and 330b. In operation 430, a TiN layer 342 (first TiN layer) is deposited on the high-k dielectric layer 320. In operation 440, the TaN layer 344 is over the TiN layer 342. In operation 450, a TiN layer 346 (a second TiN layer) is deposited on the TaN layer 344. In operation 460, a TiAl layer 348 is deposited on the TiN layer 346. In operation 470, a TiN layer 350 (a third TiN layer) is deposited on the TiAl layer 348. In operation 480, by using the fluorine-containing precursor (e.g., WF ₆₎ surrounding the periphery of a metal is deposited TiN layer 350 filling layer 360. The metal filling layer 360 is formed by using a fluorine-containing precursor (for example, WF ₆ ), and the metal filling layer 360 is surrounded by a stacked structure 390, wherein the stacked structure 390 includes a high-k dielectric layer 340 and a TiN layer. 342, TaN layer 344, TiN layer 346, TiAl layer 348, and TiN layer 350, and it is known from the EDS line scan that the sidewall of the stacked structure 390 contains a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and the stacked structure 390 The bottom contains a fluorine concentration of substantially from 1 atomic percent to 15 atomic percent. If the fluorine concentration of the sidewall of the stacked structure 390 is higher than about 20 atomic percent, it may cause a significant device shift. If the fluorine concentration on the sidewall of the stacked structure 390 is less than about 5 atomic percent, the device performance will be less effective. Similarly, if the fluorine concentration at the bottom of the stacked structure 390 is higher than about 15 atomic percent, a significant device shift may result. If the fluorine concentration at the bottom of the stacked structure 390 is less than about 1 atomic percent, the device performance will be less effective.

The TiAl layer 348 surrounded by the gate spacer 322a is used as an n-type work function metal layer, wherein the atomic ratio of Ti to Al is substantially between 1 and 3, and the two surfaces of the n-type work function metal layer contain substantially lower surfaces. Oxygen concentration at 10 atomic percent (at%), and the aluminum atom concentration near or on the surface of the TiAl layer 348 bis is higher than that of other parts of the TiAl layer 348, that is, near or on the two surfaces of the TiAl layer 348 There is more aluminum separation. In some embodiments, the TaAl layer may replace the TiAl layer 348 as an n-type work function metal layer. The TiN layer 346 surrounded by the gate gap wall 322b serves as a p-type work function metal layer, wherein the atomic ratio of Ti to N is substantially between 1: 0.9 and 1: 1.1, and the p-type work function metal layer contains a substantial Oxygen concentration below 10 atomic percent (at%).

According to some embodiments, the semiconductor device includes a semiconductor substrate; a first semiconductor fin on the semiconductor substrate; and an n-type gate structure disposed on the first semiconductor fin. The barrier metal layer contains TiN. The n-type gate structure is combined with fluorine and includes a first initial layer disposed on the first semiconductor fin; a first high dielectric constant dielectric disposed on the first initial layer and surrounding the first gate gap wall Layer; an n-type work function metal layer disposed on the first high-k dielectric layer, wherein the n-type work function metal layer contains a TiAl alloy, and the atomic ratio of Ti to Al is substantially between 1 and 3; A barrier metal layer on the n-type work function metal layer; and a first metal filling layer surrounded by the barrier metal layer, so that the first metal filling layer is surrounded by the first stacked structure, wherein a sidewall of the first stacked structure The fluorine concentration is substantially 5 atomic percent to 20 atomic percent, and the bottom of the first stacked structure includes the fluorine concentration substantially 1 atomic percent to 15 atomic percent.

According to other embodiments, a semiconductor device includes a semiconductor substrate; a first semiconductor fin and a second semiconductor fin on the semiconductor substrate; an n-type gate structure; and a p-type gate structure. The first semiconductor fin and the second semiconductor fin are separated by an isolation structure. The n-type gate structure is combined with fluorine and includes a first initial layer disposed on the first semiconductor fin and is surrounded by the first gate gap. The p-type gate structure is combined with fluorine and contains a A second initial layer on the second semiconductor fin and surrounded by the second gate spacer. Each of the n-type gate structure and the p-type gate structure includes a high dielectric constant dielectric layer disposed on the first initial layer and the second initial layer; and a first TiN disposed on the high dielectric constant dielectric layer. A TaN layer provided on the first TiN layer; a second TiN layer provided on the TaN layer; a TiAl layer provided on the second TiN layer; a third TiN layer provided on the TiAl layer; A metal filling layer of the third TiN layer so that the metal filling layer is surrounded by the stacked structure, wherein the sidewall of the stacked structure includes a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and the bottom of the second stacked structure includes substantially Fluorine concentration from 1 atomic percent to 15 atomic percent. The TiAl layer surrounded by the first gate gap wall is used as an n-type work function metal layer, and its atomic ratio of Ti to Al is substantially between 1 and 3. The second TiN layer surrounded by the second gate gap wall is used as a p-type work function metal layer, and its atomic ratio of Ti to N is substantially between 1: 0.9 and 1: 1.1.

According to some embodiments, a method includes forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure. The first initial layer is surrounded by the first gate gap wall and is formed on the first semiconductor fin, and the second initial layer is surrounded by the second gate gap wall and is formed on the second semiconductor fin. A high-k dielectric layer is deposited on the first and second initial layers. A first TiN layer is deposited on the high-k dielectric layer. A TaN layer is deposited on the first TiN layer. A second TiN layer is deposited on the TaN layer. A TiAl layer is deposited on the second TiN layer. A third TiN layer is deposited on the TiAl layer. A metal-filled layer surrounded by a third TiN layer is deposited by using a fluorine-containing precursor (eg, WF ₆ ). Then, for example, by performing a thermal process, the fluorine system diffuses to the stacked structure surrounding the metal filling layer, so that the sidewall of the stacked structure contains a fluorine concentration substantially from 5 atomic percent to 15 atomic percent, and the bottom of the stacked structure contains substantial It is a fluorine concentration from 1 atomic percent to 15 atomic percent. The TiAl layer surrounded by the first gate gap wall is used as the n-type work function metal layer, and the atomic ratio of Ti to Al ranges from 1 to 3. The second TiN layer surrounded by the second gate gap wall is used as the p-type work function metal layer, and its atomic ratio of Ti to N ranges substantially from 1: 0.9 to 1: 1.1.

The foregoing outlines the features of many embodiments, making it easier for those having ordinary skill in the art to understand the aspects of the present disclosure. Those with ordinary knowledge in this technical field should understand that they can design or modify other processes and structures based on this disclosure to achieve the same purpose and / or achieve the same advantages as in these embodiments. Those with ordinary knowledge in this technical field should also understand that such an equivalent structure does not deviate from the spirit and scope of this disclosure, and they may be able to make various changes, substitutions and changes without departing from the spirit and scope of this disclosure. range.

Claims (10)

A semiconductor device includes: a semiconductor substrate; a first semiconductor fin on the semiconductor substrate; and an n-type gate structure on the first semiconductor fin, wherein the n-type gate structure is combined Fluorine, and the n-type gate structure includes: a first initial layer on the first semiconductor fin; a first high-k dielectric layer on the first initial layer and a first gate Surrounded by a gap wall; an n-type work function metal layer disposed on the first high-permittivity dielectric layer, the n-type work function metal layer comprising a titanium aluminum (TiAl) alloy or a tantalum aluminum (TaAl) alloy, wherein When the n-type work function metal layer includes the titanium aluminum alloy, the atomic ratio of titanium to aluminum ranges substantially from 1 to 3; a first barrier metal layer is disposed on the n-type work function metal layer; and The first metal filling layer is surrounded by the first barrier metal layer, so that the first metal filling layer is surrounded by a first stacked structure, wherein one side wall of the first stacked structure contains substantially 5 atomic percent To 20 atomic percent fluorine concentration, and the first pile The bottom of one of the structures which contain substantial percentage of atoms from 1 to 15 atoms in the fluorine concentration percentages. The semiconductor device according to item 1 of the patent application scope, wherein the n-type gate structure further includes: a metal capping layer interposed between the first high-k dielectric layer and the n-type work function metal layer Wherein the metal cover layer includes titanium nitride (TiN); a barrier metal layer is interposed between the metal cover layer and the n-type work function metal layer, wherein the barrier metal layer includes tantalum nitride (TaN) And a titanium nitride layer between the barrier metal layer and the n-type work function metal layer. The semiconductor device according to item 1 of the scope of patent application, further comprising: a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure. Separate; a p-type gate structure is located on the second semiconductor fin, wherein the p-type gate structure is combined with fluorine and includes: a second initial layer on the second semiconductor fin; a second high dielectric The dielectric constant dielectric layer is located on the second initial layer and is surrounded by a second gate gap wall; a p-type work function metal layer is disposed on the second high-dielectric constant dielectric layer, and the p-type The work function metal layer includes titanium nitride, wherein the atomic ratio of titanium to nitrogen is substantially between 1: 0.9 and 1: 1.1; a second barrier metal layer is disposed on the p-type work function metal layer; and a first Two metal filling layers, the second barrier metal layer is surrounded by the periphery, so that the second metal filling layer is surrounded by a second stacked structure, wherein one side wall of the second stacked structure includes substantially from 5 atomic percent to 20 atomic percent fluorine concentration, and the second One of the base structure comprises a substantial stack of from 1 atomic percent to 15 atomic fluorine concentration percentages. According to the semiconductor device described in item 3 of the patent application scope, the p-type gate structure further includes: a titanium aluminum alloy layer disposed between the p-type work function metal layer and the second barrier metal layer; a metal cover layer Between the first high-k dielectric layer and the p-type work function metal layer, wherein the metal capping layer contains titanium nitride; and a barrier metal layer between the metal capping layer and the p Between work-type metal layers, wherein the barrier metal layer contains tantalum nitride. The semiconductor device according to item 3 of the application, wherein the first metal filling layer or the second metal filling layer contains tungsten. A semiconductor device includes: a semiconductor substrate; a first semiconductor fin and a second semiconductor fin on the semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure A n-type gate structure includes a first initial layer, the first initial layer is located on the first semiconductor fin and is surrounded by a first gate spacer, and a p-type gate structure includes a first Two initial layers, the second initial layer is located on the second semiconductor fin and is surrounded by a second gate spacer; each of the n-type gate structure and the p-type gate structure is bound to fluorine, and Including: a high-k dielectric layer on the first initial layer and the second initial layer; a first titanium nitride layer disposed on the high-k dielectric layer; a tantalum nitride layer, Disposed on the first titanium nitride layer; a second titanium nitride layer disposed on the tantalum nitride layer; a titanium aluminum alloy layer disposed on the second titanium nitride layer; a third titanium nitride Layer on the titanium-aluminum alloy layer; and a metal filling layer surrounded by the first A titanium trinitride layer so that the metal filling layer is surrounded by a stacked structure, wherein one side wall of the stacked structure includes a fluorine concentration substantially from 5 atomic percent to 20 atomic percent, and a bottom of one of the second stacked structure It includes a fluorine concentration substantially from 1 atomic percent to 15 atomic percent; wherein the titanium aluminum alloy layer surrounded by the first gate spacer is an n-type work function metal layer, wherein the atomic ratio of titanium to aluminum is substantially 1 to 3; and the second titanium nitride layer surrounded by the second gate spacer is a p-type work function metal layer, wherein the atomic ratio of titanium to nitrogen is substantially between 1: 0.9 to 1: 1.1 between. The semiconductor device according to item 6 of the scope of patent application, wherein the p-type work function metal layer contains an oxygen concentration of substantially less than 10 atomic percent, and the two surfaces of the n-type work function metal layer contain substantially less than 10 atomic percent of The oxygen concentration, the aluminum atom concentration near or on the two surfaces of the n-type work function metal layer is higher than the aluminum atom concentration of other parts of the n-type work function metal layer, and the two surfaces of the n-type work function metal layer Are adjacent to the second titanium nitride layer and the third titanium nitride layer, respectively. A method for manufacturing a semiconductor device includes forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by an isolation structure. ; Depositing a first initial layer on the first semiconductor fin, the first initial layer is surrounded by a first gate spacer, and depositing a second initial layer on the second semiconductor fin, the second initial The layer is surrounded by a second gate gap wall; a high dielectric constant dielectric layer is deposited on the first initial layer and the second initial layer; a first titanium nitride is deposited on the high dielectric constant dielectric Depositing a tantalum nitride layer on the first titanium nitride layer; depositing a second titanium nitride layer on the tantalum nitride layer; depositing a titanium aluminum alloy layer on the second titanium nitride layer; depositing A third titanium nitride layer on the titanium aluminum alloy layer; and a metal filling layer surrounding the third titanium nitride layer by using a fluorine-containing precursor to deposit the periphery; and diffusing fluorine to the metal filling layer surrounding the metal filling layer A stacked structure so that one side wall of the stacked structure contains solid As a percentage of atoms from 5 to 15 atomic percentages fluorine concentration, and the bottom one of the stacked structure containing a substantial percentage of atoms from 1 to 15 atoms in the fluorine concentration percentages. The method for manufacturing a semiconductor device according to item 8 of the scope of patent application, wherein the first titanium nitride layer, the second titanium nitride layer, the third titanium nitride layer, the tantalum nitride layer, and the titanium are deposited. The steps of the aluminum alloy layer and the metal filling layer are performed by atomic layer deposition. The method for manufacturing a semiconductor device according to item 8 of the scope of patent application, wherein the fluorine-containing precursor is tungsten hexafluoride (WF ₆ ).