TWI650745B - Display device and gate drive array control circuit therefor - Google Patents

Abstract

The present invention provides a display device including a timing control circuit and a gate drive array (GOA) control circuit. The timing control circuit is used to generate a picture synchronization signal. The GOA control circuit is coupled to the timing control circuit and includes a scanning signal management circuit. It is used to generate the scanning signal management signal according to the screen synchronization signal, the preset panel parameters and the operating clock signal; the scanning signal management circuit includes a storage unit for storing the preset panel parameters; and the level shift circuit, according to The scanning signal management signal generates a scanning control signal for controlling the gate driving array of the display panel circuit. The gate driving array generates a gate driving signal according to the scanning control signal to control the vertical scanning operation of the display panel circuit.

Description

Display device and gate driving array control circuit therein

The present invention relates to a display device, and more particularly to a display device with fewer signal lines. The present invention also relates to a gate drive array control circuit used in a display device.

The previous cases related to this case are: US patents US9595219B2, US7471286B2 and US9013468B2.

In FIG. 1, the US patent US9595219B2 discloses a prior art display device (display device 1), in which a timing controller (Tcon) 110 controls a level shifter 130 to generate a scanning signal management signal (for example, as shown in the figure). The signals (such as CLK, VST, and VRST shown) are used to control the gate drive array (GOA) 140 to generate the gate drive signal GL to control the vertical scanning operation of the display panel unit 100A. The display panel 100 includes a plurality of display panel units 100A arranged in a two-dimensional array of a plurality of horizontal rows and a plurality of vertical columns; the so-called vertical scanning operation refers to the steps of Vertically, select a scan operation for different columns.

The disadvantage of the prior art shown in FIG. 1 is that the output signal of the timing controller 110 has a one-to-one correspondence with the scanning signal management signal. Therefore, in the display panel application with higher resolution, the timing Signal line between controller 110 and level shifter 130 The number will also increase significantly, which will increase the cost and difficulty of circuit design. In addition, such display device architectures are generally applied to a single form display panel with fixed preset panel parameters. If the architecture is to be applied to multiple forms of display panels, the timing controller 110 will be used. The cost has increased significantly.

Compared with the prior art of FIG. 1, the present invention has high flexibility, can be applied to various forms of display panels, and can reduce the cost of the overall display device.

In one aspect, the present invention provides a display device including: a timing control circuit for generating a picture synchronization signal; and a gate drive array (GOA) control circuit coupled to the timing control circuit, including: : A scanning signal management circuit for generating a scanning signal management signal according to the screen synchronization signal, a preset panel parameter and an operating clock signal; wherein the scanning signal management circuit includes a storage unit for storing the Preset panel parameters; and a quasi-displacement circuit that generates a scan control signal based on the scan signal management signal to control a gate drive array of a display panel circuit, wherein the gate drive array is based on the scan control The signal generates a gate driving signal for controlling a vertical scanning operation of one of the display panel circuits.

In a preferred embodiment, the GOA control circuit further includes an oscillator for generating the operating clock signal.

In a preferred embodiment, the timing control circuit provides the operating clock signal.

In a preferred embodiment, the operation clock signal is not provided from outside the GOA control circuit.

In a preferred embodiment, the operation clock signal is synchronized with the picture synchronization signal.

In a preferred embodiment, the operation clock signal is synchronized or not synchronized with a vertical scanning frequency of the display panel circuit.

In a preferred embodiment, the preset panel parameters are one of: (1) a fixed value; (2) an optional fixed value; and (3) an adjustable value, wherein the preset The panel parameters are written into the storage unit by a user in a setting stage.

In a preferred embodiment, the scan control signal includes at least one of the following: (1) a GOA phase control signal for controlling the phase and waveform of the gate driving signal; (2) a durability control signal for To control the durability operation of one of the gate drive signals; and (3) a shutdown signal to control one of the gate drive signals to shut down.

In a preferred embodiment, the preset panel parameters include at least one of: (1) a phase number of the GOA phase control signal; (2) a phase overlay parameter of the GOA phase control signal; (3) ) One of the transient waveform parameters of the GOA phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter.

In a preferred embodiment, the scanning signal management circuit further includes at least one of the following units: a phase number control unit for determining the phase number of the GOA phase control signal; and a phase overlay control unit for adjusting the The degree of phase overlay of the GOA phase control signal; a transient control unit to control the transient waveform of the GOA phase control signal; an interval control unit to control a horizontal interval time or a vertical interval time; A durability control unit is used to generate the durability control signal; and a shutdown control unit is used to generate the shutdown signal.

In a preferred embodiment, the signal line between the timing control circuit and the GOA control circuit does not include (1) a signal line directly corresponding to the GOA phase control signal, and (2) a signal line directly corresponding to the durability control signal. , Or (3) a signal directly corresponding to the shutdown signal.

In another aspect, the present invention also provides a gate drive array (GOA) control circuit for a display device. The display device includes: a timing control circuit for producing Generating a picture synchronization signal; the GOA control circuit is coupled to the timing control circuit; the GOA control circuit includes: a scanning signal management circuit for using the picture synchronization signal, a preset panel parameter and an operating clock signal A scanning signal management signal is generated; the scanning signal management circuit includes a storage unit for storing the preset panel parameters; and a quasi-displacement circuit generates a scanning control signal according to the scanning signal management signal. To control a gate driving array of a display panel circuit, the gate driving array generates a gate driving signal according to the scan control signal to control a vertical scanning operation of the display panel circuit.

Detailed descriptions will be provided below through specific embodiments to make it easier to understand the purpose, technical content, features and effects of the present invention.

1,2,5,6‧‧‧‧display device

10‧‧‧sequence control circuit

20,20’‧‧‧GOA control circuit

21‧‧‧Scan signal management circuit

211‧‧‧Storage unit

22‧‧‧level shift circuit

23‧‧‧ Oscillator

212‧‧‧phase number control unit

213‧‧‧Phase Overlap Control Unit

214‧‧‧Transient Control Unit

215‧‧‧Interval control unit

216‧‧‧ Durability Control Unit

217‧‧‧ Shutdown Control Unit

30‧‧‧display panel circuit

31‧‧‧Gate Drive Array

32‧‧‧display panel unit

CKV_GOAm‧‧‧GOA phase control signal

CKV_GOAxP‧‧‧GOA phase control signal

CKV_GOAxN‧‧‧GOA phase control signal

CLK‧‧‧ Operation clock signal

FS‧‧‧Screen sync signal

GL‧‧‧Gate driving signal

LECn‧‧‧ Durability Control Signal

POFF‧‧‧ shutdown signal

SCS‧‧‧Scan control signal

SSM‧‧‧Scan Signal Management Signal

FIG. 1 shows a block diagram of a prior art display device.

FIG. 2 is a block diagram showing an embodiment of a display device of the present invention.

Figures 3A-3C show waveforms of the display device of the present invention.

FIG. 4 is a schematic diagram of an embodiment of a GOA control circuit in a display device of the present invention.

FIG. 5 is a block diagram showing an embodiment of a display device of the present invention.

FIG. 6 is a block diagram showing an embodiment of a display device of the present invention.

FIG. 7 shows a schematic diagram of an embodiment of a GOA control circuit in a display device of the present invention.

The drawings in the present invention are schematic, and are mainly intended to represent the coupling relationship between various circuits and the relationship between signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn to scale.

Please refer to FIG. 2, which shows an embodiment of a display device (display device 2) of the present invention. The display device 2 includes a timing control circuit 10 and a gate-driver on array (or abbreviation). GOA) control circuit 20. The timing control circuit 10 is used for generating a frame synchronization signal FS. The GOA control circuit 20 is coupled to the timing control circuit 10 and includes a scan signal management circuit 21 and a quasi-shift circuit 22. The scanning signal management circuit 21 is configured to generate a scanning signal management signal SSM according to the frame synchronization signal FS, a preset panel parameter, and an operating clock signal CLK. The scanning signal management circuit 21 includes a storage unit 211 for Save the preset panel parameters. The level shift circuit 22 generates a scan control signal SCS according to the scan signal management signal SSM to control a gate drive array of a display panel circuit 30 (such as, but not limited to, a thin film transistor liquid crystal display panel TFT LCD display panel). 31, wherein the gate driving array 31 generates a gate driving signal GL according to the scanning control signal SCS to control one of the vertical scanning operations of the display panel circuit 30; specifically, as shown in FIG. 2, the gate driving array 31 The vertical scanning of the display panel unit 32 is controlled by the gate driving signal GL to perform development.

The frame synchronization signal FS refers to a clock signal synchronized with a frame update rate of the display panel circuit 30 for synchronizing the image. In one embodiment, the frequency of the frame synchronization signal FS and the frame update of the display panel circuit 30 The rate is the same.

Please continue to refer to FIG. 2. In one embodiment, the scan control signal SCS may include at least one of the following: (1) a GOA phase control signal CKV_GOA, which is used to control the phase of the gate driving signal GL of the display panel circuit 30 and Waveform; in one embodiment, the GOA phase control signal CKV_GOA includes m phases, such as the phase control signal CKV_GOA1 ~ CKV_GOAm, where m is a positive integer; (2) a durability control signal LEC for controlling one of the durability operations of the gate driving signal GL; in one embodiment, the durability control signal LEC includes n coded or uncoded The durability control signals, such as the durability control signals LEC1 ~ LECn shown in the figure, where n is a positive integer; and (3) a shutdown signal POFF is used to control one of the gate driving signals GL to shut down. In one embodiment, the scanning signal management signals SSM correspond to the scanning control signals SCS one by one.

Display panel circuits of different manufacturers have various parameters, such as, but not limited to, vertical resolution, the number of phases of the gate drive signal GL, the transient waveform requirements of the gate drive signal GL, etc., and / or various gates Signal requirements for the durability operation or shutdown operation of the pole-driven signal GL, etc. The display device according to the present invention can be flexibly applied to display panels of different manufacturers and various forms. The details will be detailed later.

Please also refer to Figs. 3A-3C. The GOA control circuit (such as GOA control circuit 20) of the present invention can generate the corresponding GOA phase control signal CKV_GOA according to the different requirements mentioned above, and then control the gate drive array 31 to generate a corresponding response. The gate driving signal GL is shown in FIG. 3A as an example. In this embodiment, the GOA phase control signal includes a pair of complementary GOA phase control signals CKV_GOAxP and CKV_GOAxN. According to the requirements of the display panel circuit (such as charge Shared control), the rising and falling edges of GOA phase control signals CKV_GOAxP and CKV_GOAxN need to be divided into multiple stages, such as T1-T5 in the figure. Taking FIG. 3B as an example, in this embodiment, the GOA phase control signal includes, for example, but not limited to, six groups of phases, that is, CKV_GOA1 ~ CKV_GOA6 as shown in the figure, and according to the requirements of the display panel circuit in this embodiment, as shown As shown, the GOA phase control signals CKV_GOA1 ~ CKV_GOA6 must have a phase overlay relationship. For example, the GOA phase control signals CKV_GOA1 and CKV_GOA2 overlap at time points t2-t5. In addition, as shown in FIG. 3B, in this embodiment, during the development scanning phase, for example, after the time point t1, the GOA phase control signal The rising or falling edges of CKV_GOA1 ~ CKV_GOA6 need to have a transient waveform (such as the waveform of GOA phase control signal CKV_GOA1 at t1-t2).

Taking Figure 3C as an example, in this embodiment, between the ON periods of the GOA phase control signals CKV_GOA1 ~ CKV_GOA6 (for example, the ON period of CKV_GOA1 is t1-t2), there is no need to overlap, and in this embodiment, the GOA phase The transient waveform of the control signal does not need to be chamfered.

In addition, the GOA control circuit (such as the GOA control circuit 20) of the present invention can generate a corresponding durability control signal LEC in response to the aforementioned different needs, so as to extend the service life of the display panel circuit or display device. In one embodiment, the durability control signal LEC can be used to control the timing of inverting driving of the display panel circuit; in another embodiment, the durability control signal LEC can be used to control the management of some circuits in the display device in turn driving.

Similarly, the GOA control circuit (such as the GOA control circuit 20) of the present invention can generate a corresponding shutdown signal POFF to control the shutdown operation of the display panel circuit in response to the aforementioned different needs.

According to the requirements of the foregoing different panel specifications, the preset panel parameters stored in the storage unit 211 may include, for example, but not limited to, the vertical or horizontal scanning resolution of the display panel unit 32, the frame update rate, and the vertical or horizontal scanning interval. Time parameters (e.g. quantity or time length), phase numbers of vertical scanning lines, phase numbers of GOA phase control signals, phase overlap parameters, transient waveform parameters of GOA phase control signals, parameters related to durability control, parameters related to shutdown signals And the combination of the above parameters are used to generate the aforementioned corresponding scanning control signal SCS (that is, GOA phase control signal, durability control signal, shutdown signal, etc.).

Please refer to FIG. 4, which shows a specific embodiment of the GOA control circuit (GOA control circuit 20) in the display device of the present invention. In this embodiment, the scanning signal management circuit 21 further includes at least one of the following units. 1: Phase number control unit 212, phase overlap control unit 213. Transient control unit 214, interval control unit 215, durability control unit 216, and shutdown control unit 217. The control unit generates a corresponding scan according to the picture synchronization signal FS, the aforementioned preset panel parameters, and the operation clock signal CLK. The signal management signal SSM controls the level shift circuit 22 to generate a scanning control signal SCS. The phase number control unit 212 is used to determine the phase number of the GOA phase control signal to provide a corresponding GOA phase control signal; the phase overlap control unit 213 is used to adjust the degree of phase overlay of the GOA phase control signal; The transient control unit 214 is used to control the transient waveform of the GOA phase control signal; the interval control unit 215 is used to control the number or length of the horizontal interval or the vertical interval; the durability control unit 216 is used to generate the durability control signal; shutdown The control unit 217 is used for generating the shutdown signal.

The display device of the present invention can be applied to a single display panel or a plurality of display panels. In one embodiment, the preset panel parameter may be a fixed value, an optional fixed value, or an adjustable value. In the embodiment where the preset panel parameters are adjustable, the preset panel parameters can be written into the storage unit 211 by a user at a setting stage. The setting stage can be, for example, when the display panel is produced, or when the imaging scan has not been performed after each startup. In an embodiment, the preset panel parameters can be written into the storage unit 211 by the timing control circuit 10. It should be noted that this is different from the prior art in that the preset panel parameters are static parameter values according to the present invention Only need to, for example, in the setting stage, between the timing control circuit and the GOA control circuit, such as but not limited to I ² C and other serial transmission interfaces (as shown in Figure 5) to transmit the preset panel parameters And written in the storage unit 211. In contrast, in the prior art, the timing controller and the GOA control circuit are dynamic control signals that are directly related to the scan control signal and correspond in real time. Therefore, the timing controller and the GOA control circuit are There are a large number of signal lines. According to the present invention, in one embodiment, the timing control circuit 10 and the GOA control circuit 20 may include only one and only signal, that is, the frame synchronization signal FS, and the GOA control circuit 20 may be stored in the storage unit 211 according to The preset panel parameters in the system can generate various scanning control signals as mentioned above. In one embodiment, the transmission signal between the timing control circuit 10 and the GOA control circuit 20 may be composed of only the frame synchronization signal FS and the operation clock signal CLK.

Please refer to FIG. 6, which shows another embodiment of the display device (display device 6) of the present invention. In this embodiment, the operation clock signal CLK of the display device 6 is provided by the timing control circuit 10.

In one embodiment, the operation clock signal CLK may not be provided externally by the GOA control circuit. Please refer to FIG. 7, which shows a specific embodiment of a GOA control circuit (GOA control circuit 20 ′) in a display device of the present invention. In this embodiment, GOA control circuit 20 ′ and FIG. 4 The GOA control circuit 20 is similar, except that the GOA control circuit 20 'further includes an oscillator 23 for generating an operation clock signal CLK. In this embodiment, since the operation clock signal CLK is in the GOA control circuit 20' It is generated internally by itself, so the signal line between the timing control circuit 10 and the GOA control circuit 20 'can be further reduced.

In one embodiment, the operation clock signal CLK is synchronized with the frame synchronization signal FS. In a preferred embodiment, the operation clock signal CLK is synchronized with the falling edge of the frame synchronization signal FS, that is, when the synchronization signal ends, Figure 3C is an example, which is t1. In addition, in a preferred embodiment, the frequency of the clock signal CLK is 5 times or more than the vertical scanning frequency VF of the screen, where the vertical scanning frequency VF = screen update rate * (vertical resolution + vertical interval number), The scanning control signal SCS (such as the GOA phase control signal) can have a higher waveform resolution, thereby improving the display quality of the display panel circuit.

In one embodiment, the clock signal CLK may be synchronized to the vertical scan frequency VF of the display panel circuit. In one embodiment, the clock signal CLK may not be synchronized to the vertical scan frequency VF of the display panel circuit. .

It can be known from the foregoing embodiments that according to the present invention, the signal lines between the timing control circuit and the GOA control circuit can be greatly reduced. From a viewpoint, the timing control circuit and the GOA control circuit The signal lines between the control circuits do not include (1) a signal line directly corresponding to the GOA phase control signal, (2) a signal line directly corresponding to the durability control signal, or (3) a signal directly corresponding to the shutdown signal. In one embodiment, the signal line between the timing control circuit and the GOA control circuit does not include a combination of the above signal lines. The “directly corresponding” GOA phase control signal refers to a signal received by the GOA control circuit from the timing control circuit, and has a corresponding relationship with the GOA phase control signal, such as one-to-one, or an uncoded corresponding relationship.

The present invention has been described above with reference to the preferred embodiments, but the above is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Each of the described embodiments is not limited to a single application, and may be applied in combination. In addition, under the same spirit of the present invention, those skilled in the art can consider various equivalent changes and various combinations. For example, the operation clock signal CLK is optional, that is, the operation clock signal CLK can be selected by the user. The GOA control circuit is provided internally (such as the aforementioned oscillator), or it is provided externally of the GOA control circuit (for example, provided by a timing control circuit). For another example, the term "processing or calculation according to a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes performing voltage-current conversion, current-voltage conversion on the signal when necessary, and / Or proportional conversion, etc., and then process or calculate according to the converted signal to produce an output result. It can be seen that, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed here. Therefore, the scope of the invention should cover the above and all other equivalent variations.

Claims (20)

A display device includes: a timing control circuit for generating a picture synchronization signal; and a gate drive array (GOA) control circuit coupled to the timing control circuit, including: a scanning signal management circuit for The screen synchronization signal, a preset panel parameter, and an operating clock signal generate a scanning signal management signal; wherein the scanning signal management circuit includes a storage unit for storing the preset panel parameter; and a standard The displacement circuit generates a scanning control signal according to the scanning signal management signal to control a gate driving array of a display panel circuit, wherein the gate driving array generates a gate driving signal according to the scanning control signal and is used for Controlling one of the display panel circuits' vertical scanning operation; wherein the scanning control signal includes at least one of the following: (1) a GOA phase control signal for controlling the phase and waveform of the gate driving signal; (2) a durability A control signal for controlling one of the durability operations of the gate driving signal; and (3) a shutdown signal for controlling the One gate drive signal shutdown. The display device according to item 1 of the scope of patent application, wherein the GOA control circuit further includes an oscillator for generating the operating clock signal. The display device according to item 1 of the scope of patent application, wherein the timing control circuit provides the operating clock signal. The display device according to item 1 of the scope of patent application, wherein the operating clock signal is not provided from the outside of the GOA control circuit. The display device according to any one of claims 2 to 4, wherein the operation clock signal is synchronized with the screen synchronization signal. The display device according to any one of claims 2 to 4, wherein the operating clock signal is synchronized or asynchronous to a vertical scanning frequency of the display panel circuit. The display device according to item 1 of the scope of patent application, wherein the preset panel parameters are one of: (1) a fixed value; (2) an optional fixed value; and (3) an adjustable value , Wherein the preset panel parameters are written into the storage unit by a user in a setting stage. The display device according to item 1 of the scope of patent application, wherein the preset panel parameters include at least one of the following: (1) one phase number of the GOA phase control signal; (2) one phase of the GOA phase control signal Overlay parameters; (3) one of the transient waveform parameters of the GOA phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter. The display device according to item 1 of the patent application scope, wherein the scanning signal management circuit further includes at least one of the following units: a phase number control unit for determining the number of phases of the GOA phase control signal; a phase overlay control A unit for adjusting the degree of phase overlay of the GOA phase control signal; a transient control unit for controlling the transient waveform of the GOA phase control signal; an interval control unit for controlling a horizontal interval time Or a vertical interval; a durability control unit for generating the durability control signal; and a shutdown control unit for generating the shutdown signal. The display device according to item 1 of the scope of patent application, wherein the signal line between the timing control circuit and the GOA control circuit does not include (1) a signal line directly corresponding to the GOA phase control signal; (2) directly corresponding to a durable The signal line of the degree control signal; or (3) the signal directly corresponding to the shutdown signal. A gate drive array (GOA) control circuit for a display device includes: a timing control circuit for generating a picture synchronization signal; the GOA control circuit is coupled to the timing control circuit; the GOA control The circuit includes: a scanning signal management circuit for generating a scanning signal management signal according to the screen synchronization signal, a preset panel parameter and an operating clock signal; wherein the scanning signal management circuit includes a storage unit for Storing the preset panel parameters; and a quasi-shift circuit that generates a scanning control signal according to the scanning signal management signal to control a gate driving array of a display panel circuit, wherein the gate driving array is based on the The scanning control signal generates a gate driving signal for controlling a vertical scanning operation of the display panel circuit. The scanning control signal includes at least one of the following: (1) a GOA phase control signal for controlling the gate driving Phase and waveform of the signal; (2) A durability control signal for controlling the durability of one of the gate driving signals Made; and (3) a shutdown signal for controlling the gate driving signals one shutdown. The GOA control circuit according to item 11 of the scope of patent application, wherein the GOA control circuit further includes an oscillator for generating the operation clock signal. The GOA control circuit according to item 11 of the patent application scope, wherein the timing control circuit provides the operation clock signal. The GOA control circuit according to item 11 of the scope of the patent application, wherein the operating clock signal is not provided outside the GOA control circuit. The GOA control circuit according to any one of claims 12 to 14, wherein the operation clock signal is synchronized with the screen synchronization signal. The GOA control circuit according to any one of claims 12 to 14, wherein the operating clock signal is synchronized or asynchronous to a vertical scanning frequency of the display panel circuit. The GOA control circuit according to item 11 of the scope of patent application, wherein the preset panel parameters are one of the following: (1) a fixed value; (2) an optional fixed value; and (3) an adjustable Value, wherein the preset panel parameter is written into the storage unit by a user in a setting stage. The GOA control circuit according to item 11 of the scope of patent application, wherein the preset panel parameters include at least one of: (1) one phase number of the GOA phase control signal; (2) one of the GOA phase control signal Phase overlay parameters; (3) one of the transient waveform parameters of the GOA phase control signal; (4) a durability control related parameter; and (5) a shutdown signal related parameter. The GOA control circuit according to item 11 of the patent application scope, wherein the scanning signal management circuit further includes at least one of the following units: a phase number control unit for determining the number of phases of the GOA phase control signal; a phase overlay A control unit for adjusting the degree of phase overlay of the GOA phase control signal; a transient control unit for controlling the transient waveform of the GOA phase control signal; an interval control unit for controlling a horizontal interval Time or a vertical interval; a durability control unit for generating the durability control signal; and a shutdown control unit for generating the shutdown signal. The GOA control circuit as described in item 11 of the patent application scope, wherein the signal line between the timing control circuit and the GOA control circuit does not include (1) a signal line directly corresponding to the GOA phase control signal, and (2) directly corresponding to The signal line of the durability control signal, or (3) the signal directly corresponding to the shutdown signal.