TWI649733B - Display device and its gate driver - Google Patents

Abstract

An embodiment of the present invention provides a display device and a gate driver thereof. The display device and its gate driver may integrate the clock signal and the enabling signal into a same signal, and perform calculation processing on the enabling signal by using a plurality of logic circuit elements to obtain the required gate driver. The start signal, thereby reducing the number of input signal pins on the gate driver.

Description

Display device and gate driver thereof

The invention relates to a display device and a gate driver thereof, and in particular to a display device and a gate driver thereof capable of reducing the number of pins.

Generally, a display device includes a data driver, a gate driver, and pixels arranged in a matrix form. The gate driver includes multiple shift register circuits. The shift register circuit is used to output multiple scanning signals to turn on multiple rows of pixels in the display device, and the turned-on pixels receive the data provided by the data driver. And display the data accordingly. In recent years, in order to meet the demands of consumers, display devices are usually designed in the direction of thin, thin, and narrow (no) bezels. Therefore, in this type of design, the number of pins of the input signal must be severely limited. In view of this, there is an urgent need in the art for a display device capable of reducing the number of pins and a gate driver thereof.

An object of the present invention is to provide a display device capable of reducing the number of pins and a gate driver thereof. To achieve the above object, an embodiment of the present invention provides a gate driver. The gate driver includes a start signal generating circuit, a first shift register circuit, a second shift register circuit, and a third shift register. Memory circuit. The starting signal generating circuit is used for receiving the first enabling signal, the second enabling signal and the third enabling signal, and generating a starting signal. The first shift register circuit is electrically coupled to the start signal generating circuit. The first shift register circuit receives the first enable signal and the start signal and is used to generate at least one first gate driving signal. The second shift register circuit is electrically coupled to the start signal generating circuit. The second shift register circuit receives the second enable signal and the start signal and is used to generate at least one second gate driving signal. The third shift register circuit is electrically coupled to the start signal generating circuit. The third shift register circuit receives a third enable signal and a start signal, and is used to generate at least a third gate driving signal.

An embodiment of the present invention further provides a display device including a timing controller, a start signal generating circuit, a gate driver, a data driver, and a plurality of pixel units. The timing controller is used for generating a first enabling signal, a second enabling signal and a third enabling signal. The starting signal generating circuit is electrically coupled to the timing controller. The starting signal generating circuit is configured to receive the first enabling signal, the second enabling signal and the third enabling signal, and generate a starting signal. The gate driver is electrically coupled with the timing controller and the starting signal generating circuit. The gate driver receives the first enabling signal, the second enabling signal, the third enabling signal and the starting signal, and according to the first enabling The signal, the second enabling signal, the third enabling signal, and the start signal output a plurality of gate driving signals. The data driver is used to output multiple display data, and each pixel unit is electrically coupled to the gate driver and the data driver. Each pixel unit is used to determine whether to receive display data according to the received gate driving signal.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and accompanying drawings of the present invention, but these descriptions and attached drawings are only used to illustrate the present invention, not the right to the present invention. No limitation on scope.

Hereinafter, the present invention will be described in detail by explaining various embodiments of the present invention with drawings. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Moreover, the same reference numbers may be used in the drawings to indicate similar elements.

Specifically, the gate driver provided in the embodiment of the present invention may be applicable to any display device, for example, an active matrix organic light emitting diode (AMOLED) display device adopting a progressive scanning method, but the present invention does not use this. For restrictions. In a word, the present invention does not limit the specific implementation of the display device. Those with ordinary knowledge in the technical field should be able to design according to actual needs or applications.

In addition, according to the prior art, the gate driver can include multiple shift register circuits, and each shift register circuit must receive an enable signal, a start signal, and at least one clock signal, and generate At least one gate driving signal drives at least one column of pixels in the display device. Therefore, in the case where only three sets of shift register circuits are taken as an example, it is necessary to have at least seven input signal pins on the conventional gate driver. Three of them are used to individually receive an enable signal, the other three are used to individually receive a clock signal, and the last one is used to receive a common start signal.

However, compared with the prior art, the present invention is designed to hide or merge part of the control mechanism on some existing signals, so as to achieve the purpose of reducing the number of pins. Please refer to FIG. 1, which is a functional block diagram of a gate driver according to an embodiment of the present invention. The gate driver 10 includes a start signal generating circuit 101, a first shift register circuit 103, a second shift register circuit 105, and a third shift register circuit 107. The starting signal generating circuit 101 is configured to receive the first enabling signal emOE1, the second enabling signal emOE2, and the third enabling signal emOE3, and generate an initial signal i-STP.

In addition, the first to third shift register circuits 103, 105, and 107 are electrically coupled to the start signal generating circuit 101, respectively, and the first shift register circuit 103 receives the first enable signal emOE1 and The starting signal i-STP is used to generate at least one first gate driving signal GS1. The second shift register circuit 105 receives the second enable signal emOE2 and the start signal i-STP, and is used to generate at least a second gate drive signal GS2, and the third shift register circuit 107 receives The third enabling signal emOE3 and the start signal i-STP are used to generate at least one third gate driving signal GS3. It is worth noting that, for the convenience of the following description, the shift register circuit of this embodiment is also described by using only an example of three groups (ie, the first to third shift register circuits 103, 105). , 107), but it is not intended to limit the invention.

In other words, the gate driver 10 may further include a fourth shift register circuit to an N-th shift register circuit (that is, N is a positive integer greater than or equal to five), and it should be understood that The operation principles of the fourth to N-th shift register circuits are similar to the operation principles of the first to third shift register circuits 103, 105, and 107, so they will not be described in detail here. In addition, since the detailed contents of the shift register circuit are already known to those having ordinary knowledge in the technical field, only the detailed contents of the first shift register circuit 103 are illustrated in FIG. 1, and Details of the second and third shift register circuits 105 and 107 will not be repeated here. As shown in FIG. 1, the first shift register circuit 103 may include a shift register 1031 and a plurality of AND gates 1033.

Similarly, in order to facilitate the following description, the AND gate 1033 in FIG. 1 is also described by using only an example of four, but it is not intended to limit the present invention. According to the prior art, the waveform of the first clock signal (not shown) that should be received by the shift register 1031 and the waveform of the first enable signal emOE1 that the gate 1033 must receive are extremely different. Similarly, this embodiment will integrate the aforementioned first clock signal and the first enabling signal emOE1 into the same signal, and so on. In this embodiment, the second and third shift register circuits 105, The second clock signal (not shown) and the third clock signal (not shown) that were originally received by 107 are integrated with the second enabling signal emOE2 and the third enabling signal emOE3, respectively, into the same signal. In this way, the number of input signal pins on the gate driver 10 can be omitted first while still meeting the operating requirements of the display device.

In addition, since the starting signals i-STP that the first to third shift register circuits 103, 105, 107 must receive in common can be generated by the starting signal generating circuit 101 in the gate driver 10, Therefore, the number of input signal pins on the gate driver 10 is omitted again. That is, compared with the conventional gate driver that requires seven input signal pins, the gate driver 10 according to the embodiment of the present invention only needs four input signal pins. However, in order to further explain the implementation details of the start signal generating circuit 101, the present invention further provides an implementation of the start signal generating circuit 101. Please refer to FIG. 2 together. FIG. 2 is a circuit diagram of a start signal generating circuit in the gate driver of FIG. 1. Among them, some components in FIG. 2 that are the same as those in FIG. 1 are marked with the same drawing numbers, and therefore no further details are given here.

In this embodiment, the starting signal generating circuit 101 may include a plurality of logic gates and a plurality of D-type flip-flops, such as the first to fourth logic gates 2011 to 2014, and the first to fourth D-type flip-flops. Inverter 2021 ～ 2024. The first logic gate 2011 has two input terminals and one output terminal. One input terminal receives the first enabling signal emOE1, and the other input terminal receives the second enabling signal emOE2. The second logic gate 2012 also has two input terminals and one output terminal, but one input terminal receives the second enabling signal emOE2, and the other input terminal receives the third enabling signal emOE3. The third logic gate 2013 also has two input terminals and one output terminal, but one input terminal receives the third enabling signal emOE3, and the other input terminal receives the first enabling signal emOE1.

Then, the data input terminal (D) of the first D-type flip-flop 2021 is electrically coupled to the output terminal of the first logic gate 2011, and the clock input terminal of the first D-type flip-flop 2021 receives a third signal. Can signal emOE3. Similarly, the data input terminal of the second D-type flip-flop 2022 is electrically coupled to the output terminal of the second logic gate 2012, and the clock input terminal of the second D-type flip-flop 2022 receives the first enable signal. emOE1. The data input terminal of the third D-type flip-flop 2023 is electrically coupled to the output terminal of the third logic gate 2013, and the clock input terminal of the third D-type flip-flop 2023 receives the second enabling signal emOE2.

In addition, the fourth logic gate 2014 has three input terminals and one output terminal, and the three input terminals are electrically coupled to the positive-phase output terminals (Q) of the first to third D-type flip-flops 2021 to 2023, respectively. The data input terminal of the fourth D-type flip-flop 2024 is electrically coupled to the output terminal of the fourth logic gate 2014, and the clock input terminal of the fourth D-type flip-flop 2024 receives the third enabling signal emOE3, The positive signal i-STP is output at the non-inverting output end of the fourth D-type flip-flop 2024.

In this embodiment, the first logic gate 2011, the second logic gate 2012, and the third logic gate 2013 may all be OR gates, and the fourth logic gate 2014 may be, for example, an OR gate. And the first D-type flip-flop 2021, the second D-type flip-flop 2022, and the third D-type flip-flop 2023 can all be, for example, positive-triggered D-type flip-flops, and the fourth D-type flip-flop 2024 can trigger a D-type flip-flop for a negative edge, as shown in FIG. 2, but the present invention is not limited thereto. In addition, since the operation principle of OR gate, reverse OR gate, positive edge triggering D-type flip-flop and negative edge triggering D-type flip-flop are already known to those with ordinary knowledge in the technical field, the above-mentioned first Details of the fourth to fourth logic gates 2011 to 2014 and the first to fourth D-type flip-flops 2021 to 2024 will not be repeated here.

However, according to the teachings of the above, those having ordinary knowledge in the technical field should understand that the present invention can be implemented by using a plurality of logic circuit elements (that is, the first to fourth logic gates 2011 to 2014 and the first to fourth logic gates The fourth D-type flip-flops 2021 to 2024) perform arithmetic processing on the first to third enable signals emOE1 to emOE3 to obtain the first to third shift register circuits 103 to 107 that must be received in common. Start signal i-STP. In addition, since the initial signal i-STP is generally generated only before the display device displays a screen, the present invention can also additionally design a set of waveforms of the first to third enabling signals emOE1 to emOE3 for use. To generate the initial signal i-STP. In other words, during the period when the display device normally displays one frame, the original waveforms of the first to third enabling signals emOE1 to emOE3 will not be used to generate the initial signal i-STP.

Please refer to FIG. 3A and FIG. 3B together. FIG. 3A is a timing diagram of the first to third enabling signals in the gate driver of FIG. 1 during the first period. The first period may be, for example, any period before the display device displays a screen. As shown in FIG. 3A, during the first period, the rising edge and falling edge of the first enabling signal emOE1 are earlier than the rising edge and falling edge of the second enabling signal emOE2, and the rising edge of the second enabling signal emOE2 And the falling edge is earlier than the rising edge and falling edge of the third enabling signal emOE3. Therefore, before the display device displays a screen, the starting signal generating circuit 101 in FIG. 2 also generates a high-level starting signal i-STP according to the above waveform.

Similarly, FIG. 3B is a timing diagram of the first to third enabling signals in the gate driver of FIG. 1 during the second period. The second period may be, for example, any period when the display device normally displays a screen. As shown in FIG. 3B, during the second period, the rising edge of the third enabling signal emOE3 is earlier than the rising edge of the second enabling signal emOE2, and the rising edge of the second enabling signal emOE2 is earlier than the first enabling signal. The rising edge of the energy signal emOE1, the falling edge of the second enabling signal emOE2 is also earlier than the falling edge of the first enabling signal emOE1, and the falling edge of the first enabling signal emOE1 is earlier than the falling edge of the third enabling signal emOE3. edge. Therefore, during the period when the display device normally displays a frame, the starting signal generating circuit 101 in FIG. 2 will not generate the starting signal i-STP according to the above waveform.

It should be noted that the waveforms of the first to third enabling signals emOE1 to emOE3 used in FIG. 3A and FIG. 3B are merely examples, which are not intended to limit the present invention. In other words, those with ordinary knowledge in the technical field should be able to design different timing waveforms according to actual needs or applications. Next, in order to further explain the application of reducing the input signal pins on the gate driver, the present invention further provides an embodiment of the display device. Please refer to FIG. 4, which is a functional block diagram of a display device according to an embodiment of the present invention. Among them, some of the components in FIG. 4 that are the same as those in FIG. 1 are marked with the same drawing numbers, so details are not described in detail here.

As shown in FIG. 4, the display device 4 may include a timing controller 40, a start signal generating circuit 101, a gate driver 42, a data driver 44, and a plurality of pixel units 46. The timing controller 40 is configured to generate a first enabling signal emOE1, a second enabling signal emOE2, and a third enabling signal emOE3. The start signal generating circuit 101 is electrically coupled to the timing controller 40, and the start signal generating circuit 101 is configured to receive the first enabling signal emOE1, the second enabling signal emOE2, and the third enabling signal emOE3, and generate Start signal i-STP.

The gate driver 42 is electrically coupled to the timing controller 40 and the start signal generating circuit 101, and the gate driver 42 receives the first enabling signal emOE1, the second enabling signal emOE2, the third enabling signal emOE3, and the The starting signal i-STP, and output multiple gate driving signals according to the first enabling signal emOE1, the second enabling signal emOE2, the third enabling signal emOE3, and the starting signal i-STP, as shown in FIG. 4 The pole driving signals G ₁ to G _M (that is, M is a positive integer greater than 1). Further, the data driver 44 for outputting a plurality of display data, the display data S shown in FIG. 4 ₁ ~ S _P (i.e., P is a positive integer greater than 1). Each pixel unit 46 is electrically coupled to the gate driver 42 and the data driver 44, and each pixel unit 46 is configured to receive a gate driving signal G _i (that is, i is 1 to M) positive integer) to decide whether to receive display data S ₁ ~ S _P.

However, as described in the foregoing, this embodiment is to separate the clock signal (not shown) originally received by the gate driver 42 from the first enable signal emOE1, the second enable signal emOE2, or The third enabling signal emOE3 is integrated into the same signal, so the number of input signal pins on the gate driver 42 can be omitted by three while still meeting the operating requirements of the display device 4. In addition, the starting signal generating circuit 101 in this embodiment may also be configured in the gate driver 42. Therefore, please refer to FIG. 5 together. FIG. 5 is a functional block diagram of a display device according to another embodiment of the present invention. . Among them, some components in FIG. 5 that are the same as those in FIG. 4 are marked with the same reference numerals, so details are not described in detail here.

In the display device 5 of FIG. 5, the gate driver 52 actively includes a start signal generating circuit 101. Since the start signal i-STP that multiple shift register circuits 520 in the gate driver 52 must receive in common can be generated by the start signal generating circuit 101 in the gate driver 52, the gate The number of input signal pins on the driver 52 is omitted again. In a word, the present invention does not limit the specific configuration position of the initial signal generating circuit 101. Those with ordinary knowledge in the technical field should be able to design according to actual needs or applications.

In addition, the specific implementation of the start signal generating circuit 101 can also be as described in the previous embodiment, so the details will not be described in detail here. Furthermore, because the present invention may additionally design a set of waveforms of the first to third enabling signals emOE1 to emOE3 to generate the start signal i-STP, the first signal generated by the timing controller 40 is The waveforms of the third enabling signals emOE1 to emOE3 can also be as described in the foregoing embodiment, so the details will not be described in detail here.

In summary, the display device and its gate driver provided in the embodiments of the present invention can integrate the clock signal and the enable signal into the same signal, and use multiple logic circuit elements to calculate the enable signal. Processing to obtain the initial signal required by the gate driver, thereby reducing the number of input signal pins on the gate driver.

The above description is only an embodiment of the present invention, and is not intended to limit the patent scope of the present invention.

4, 5‧‧‧ display device

40‧‧‧sequence controller

44‧‧‧Data Drive

46‧‧‧Pixel Unit

10, 42, 52‧‧‧‧Gate driver

101‧‧‧Start signal generating circuit

520‧‧‧shift register circuit

103‧‧‧First shift register circuit

105‧‧‧Second shift register circuit

107‧‧‧Third shift register circuit

emOE1‧‧‧First enabling signal

emOE2‧‧‧Second enabling signal

emOE3‧‧‧ Third enabling signal

i-STP‧‧‧Start signal

GS1‧‧‧First gate drive signal

GS2‧‧‧Second gate drive signal

GS3‧‧‧Third gate drive signal

G ₁ ～ G _M ‧‧‧pole drive signal

S ₁ ～ S _P ‧‧‧Display data

1031‧‧‧Shift register

1033‧‧‧ and Gate

2011 ～ 2014‧‧‧‧First to fourth logic gates

2021 ～ 2024‧‧‧‧First to fourth D-type flip-flops

FIG. 1 is a functional block diagram of a gate driver according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a start signal generating circuit in the gate driver of FIG. 1. FIG. 3A is a timing diagram of the first to third enabling signals in the gate driver of FIG. 1 during a first period. FIG. 3B is a timing diagram of the first to third enabling signals in the gate driver of FIG. 1 during the second period. FIG. 4 is a functional block diagram of a display device according to an embodiment of the present invention. FIG. 5 is a functional block diagram of a display device according to another embodiment of the present invention.

Claims (9)

A gate driver includes: a starting signal generating circuit for receiving a first enabling signal, a second enabling signal and a third enabling signal, and generating a starting signal; a first shift temporary storage A generator circuit electrically coupled to the starting signal generating circuit, the first shift register circuit receiving the first enabling signal and the starting signal, and used to generate at least a first gate driving signal; A second shift register circuit is electrically coupled to the start signal generating circuit. The second shift register circuit receives the second enable signal and the start signal, and is used for generating at least one second signal. A gate driving signal; and a third shift register circuit electrically coupled to the start signal generating circuit, the third shift register circuit receiving the third enable signal and the start signal, And used to generate at least one third gate driving signal. The gate driver according to claim 1, wherein the starting signal generating circuit includes: a first logic gate having a first input terminal, a second input terminal, and an output terminal, the first logic gate A first input terminal receives the first enable signal, and a second input terminal of the first logic gate receives the second enable signal; a second logic gate having a first input terminal, a second input terminal, and An output end, the first input end of the second logic gate receives the second enable signal, and the second input end of the second logic gate receives the third enable signal; a third logic gate having a A first input terminal, a second input terminal, and an output terminal; the first input terminal of the third logic gate receives the third enable signal; and the second input terminal of the third logic gate receives the first enable signal. Energy signal; a first D-type flip-flop having a data input terminal, a clock input terminal and a non-inverting output terminal, the data input terminal of the first D-type flip-flop and the first logic gate of the The output terminal is electrically coupled, and the clock input terminal of the first D-type flip-flop is connected. The third enabling signal; a second D-type flip-flop having a data input terminal, a clock input terminal and a non-inverting output terminal, the data input terminal of the second D-type flip-flop and the second D-type flip-flop The output end of the logic gate is electrically coupled, and the clock input end of the second D-type flip-flop receives the first enable signal. A third D-type flip-flop has a data input end and a clock. An input terminal and a non-inverting output terminal, the data input terminal of the third D-type flip-flop is electrically coupled with the output terminal of the third logic gate, and the clock input of the third D-type flip-flop Receiving a second enabling signal; a fourth logic gate having a first input terminal, a second input terminal, a third input terminal and an output terminal, the first input terminal of the fourth logic gate and The positive phase output terminal of the first D-type flip-flop is electrically coupled, the second input terminal of the fourth logic gate is electrically coupled with the positive-phase output terminal of the second D-type flip-flop, The third input terminal of the fourth logic gate is electrically coupled to the positive-phase output terminal of the third D-type flip-flop; and a fourth D-type flip-flop, having A data input terminal, a clock input terminal, and a non-inverting output terminal. The data input terminal of the fourth D-type flip-flop is electrically coupled to the output terminal of the fourth logic gate. The clock input terminal of the inverter receives the third enabling signal, and the non-inverting output terminal of the fourth type flip-flop outputs the start signal. The gate driver according to claim 2, wherein the first logic gate, the second logic gate, and the third logic gate are OR gates, the first D-type flip-flop, and the second D-type flip-flop The third D-type flip-flop is a positive edge-triggered D-type flip-flop, the fourth logic gate is a reverse OR gate, and the fourth D-type flip-flop is a negative-edge triggered D-type flip-flop. The gate driver according to claim 3, wherein in a first period, the rising edge and the falling edge of the first enable signal are earlier than the rising edge and the falling edge of the second enable signal, and the second enable The rising edge and falling edge of the signal are earlier than the rising edge and falling edge of the third enabling signal. In a second period, the rising edge of the third enabling signal is earlier than the rising edge of the second enabling signal. The rising edge of the second enabling signal is earlier than the rising edge of the first enabling signal, the falling edge of the second enabling signal is earlier than the falling edge of the first enabling signal, and the falling edge of the first enabling signal Earlier than the falling edge of the third enabling signal. A display device includes: a timing controller for generating a first enabling signal, a second enabling signal, and a third enabling signal; a start signal generating circuit electrically coupled to the timing controller; The starting signal generating circuit is used to receive the first enabling signal, the second enabling signal and the third enabling signal, and generate a starting signal; a gate driver, the timing controller and the starting signal The start signal generating circuit is electrically coupled, and the gate driver receives the first enable signal, the second enable signal, the third enable signal, and the start signal, and according to the first enable signal, the The second enabling signal, the third enabling signal, and the start signal output a plurality of gate driving signals; a data driver for outputting a plurality of display data; and a plurality of pixel units, each pixel unit and The gate driver and the data driver are electrically coupled, and each of the pixel units is used to determine whether to receive the display data according to the received gate driving signal. The display device according to claim 5, wherein the start signal generating circuit is configured in the gate driver. The display device according to claim 5, wherein the initial signal generating circuit comprises: a first logic gate having a first input terminal, a second input terminal, and an output terminal, the first logic gate An input terminal receives the first enabling signal, and the second input terminal of the first logic gate receives the second enabling signal. A second logic gate has a first input terminal, a second input terminal, and a An output end, the first input end of the second logic gate receives the second enable signal, and the second input end of the second logic gate receives the third enable signal; a third logic gate having a first An input terminal, a second input terminal, and an output terminal, the first input terminal of the third logic gate receives the third enable signal, and the second input terminal of the third logic gate receives the first enable signal A signal; a first D-type flip-flop having a data input terminal, a clock input terminal and a non-inverting output terminal, the data input terminal of the first D-type flip-flop and the output of the first logic gate Terminal is electrically coupled, the clock input terminal of the first D-type flip-flop receives A third enabling signal; a second D-type flip-flop having a data input terminal, a clock input terminal and a non-inverting output terminal, the data input terminal of the second D-type flip-flop and the second logic The output end of the brake is electrically coupled, and the clock input end of the second D-type flip-flop receives the first enabling signal. A third D-type flip-flop has a data input end and a clock input. Terminal and a non-inverting output terminal, the data input terminal of the third D-type flip-flop is electrically coupled to the output terminal of the third logic gate, and the clock input terminal of the third D-type flip-flop Receiving the second enabling signal; a fourth logic gate having a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the fourth logic gate and the The positive-phase output terminal of the first D-type flip-flop is electrically coupled, the second input terminal of the fourth logic gate is electrically coupled with the positive-phase output terminal of the second D-type flip-flop, and The third input terminal of the fourth logic gate is electrically coupled to the positive-phase output terminal of the third D-type flip-flop; and a fourth D-type flip-flop having A data input terminal, a clock input terminal and a non-inverting output terminal, the data input terminal of the fourth D-type flip-flop is electrically coupled with the output terminal of the fourth logic gate, and the fourth type flip-flop The clock input terminal receives the third enable signal, and the non-inverting output terminal of the fourth type flip-flop outputs the start signal. The display device according to claim 7, wherein the first logic gate, the second logic gate, and the third logic gate are OR gates, the first D-type flip-flop, the second D-type flip-flop, The third D-type flip-flop is a positive-edge-triggered D-type flip-flop, the fourth logic gate is a reverse-OR gate, and the fourth D-type flip-flop is a negative-edge-triggered D-type flip-flop. The display device according to claim 8, wherein in a first period, the rising edge and the falling edge of the first enabling signal are earlier than the rising edge and the falling edge of the second enabling signal, and the second enabling signal The rising edge and falling edge of are earlier than the rising edge and falling edge of the third enabling signal. In a second period, the rising edge of the third enabling signal is earlier than the rising edge of the second enabling signal. The rising edge of the second enabling signal is earlier than the rising edge of the first enabling signal, the falling edge of the second enabling signal is earlier than the falling edge of the first enabling signal, and the falling edge of the first enabling signal is earlier At the falling edge of the third enabling signal.