TWI648823B - Memory device - Google Patents

Abstract

A memory device. The memory device includes an array of memory. The memory array includes a main memory block and a backup memory block. The memory array includes a primary bit line and a backup bit line. The ratio A of the number of blocks of the backup memory block to the main memory block is greater than the ratio B of the number of bit lines of the backup bit line to the main bit line.

Description

Memory device

The present invention relates to a memory device, and more particularly to a memory device having a NAND memory structure.

As the critical dimensions of components in integrated circuits shrink to the limits that process technology can perceive, designers have begun to look for techniques that can achieve greater memory densities, thereby achieving lower cost per bit. Techniques currently being addressed include NAND memory and its operation.

The present invention relates to a memory device.

According to an aspect of the invention, a memory device is proposed. The memory device includes an array of memory. The memory array includes a main memory block and a backup memory block. The memory array includes a primary bit line and a backup bit line. The ratio A of the number of blocks of the backup memory block to the main memory block is greater than the ratio B of the number of bit lines of the backup bit line to the main bit line.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

The embodiment provides a memory device with a backup function bit line and a backup memory block or a secondary backup memory block, which can effectively maintain the expected memory capacity of the memory device and improve product yield and performance. .

The following is explained by some embodiments. It should be noted that the disclosure does not show all possible embodiments, and other embodiments not disclosed in the disclosure may also be applied. Furthermore, the dimensional ratios on the drawings are not drawn in proportion to the actual product. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting. In addition, the description in the embodiments, such as the detailed structure, the process steps, the material application, and the like, are for illustrative purposes only and are not intended to limit the scope of the disclosure. The details of the steps and the details of the embodiments may be varied and modified in accordance with the needs of the actual application process without departing from the spirit and scope of the disclosure. The same/similar symbols are used to describe the same/similar elements.

First, the related concepts of the block ratio and the bit line ratio according to the present disclosure can be understood by referring to FIGS. 1 to 4.

Figure 1 is a schematic illustration of a memory device in accordance with an embodiment. The memory array of the memory device includes a memory array region MMR and a memory array region EMR. In one embodiment, the memory array region MMR and the memory array region EMR may be arranged along the NAND string extending direction. The memory array area MMR and the memory array area EMR may each include a (primary) bit line area MBLR and a (backup) bit line area EBLR arranged along the direction in which the word line WL extends.

2 is a top view of a bit line region MBLR and a bit line region EBLR according to an embodiment. In one embodiment, the bit line area MBLR is a main bit line area, and includes a plurality of main bit lines MBL, for example, including the main bit lines MBL1, MBL2 to MBLN arranged in sequence in FIG. 2, wherein N is a positive integer. In one embodiment, the bit line area EBLR is a backup bit line area including a plurality of backup bit lines EBL, such as the sequentially arranged backup bit lines EBL1, ELB2 to EBLK shown in FIG. 2, where K Is a positive integer. The main bit lines MBL1, MBL2 to MBLN of the bit line area MBLR are independently and separately controlled from the backup bit lines EBL1, ELB2 to EBLK of the bit line area EBLR.

FIG. 3 is a schematic diagram of a memory array region MMR and a memory array region EMR according to an embodiment. In one embodiment, the memory array region MMR may be a main memory array region including one or more main memory blocks MB, which may include, for example, the main rows arranged along the NAND string extending direction shown in FIG. Memory blocks MB1, MB2 to MBP, where P is a positive integer. In one embodiment, the memory array area EMR may be a backup memory array area including one or more backup memory blocks EB, for example, may be arranged along the extending direction of the NAND string as shown in FIG. The memory blocks EB1 to EBQ are backed up, where Q is a positive integer.

FIG. 4 is a schematic diagram showing an equivalent circuit of a memory block of a 2D NAND memory array according to an embodiment. For example, the memory block includes bit lines BL1, BL2, BL3, BL4 and word line WL1, word line WL2, word line WL3, and word line WL4, and the memory cell array is defined at the intersection. The memory block may also include a serial selection line SSL, a ground selection line GSL, and a ground line GND. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 are between the string selection line SSL and the ground selection line GSL.

In an embodiment, the memory block (eg, the main memory block MB and/or the backup memory block EB) may include a serial selection line SSL, a ground selection line GSL, and a configuration corresponding to each (ie, independently controlled). A word line WL (for example, a word line WL1, a word line WL2, a word line WL3, and a word line WL4) between the string selection line SSL and the ground selection line GSL. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 are coupled to a word line decoder (WL decoder).

In one embodiment, the main memory block MB and the backup memory block EB may each have a circuit similar to that shown in FIG. 4, wherein, for example, the bit line BL1, the bit line BL2, the bit line BL3, and A part of the bit line BL4 is used as the main bit line MBL, and another part of the bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4 is used as the backup bit line EBL. The bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4 are coupled to a page buffer.

In this disclosure, the primary bit line MBL may also be referred to as a non-backup bit line or a non-extra bit line. In some cases, when the main bit line MBL (or the memory channel to which it is connected) is defective, causing the memory cell (serial) corresponding to the main bit line MBL to fail to perform the function, the backup bit line EBL can be used. Redundancy repair or Error Checking and Correcting (ECC) to maintain the expected effective memory capacity of the memory device and improve performance. In this disclosure, the backup bit line EBL may also be referred to as an extra bit line or a redundant bit line. The main bit line MBL and the backup bit line EBL in the present disclosure do not refer to dummy bit lines. Generally, the dummy bit line is not used to perform the function of the memory cell, and may be disposed in a peripheral non-practical area, or may be mainly used to slow down the loading effect of the process.

In this disclosure, the primary memory block MB may also be referred to as a non-backup memory block or a non-additional memory block.

In one embodiment, when the main bit line MBL in the main memory block MB is defective and the corresponding NAND string cannot perform the function, the backup bit line EBL in the same main memory block MB can be used. Redundancy repair or error checking and correction.

In one embodiment, a defect occurs in the main memory block MB, for example, at least one of the word line WL1, the word line WL2, the word line WL3, and the word line WL4 is defective to cause the main memory block MB. When all memory cells are not performing, the backup memory block EB can be used for block repair. In this disclosure, the backup memory block EB may also be referred to as an extra memory block or a redundant memory block.

In an embodiment, when the main bit line MBL in the executed backup memory block EB is defective, and the corresponding NAND string cannot perform the function, the backup bit in the same backup memory block EB can be used. Line EBL performs redundancy repair or error checking and correction.

The ratio of the backup memory block EB to the main memory block MB (i.e., the number Q of backup memory blocks EB divided by the number P of main memory blocks MB) is defined as the block number ratio A. The ratio of the backup bit line EBL to the main bit line MBL (that is, the number K of backup bit lines EBL divided by the number N of main bit lines MBL) is defined as the bit line number ratio B. In an embodiment, the block number ratio A is greater than the bit line number ratio B. In one embodiment, for example, the bit line number ratio B is 0.5% to 10%. In one embodiment, for example, the block number ratio A is greater than 10%.

The concept of the present disclosure is not limited to 2D NAND memory arrays, but can also be extended to 3D NAND memory arrays.

For example, please refer to Figures 5 to 7. 5 and 6 are respectively a top view and a perspective view of a memory block of a three-dimensional vertical channel (3D VC) NAND memory device according to an embodiment. Figure 7 is an equivalent circuit diagram of the memory block.

Referring to FIG. 5 and FIG. 6, the vertical channel VC (not shown in FIG. 6) is interleaved with the word line WL (for example, the word line WL1, the word line WL2, the word line WL3, and the word line WL4). The memory cell array is connected to the bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4 through the string selection line SSL1, the string selection line SSL2, and the string selection line SSL3. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 are electrically connected to the respective contact pillars CP via the step contact CS. Referring to FIG. 7, the memory block may also include a ground selection line GSL and a ground line GND. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 are between the string selection lines SSL1, SSL2, SSL3 and the ground selection line GSL. The bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4 are coupled to the page buffer.

In an embodiment, the memory block (eg, the main memory block MB and/or the backup memory block EB) may include a serial selection line SSL (serial selection line SSL1) corresponding to each (ie, independently controlled). The string selection line SSL2, the string selection line SSL3), the ground selection line GSL, and the word line WL (word line WL1, word line WL2, word element) arranged between the string selection line SSL and the ground selection line GSL Line WL3, word line WL4). The word line WL is coupled to the word line decoder.

In one embodiment, when the main bit line MBL in the main memory block MB (for example, the bit line BL1, the bit line BL2, the bit line BL3, and a part of the bit line BL4) is defective, the corresponding NAND string is caused. When the column cannot perform the function, the backup bit line EBL (for example, the bit line BL1, the bit line BL2, the bit line BL3, and the other part of the bit line BL4) in the same main memory block MB can be used for redundancy. Repair or error checking and correction to maintain the expected effective memory capacity of the memory device and improve performance.

A defect occurs in the main memory block MB, for example, at least one of the word line WL1, the word line WL2, the word line WL3, and the word line WL4 is defective, so that all the memory cells in the main memory block MB are not emitted. When performing the function, the backup memory block EB can be used for block repair. In one embodiment, when the main bit line MBL (for example, the bit line BL1, the bit line BL2, the bit line BL3, and a part of the bit line BL4) in the backup memory block EB is executed, a defect occurs. When the NAND string cannot perform the function, the backup bit line EBL in the same backup memory block EB can be used (for example, the bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4) Perform redundancy repair or error checking and correction to maintain the expected effective memory capacity of the memory device and improve performance.

In the embodiment, the ratio A of the number of blocks of the backup memory block EB to the main memory block MB is greater than the ratio B of the number of bit lines of the backup bit line EBL to the main bit line MBL. In particular, when the development trend of the 3D NAND memory device causes the memory block to require a larger number (larger value Q) of the backup memory block EB to be repaired, the block number ratio A is greater than the bit line number ratio B. Make memory devices more in line with trending needs and improve product yield and performance. In one embodiment, for example, the bit line number ratio B is 0.5% to 10%. In one embodiment, for example, the block number ratio A is greater than 10%.

The concept of the present disclosure is not limited to a three-dimensional vertical channel NAND memory device, and may be extended to a three-dimensional vertical gate NAND memory array, for example, in other embodiments.

In other embodiments, the memory block of the memory array can be further divided into a plurality of sub-memory blocks that are independently controlled, thereby improving repair efficiency with a smaller area of repair unit. The concept can be understood by referring to Figures 8 to 9.

FIG. 8 is a schematic diagram of a 3D NAND memory array according to another embodiment. In this example, the main memory block MB1, the main memory block MB2 to the main memory block MBP may each include a sub-primary memory block SMB1 and a sub-primary memory region arranged along the direction in which the word line WL extends. Block SMB2 to sub-primary memory block SMBZ. The backup memory block EB1 to the backup memory block EBQ may each include a secondary backup memory block SEB1, a secondary backup memory block SEB2, and a secondary backup memory block SEBZ arranged along the direction in which the word line WL extends. Where Z is a positive integer.

Please refer to FIG. 9 , which illustrates an equivalent circuit diagram of a memory block of a 3D NAND memory array according to an embodiment. For example, the plurality of sub-memory blocks SB of the memory block (such as the sub-memory block SB1 and the sub-memory block SB2 shown in FIG. 9) may each have an independently controllable ground line GND, Characters between the ground selection line GSL, the serial selection line SSL1, the serial selection line SSL2, the serial selection line SSL3, and the ground selection line GSL and the serial selection line SSL1, the serial selection line SSL2, and the serial selection line SSL3 Line WL1, word line WL2, word line WL3, and word line WL4. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 of the secondary memory block SB1 may be collectively referred to as a word line group WLG1, and the word line WL1 of the secondary memory block SB2. The element line WL2, the word line WL3, and the word line WL4 may be collectively referred to as another word line group WLG2. In the upper view of the memory array (see the concept of FIG. 2), the bit line BL1, the bit line BL2, the bit line BL3, and the bit line BL4 are sequentially arranged in an array direction. In this example, the word line WL1, the word line WL2, the word line WL3, and the word line WL4 of the secondary memory block SB1 are alternately defined with the one-bit line group SLG1 including the bit line BL1 and the bit line BL2. The memory cell array is output, and the bit line group SLG1 is electrically connected to a sub page buffer. The word line WL1, the word line WL2, the word line WL3, and the word line WL4 of the secondary memory block SB2 are interleaved with another bit line group SLG2 including the bit line BL3 and the bit line BL4 to define a memory cell. The array, and the bit line group SLG2 is electrically connected to another sub page buffer.

The sub-memory block of the present disclosure is not limited to a bit line group composed of two bit lines. In other embodiments, the secondary memory block may also use a bit line group designed with other bit line numbers. For example, a bit line group of a secondary memory block uses three bit lines each. The bit line group of the secondary memory block may have a different number of bit lines.

The memory block shown in FIG. 9 may be the main memory block MB, that is, the secondary memory blocks SB1, SB2 may be the secondary main memory block SMB. Alternatively, the memory block may be the backup memory block EB, that is, the secondary memory blocks SB1, SB2 may be the secondary backup memory block SEB.

Referring to FIG. 9, for example, when at least one of the word line WL1, the word line WL2, the word line WL3, and the word line WL4 of the secondary memory block SB2 is defective, the secondary memory is caused. When all the memory cells in block SB2 have no performance, the secondary backup memory block SEB can be used for sub-block repair. Taking Fig. 8 as an example, when the secondary memory block SMB1, the secondary memory block SMB2, and the secondary memory block SMBZ have four defects, the secondary backup memory block SEB1 can be used correspondingly. Four of the backup memory block SEB2 to the secondary backup memory block SEBZ are repaired by the secondary block.

In some embodiments, as shown in FIG. 10 and FIG. 11, the memory block is not divided into sub-memory blocks, and when the same number of defects occur in the main memory block MB, a backup memory area may occur. Block EB patching problem. In other words, the memory device having the sub-memory block of Fig. 8 can improve the repair efficiency with a smaller repair unit than the memory device having no sub-memory block in Fig. 10.

In an embodiment, the bit line BL of the secondary memory block may include a primary bit line MBL and a backup bit line EBL.

For example, FIG. 12 is a schematic diagram of a memory array according to still another embodiment, which differs from the memory array shown in FIG. 8 in that the secondary memory blocks each include a (primary) bit line region. MBLR and (backup) bit line area EBLR.

In some embodiments, a defect occurs in the main bit line MBL of the (primary) bit line region MBLR (or the memory channel to which it is connected), causing the memory cell (serial) corresponding to the main bit line MBL to fail to perform. Redundancy repair or error checking and correction can be performed using the backup bit line EBL in the (backup) bit line area EBLR to maintain the expected effective memory capacity of the memory device and improve performance.

In one embodiment, when the main bit line MBL in the secondary memory block SMB is defective and the corresponding NAND string cannot perform the function, the backup bit line in the same primary memory block SMB can be used. EBL performs redundancy repair or error checking and correction.

When the SMB of the secondary memory block is defective, for example, at least one of the word lines WL is defective, and all the memory cells in the secondary memory block SMB have no effect, the secondary backup memory block SEB may be used. Perform sub block repair.

In an embodiment, when the main bit line MBL in the executed secondary backup memory block SEB is defective, and the corresponding NAND string cannot perform the function, the backup in the same backup memory block SEB can be used. The bit line EBL performs redundancy repair or error checking and correction.

In the embodiment, the ratio of the number of blocks of the secondary backup memory block SEB to the secondary memory block SMB (that is, the number of secondary backup memory blocks SEB (ie, QxZ) is divided by the secondary memory block SMB. The number (i.e., PxZ) is equal to the block number ratio A. In an embodiment, the block number ratio A is greater than the bit line number ratio B. In one embodiment, for example, the bit line number ratio B is 0.5% to 10%. In one embodiment, for example, the block number ratio A is greater than 10%.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

MBLR‧‧‧ bit line area

EBLR‧‧‧ bit line area

MMR‧‧‧ memory array area

EMR‧‧‧Memory Array Area

MB1, MB2, MBP‧‧‧ memory blocks

EB1, EBQ‧‧‧ backup memory block

MBL1, MBL2, MBLN‧‧‧ main bit line

EBL1, EBL2, EBLK‧‧‧ backup bit line

BL1, BL2, BL3, BL4‧‧‧ bit line

SSL, SSL1, SSL2, SSL3‧‧‧ tandem selection line

GSL‧‧‧ Grounding selection line

GND‧‧‧ Grounding wire

WL1, WL2, WL3, WL4‧‧‧ character lines

CS‧‧‧Step contact

CP‧‧‧Contact column

SMB1, SMB2, SMBZ‧‧‧ primary memory blocks

SEB1, SEB2, SEBZ‧‧‧ backup memory blocks

SB1, SB2‧‧‧ memory blocks

Figure 1 is a schematic illustration of a memory device in accordance with an embodiment. 2 is a top view of a bit line region and a bit line region, according to an embodiment. FIG. 3 is a schematic diagram of a memory array region and a memory array region according to an embodiment. 4 is a circuit diagram of a memory block of, for example, a 2D NAND memory array, in accordance with an embodiment. 5 is a top view of a memory block of a three-dimensional vertical channel (3D VC) NAND memory device, in accordance with an embodiment. FIG. 6 is a perspective view of a memory block of a three-dimensional vertical channel (3D VC) NAND memory device according to an embodiment. FIG. 7 is an equivalent circuit diagram of a memory block according to an embodiment. FIG. 8 is a schematic diagram of a 3D NAND memory array according to another embodiment. FIG. 9 is a schematic diagram showing an equivalent circuit of a memory block of a 3D NAND memory array according to another embodiment. FIG. 10 is a schematic diagram of a memory array of an embodiment. 11 is a schematic diagram showing an equivalent circuit of a memory block of an embodiment. FIG. 12 is a schematic diagram of a memory array according to another embodiment.

Claims (10)

A memory device includes a memory array, wherein the memory array includes a main memory block and a backup memory block, and the memory array includes a main bit line and a backup bit line, wherein the backup memory area The ratio A of the block to the main memory block is greater than the ratio B of the one bit line of the backup bit line to the main bit line. The memory device of claim 1, wherein the bit line number ratio B is 0.5% to 10%, and the block number ratio A is greater than 10%. The memory device of claim 1, wherein the primary memory block and the backup memory block each include a portion of the primary bit line and a portion of the backup bit line. The memory device of claim 1, wherein the backup bit line is used for redundancy repair when the main bit line and/or the memory cell corresponding to the main bit line is defective (redundancy) Repair) or Error Checking and Correcting (ECC), which is used to perform block repair when a defect occurs in the main memory block. The memory device of claim 1, wherein the main memory block comprises a plurality of sub-main memory blocks, each of the main memory blocks comprising a word line and a ground selection line, The primary memory blocks each independently control the word line and the ground selection line. The memory device of claim 1, wherein the main memory block comprises a plurality of sub-main memory blocks, the main memory block comprising a plurality of bit lines, a plurality of ground selection lines and a plurality of word lines, wherein the bit lines are divided into a plurality of bit line groups by a group of at least two bit lines, and the word lines are corresponding to a plurality of bit line components a word line group, each of the primary memory blocks including one of the bit line groups, one of the ground selection lines and one of the word line groups, and the second main memory The plurality of word line groups of the block are controlled independently of each other, and the ground selection lines of the second main memory blocks are controlled independently of each other. The memory device of claim 1, wherein the backup memory block comprises a plurality of secondary backup memory blocks, each of the backup memory blocks comprising a word line and a ground selection line. The backup memory blocks each independently control the word line and the ground selection line. The memory device of claim 1, wherein the backup memory block comprises a plurality of secondary backup memory blocks, the backup memory block comprising a plurality of bit lines and a plurality of word lines. The bit lines are divided into a plurality of bit line groups by a group of at least two bit lines, and the word lines are corresponding to the plurality of word line groups. The backup memory blocks each include one of the bit line groups and one of the word line groups, and the word line groups of the backup memory blocks are controlled independently of each other. The memory device of claim 1, wherein the backup memory block comprises a plurality of secondary backup memory blocks, the backup memory block comprising a plurality of bit lines and a plurality of ground selection lines. The bit lines are divided into a plurality of bit line groups by a group of at least two bit lines, and the backup memory blocks each include one of the ground selection lines and the bits. One of the sets of the meta-line, the ground selection lines of the backup memory blocks are controlled independently of each other. The memory device of claim 1, wherein the memory array comprises a 3D NAND string.