TWI646550B - Non-volatile memory and program method thereof - Google Patents

Abstract

Non-volatile memory and its writing method. The method for writing non-volatile memory includes: setting a first increment amount, and sequentially writing a plurality of non-volatile memory cells by sequentially providing a plurality of first pulses of voltage increment according to the first increment amount in the first time interval. And setting a second incrementing amount, wherein the second time interval after the first time interval is followed by sequentially providing a plurality of second pulses of increasing voltage according to the second increasing amount to perform a writing operation on the non-volatile memory cell, wherein The first increment is less than the second increment.

Description

Non-volatile memory and its writing method

The present invention relates to a non-volatile memory and a method of writing the same, and more particularly to a method of writing a non-volatile memory that can reduce bit line interference.

Please refer to FIG. 1. FIG. 1 is a diagram showing a threshold voltage change of a write operation of a flash memory in a conventional technique. In the prior art, when a memory operation is performed on a memory cell of a flash memory, a sequentially increasing pulse is generated according to a fixed increment value ISPP to be written by an incremental step pulse. The (Incremental Step Pulse Programming) method performs a write operation on a memory cell. As the pulse is applied successively, the threshold voltage of the memory cell can be sequentially shifted toward the reference voltage value PV, and the memory cell that completed the write operation in the previous stage is as shown by the threshold voltage distribution curve 110. Wherein, the width of the threshold voltage distribution curve 110 can be equal to the value of the increment value ISPP without considering other non-ideal effects (such as read noise, program noise, etc.). . Here, in order to simplify the description, some non-ideal effects will be ignored to facilitate explanation.

Then, the incremental step pulse writing operation is continuously performed on the memory cell, and the threshold voltage distribution curve 110 of the memory cell that completes the writing operation in the early stage causes further movement due to the bit line interference phenomenon (bit line interference) (away from the reference) The voltage value PV) becomes the threshold voltage distribution curve 110', and the memory cells that complete the write operation later are as shown by the threshold voltage distribution curve 120.

When all of the memory cells complete the write operation, in conjunction with the threshold voltage profiles 110' and 120, the threshold voltage distribution of the memory cells can be the threshold voltage profile 130. Here, it can be clearly found that the width BW1 of the threshold voltage distribution curve 130 is increased by the bit line interference phenomenon BI, so that the reading space of the memory cell and/or the current overdrive is reduced, and the flash is increased. The read failure rate of the memory cell.

The invention provides a non-volatile memory and a writing method thereof, which can reduce the influence of bit line interference in a writing operation.

The method for writing a non-volatile memory of the present invention includes: setting a first increment amount, sequentially providing a plurality of first pulses of voltage increments to a plurality of non-volatile memory cells according to a first increment amount in a first time interval And performing a write operation; and setting a second increment amount, and writing a plurality of second pulses sequentially increasing in voltage according to the second increment amount in the second time interval after the first time interval to write the non-volatile memory cell The action, wherein the first increment is less than the second increment.

The non-volatile memory of the present invention includes a memory cell array and a controller. The memory cell array includes a plurality of non-volatile memory cells. The controller is coupled to the non-volatile memory cell, configured to: set a first incrementing quantity, and sequentially provide a plurality of first pulses of increasing voltage according to the first increasing amount in the first time interval to perform the plurality of non-volatile memory cells a write operation; and, in the second time interval after the first time interval, sequentially providing a plurality of second pulses of increasing voltage according to the second increment to write the non-volatile memory cells Wherein the first increment is less than the second increment.

Based on the above, the present invention performs a write operation on a flash memory cell by providing pulses having different increments in different time intervals. By slowing down (writing with relatively low increments of pulses) and then quickly (writing with relatively high increments of pulses), the effect of bit line interference on memory cell writes is effectively reduced and reduced. The distribution width of the threshold voltage written to the memory cell reduces the read error rate of writing to the memory cell.

The above described features and advantages of the invention will be apparent from the following description.

Please refer to FIG. 2. FIG. 2 is a flow chart of a method for writing a non-volatile memory according to an embodiment of the present invention. In step S210, a first increment is set, and a plurality of first pulses of voltage increment are sequentially supplied according to the first increment in the first time interval to perform a write operation on the plurality of memory cells of the non-volatile memory. . Next, in step S220, a second increment is set, and in the second time interval after the first time interval, a plurality of second pulses of voltage increment are sequentially supplied according to the second increment to non-volatile memory. The memory cell performs a write operation. Wherein, the first increment is less than the second increment.

Referring to FIG. 2 and FIG. 3 simultaneously, FIG. 3 is a diagram showing voltage waveforms of a write operation according to an embodiment of the present invention. The write voltage applied to the non-volatile memory cells of the non-volatile memory is generated in the form of a pulse. In the first time interval T1, the pulse of the write voltage is generated in such a manner that a first increment value ISPP1 is added each time. For example, in the first time interval T1, the voltage value of the pulse WVP2 is equal to the voltage value of the previously generated pulse WVP1 plus a first increment value ISPP1. In the second time interval T2, the pulse of the write voltage is generated by adding a second increment value ISPP2 each time, and the second increment value ISPP2 is greater than the first increment value ISPP1. For example, in the second time interval T2, the voltage value of the pulse WVPN+2 is equal to the voltage value of the previously generated pulse WVPN+1 plus a second increment value ISPP2.

Here, please refer to FIG. 4. FIG. 4 is a schematic diagram showing a threshold voltage distribution curve of a non-volatile memory cell during a write operation of a non-volatile memory according to an embodiment of the present invention. In the first time interval T1, the non-volatile memory cells receive the voltage-increasing pulses WVP1~WVPN, and the voltage value of the threshold voltage of the partial non-volatile memory cells is greater than the reference voltage value PV and the writing operation is completed. The threshold voltage distribution of the non-volatile memory cells that complete the write operation is as shown by the threshold voltage distribution curve 410. Wherein, the width of the threshold voltage distribution curve 410 is substantially equal to the first increment value ISPP1.

Then, in the second time interval T2, the non-volatile memory cells receive the pulse WVPN+1~WVPM with increasing voltage. At the same time, the threshold voltage profile 410 will move away from the reference voltage value PV due to bit line interference and become a threshold voltage profile 410'. The other part of the non-volatile memory cell changes its threshold voltage according to the write action of the pulse WVPN+1~WVPM, and obtains the threshold voltage distribution curve 420. It should be noted that the width of the threshold voltage distribution curve 420 may approach the second incremental value ISPP2 under ideal conditions, and the threshold voltage distribution curve 420 may be completely under the premise that the second incremental value ISPP2 is greater than the first incremental value ISPP1. Or partially wrapped with a threshold voltage distribution curve 410'. That is, by combining the threshold voltage distribution curves 420 and 410', a threshold voltage distribution curve 430 of the threshold voltage of all non-volatile memory cells that have been written can be obtained. The width of the threshold voltage profile 430 will ideally approach the second incremental value ISPP2, ie the width BW2. Wherein, the width BW2 may be smaller than the width BW1 as shown in FIG.

It is not difficult to know from the above description that the embodiment of the present invention can be set to be smaller than the incremental value ISPP in the prior art by setting the first incremental value ISPP1, and equal to the incremental value ISPP in the prior art by setting the second incremental value ISPP2. In this way, with the writing method performed by the embodiment of the present invention, the threshold voltage distribution curve 430 of the threshold voltage of the non-volatile memory cell having a relatively small width can be obtained, and the reading error rate of the non-volatile memory cell can be reduced.

Referring to FIG. 3 again, it should be noted that in the embodiment of the present invention, the first time interval T1 and the second time interval T2 may be connected, or may not be consecutively generated. In the embodiment in which the first time interval T1 and the second time interval T2 do not continuously occur, in the third time interval between the first time interval T1 and the second time interval T2, the second incremental value ISPP2 may be set. And generating a third incremental value of the first incremental value ISPP1, and sequentially providing a plurality of third pulses of voltage increment according to the third incremental amount in the third time interval to perform a writing operation on the non-volatile memory cell.

Further, the setting of the length of time for the first time interval T1 can be determined in different ways. In one embodiment, in the first time interval, after each pulse WVP1-WVPN is applied to perform a write operation, the embodiment of the present invention can perform a verification action on the non-volatile memory cell and obtain a verification result. The verification operation can read the threshold voltage of the non-volatile memory cell, and judge whether the non-volatile memory cell has completed the writing operation by the result of the reading. In terms of details, it can be determined whether the threshold voltage of each non-volatile memory cell is greater than the reference voltage value PV, and the number of passes of the non-volatile memory cell threshold voltage greater than the reference voltage value PV is calculated. The first time interval T1 can be terminated by comparing the number of passes with a preset set value. Wherein, when the number of passes is greater than a preset set value, the first time interval T1 may be terminated.

The part about the set value can be obtained by multiplying the total number of non-volatile memory cells by a preset ratio value. For example, the preset scale value can be set to 30%, that is, the first time interval T1 can be ended when half of the non-volatile memory cells complete the write action.

Further, the setting of the length of time in the first time interval T1 can be determined by the number of write pulses set in advance. For example, the first time interval T1 and the second time interval T2 can be switched from the fourth write pulse. The number of write pulses can also be dynamically fed back through other mechanisms to compensate for changes in the write speed as a result of the write erase cycle.

Incidentally, in the second time interval T2, after each pulse WVPN+1~WVPM is applied to the non-volatile memory cell to perform the writing operation, the verification operation may also be performed for the non-volatile memory cell. And to determine whether the non-volatile memory cell write action has been completed. After all the writing operations of the non-volatile memory cells have been completed, the second time interval T2 may be ended.

According to the above description, it can be known that the effect of the bit line interference on the threshold voltage shift of the non-volatile memory cell can be effectively reduced by the writing method of the incremental step pulse programming. The width of the distribution curve of the threshold voltage of the non-volatile memory cells after writing can be effectively controlled, and the reading error rate of the non-volatile memory cells can be reduced.

Incidentally, the non-volatile memory of the embodiment of the present invention may be a two-dimensional reverse (NAND) flash memory or a three-dimensional inverse flash memory. The non-volatile memory of the embodiment of the present invention may be a single level cell (SLC) flash memory, a multi-level cell (MLC) flash memory, or a third-order storage flash memory. Triple level cell (TLC) or quadruple level cell (QLC).

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a write operation of a non-volatile memory cell according to another embodiment of the present invention. In this embodiment, when the write operation is performed on the selected memory cell SMC, in addition to directly providing the write voltage Vpgm to the selected memory cell SMC, as shown in FIG. 5, an auxiliary write may be further provided. The pulses VAP1, VAP2 are passed to one or more adjacent memory cells AMC1, AMC2 adjacent to the selected memory cell SMC to adjust the voltage value actually applied to the floating gate FG1 of the selected memory cell SMC. In this embodiment, only one of the auxiliary write pulses VAP1 and VAP2 may be provided to the corresponding adjacent memory cell AMC1 or AMC2, or the auxiliary write pulses VAP1 and VAP2 may be respectively provided to the adjacent memory cells AMC1 and AMC2. The voltage value actually applied to the floating gate FG1 of the selected memory cell SMC is adjusted. The auxiliary write pulse VAP1 (VAP2) applied to the adjacent memory cell AMC1 (AMC2) can adjust the write action by the coupling relationship between the adjacent memory cell AMC1 (AMC2) and the floating gate FG1 of the selected memory cell SMC. , the voltage value on the floating gate FG1, and increase the diversity of the write voltage. Wherein, the voltage value VW on the floating gate FG1 can be calculated according to the formula (1):

VW = (Vpgm)*GCR + (VAP1 + VAP2) * CR + Q/C (1)

Wherein, the GCR is equal to the capacitive coupling ratio of the floating gate FG1 of the selected memory cell SMC, CR is equal to the coupling ratio between the selected memory cell SMC and the adjacent memory cells AMC1, AMC2, and Q is the amount of charge stored by the floating gate FG1. C is the capacitance of the floating gate FG1.

Please refer to FIG. 6 below. FIG. 6 is a schematic diagram of a non-volatile memory according to an embodiment of the present invention. The non-volatile memory 600 includes a controller 610, a memory cell array 620, a power generator circuit 630, a sense amplifier and data entry circuit 640, a bit line decoder 650, and a word line decoding and driver 660. Memory cell array 620 includes a plurality of non-volatile memory cells. The bit line decoder 650 is coupled to the controller 610 and the memory cell array 620 and provides a plurality of bit line signals BL1-BLM. The word line decoding and driver 660 is coupled to the controller 610 and the memory cell array 620 and provides a plurality of word line signals WL1-WLN. The sense amplifier and data input circuit 640 is coupled to the bit line decoder 650 and the controller 610 for receiving the write data WD or transmitting the read data RD. The power generation circuit 630 is coupled to the controller 610 to provide a voltage source for generating the first pulse and the second pulse.

The controller 610 is coupled to the memory cell array 620 and performs the steps shown in FIG. 2 during the write operation. The foregoing embodiments and implementations are described in detail with respect to the relevant implementation details and are not described herein.

In summary, the present invention effectively reduces the threshold voltage distribution of non-volatile memory cells caused by bit line interference when the write operation is effectively slowed down by a slow and fast incremental step pulse stylized write mode. The phenomenon. Effectively reduce the read error rate of non-volatile memory cells after writing, and further improve the performance of non-volatile memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110, 110', 130, 410, 410', 420, 430‧ ‧ critical voltage distribution curve

ISPP‧‧‧ incremental value

BI‧‧‧ bit line interference phenomenon

S210-S220‧‧‧Write step

ISPP1‧‧‧ first incremental value

ISPP2‧‧‧ second incremental value

WVP1~WVPM‧‧‧pulse

T1‧‧‧ first time interval

T2‧‧‧ second time interval

VAP1, VAP2‧‧‧ auxiliary write pulse

SMC‧‧‧Selected memory cells

AMC1, AMC2‧‧‧ adjacent memory cells

FG1‧‧‧ floating gate

600‧‧‧Non-volatile memory

610‧‧‧ Controller

620‧‧‧ memory cell array

630‧‧‧Power generator circuit

640‧‧‧Sensor amplifier and data input circuit

650‧‧‧ bit line decoder

660‧‧‧Word line decoding and driver

BL1-BLM‧‧‧ bit line signal

WL1-WLN‧‧‧ character line signal

BW1, BW2‧‧‧ width

FIG. 1 is a diagram showing a threshold voltage change of a write operation of a flash memory in a conventional technique. 2 is a flow chart showing a method of writing a non-volatile memory according to an embodiment of the present invention. FIG. 3 is a diagram showing voltage waveforms of a write operation according to an embodiment of the present invention. 4 is a schematic diagram showing a threshold voltage distribution curve of a non-volatile memory cell during a write operation of a non-volatile memory according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a write operation of a non-volatile memory cell according to another embodiment of the present invention. 6 is a schematic diagram of a non-volatile memory in accordance with an embodiment of the present invention.

Claims (8)

A method for writing a non-volatile memory includes: setting a first increment amount, sequentially providing a plurality of first pulses of voltage increments to a plurality of non-volatiles according to the first increment amount in a first time interval The memory cell performs a write operation; setting a second increment amount, and sequentially providing a plurality of second pulses of voltage increments according to the second increment amount in a second time interval after the first time interval The memory cell performs a writing operation; in the first time interval, verifying the threshold voltage values of the non-volatile memory cells to obtain a verification result; verifying that the threshold voltage values of the non-volatile memory cells are greater than a preset value a pass-through quantity of a reference voltage value; generating the verification result according to whether the pass-through quantity is greater than a set value; and determining an end time point of the first time interval according to the verification result or a number of write pulses, wherein The first increment is less than the second increment. The method for writing a non-volatile memory according to claim 1, wherein the set value is equal to a product of the total number of the non-volatile memory cells and a predetermined ratio. The method for writing non-volatile memory according to claim 1 of the patent application scope further includes: Setting a third increment amount, in the third time interval of the first time interval and the second time interval, sequentially providing a plurality of third pulses of voltage increment according to the third increment amount to the non-volatile The memory cell performs a write operation, wherein the third increment is greater than the first increment, and the third increment is less than the second increment. The method for writing a non-volatile memory according to claim 1, further comprising: generating an auxiliary write pulse; and selecting, according to each of the first pulse or each of the second pulses, a selected memory cell When the write operation is performed, the auxiliary write pulse is provided to at least one adjacent memory cell adjacent to the selected memory cell to perform an auxiliary write operation on the selected memory cell. The method for writing a non-volatile memory according to claim 1, wherein the non-volatile memory is a two-dimensional inverse flash memory or a three-dimensional inverse flash memory. The method for writing non-volatile memory according to claim 1, wherein the non-volatile memory is a single-order storage flash memory, a multi-level storage flash memory, and a third-order storage flash memory. Or fourth-order storage flash memory. A non-volatile memory, comprising: a memory cell array comprising a plurality of non-volatile memory cells; and a controller coupled to the non-volatile memory cells for: setting a first increment, in a The plurality of first pulses that sequentially increase the voltage according to the first increment in the first time interval are for the non-volatile memory cells a row writing operation; setting a second incrementing amount, and sequentially providing a plurality of second pulses of voltage increments to the non-volatile memories according to the second increasing amount in a second time interval after the first time interval The cell performs a write operation; in the first time interval, verifying the threshold voltage values of the non-volatile memory cells to obtain a verification result; verifying that the threshold voltage values of the non-volatile memory cells are greater than a preset reference a pass number of the voltage value; generating the verification result according to whether the pass quantity is greater than a set value; and determining an end time point of the first time interval according to the verification result or a number of write pulses, wherein the An increment is less than the second increment. The non-volatile memory of claim 7, further comprising: a one-line decoder coupled to the controller and the memory cell array to provide a plurality of bit line signals; a word line decoding And a driver coupled to the controller and the memory cell array to provide a plurality of word line signals; a sense amplifier and a data input circuit coupled to the bit line decoder and the controller for receiving a write Data or a read data; and a power generating circuit coupled to the controller to provide a voltage source for generating the first pulse and the second pulses.