TWI642112B - Semiconductor memory device - Google Patents

Abstract

According to an embodiment, the semiconductor memory device includes a row decoder and a memory cell array having a first block. The first block includes: a first region; a second region that is adjacent to the first region in the first direction; and a third region that connects the first region and the second region. The memory cell array further includes: a first insulating layer that fills the first groove between the first region and the second region and is in contact with the third region; a first contact plug that is disposed in the first insulating layer And is electrically connected to the column decoder; and the first wiring layer is connected to select the gate line and the first contact plug.

Description

Semiconductor memory device Cross-reference to related applications

This application is based on and claims the benefit of priority of PCT Application No. PCT / JP2016 / 050888 filed on January 13, 2016, the entire contents of which are incorporated herein by reference.

The embodiments described in this case generally relate to a semiconductor memory device.

A NAND (Not-AND) type flash memory is known in which memory cells are arranged in three dimensions.

Generally speaking, according to an embodiment, a semiconductor memory device includes: a column decoder disposed on a semiconductor substrate; and a memory cell array disposed above the column decoder and having a first block. The first block includes a first region that extends along a first plane formed by the in-plane direction of the semiconductor substrate, that is, the first direction, and a second direction that is different from the first direction, and that follows The second direction has a first width; the second region extends along the first plane, has a second width larger than the first width along the second direction, and is adjacent to the first region in the first direction; and The third region extends along the first plane, has a third width smaller than the first width in the second direction, and is located between the first region and the second region to connect the two. The first to third regions include a plurality of first word lines that are laminated along the vertical direction of the semiconductor substrate, that is, the third direction, and the first region further includes a layer disposed on the uppermost layer. The first selection gate line on the first character line. The memory cell array further includes: a first insulating layer, which fills a first groove between the first region and the second region, and is in contact with the third region in the second direction; and a first contact plug, which is disposed on the The first insulation layer is electrically connected to the column decoder; and the first wiring layer is connected to the first selection gate line and the first contact plug.

1‧‧‧Memory System

10‧‧‧sensing circuit

11‧‧‧Sensor Amplification

12‧‧‧ Latch circuit

13‧‧‧Connecting Department

14‧‧‧n-channel MOS transistor

14-14‧‧‧line

15‧‧‧n-channel MOS transistor

15-15‧‧‧line

16-16‧‧‧line

17-17‧‧‧line

18-18‧‧‧line

19-19‧‧‧line

20-20‧‧‧line

20 ~ 26‧‧‧n-channel MOS transistor

21-21‧‧‧line

26A-26A‧‧‧line

26B-26B‧‧‧line

27‧‧‧p-channel MOS transistor

28‧‧‧ Capacitor element

40‧‧‧block decoder

50‧‧‧High withstand voltage n-channel MOS transistor

50-0 ~ 50-23‧‧‧‧High withstand voltage n-channel MOS transistor

60‧‧‧ cell area

60-1 ~ 60-4‧‧‧ cell area

100‧‧‧NAND flash memory

110‧‧‧Memory Cell Array

111‧‧‧NAND String

120‧‧‧column decoder

120-0 ~ 120-3‧‧‧column decoder

130‧‧‧Drive circuit

140‧‧‧Sense Amplifier

150‧‧‧Address Register

160‧‧‧Instruction Register

170‧‧‧Sequencer

200‧‧‧ Controller

210‧‧‧Host Interface Circuit

220‧‧‧Built-in memory

230‧‧‧ processor

240‧‧‧ buffer memory

250‧‧‧NAND interface circuit

260‧‧‧ECC circuit

300‧‧‧ host machine

500‧‧‧ semiconductor substrate

501‧‧‧Interlayer insulation film

502‧‧‧Interlayer insulation film

503‧‧‧Interlayer insulation film

700‧‧‧ laminated structure

710‧‧‧Insulation

730‧‧‧ Insulation

AA‧‧‧Dummy component area

ADD‧‧‧Address

ALE‧‧‧Address latch enable signal

BA‧‧‧block address

BL‧‧‧bit line

BL0 ~ BL (L-1) ‧‧‧Bit line

BLC‧‧‧Signal

BLK‧‧‧block

BLK0 ~ BLK3‧‧‧block

BLKa‧‧‧block

BLKb‧‧‧block

BLQ‧‧‧Signal

BLS‧‧‧Signal

BLX‧‧‧Signal

C‧‧‧Xundao

C0‧‧‧contact plug

C1‧‧‧contact plug

C2‧‧‧contact plug

CA‧‧‧Xundao

CB‧‧‧ Channel

CC‧‧‧contact plug

CG‧‧‧Signal cable

CG0 ~ CG18‧‧‧Signal cable

CEL‧‧‧ Cell Division

CLE‧‧‧Instruction latch enable signal

CLK‧‧‧ signal

CMD‧‧‧Directive

CNCT‧‧‧Connecting Department

CP10‧‧‧contact plug

CS‧‧‧contact plug

CU‧‧‧ Cell Unit

CP10 ~ CP13‧‧‧Contact plug

CP20‧‧‧contact plug

CP21‧‧‧contact plug

D1‧‧‧ Cell Wiring

D2‧‧‧ Cell Wiring

DAT‧‧‧ Information

DMY‧‧‧Dummy Area

DY‧‧‧slot

FG‧‧‧ floating gate electrode

GSGS‧‧‧Select gate

GC‧‧‧Gate electrode

GC‧‧‧Gate

IC0 ~ IC2‧‧‧metal wiring layer

IC2A‧‧‧metal wiring layer

IC2B‧‧‧metal wiring layer

IC2C‧‧‧metal wiring layer

IC10‧‧‧wiring layer

IC11‧‧‧wiring layer

IC12-0 ~ IC12-18‧‧‧Wiring layer

IC13‧‧‧wiring layer

INV_S‧‧‧node

I / O‧‧‧I / O signal

LBUS‧‧‧node

LP‧‧‧Logic Plane

LP0 ~ LP3‧‧‧Logic plane

M0‧‧‧Subcellular Wiring

M1‧‧‧Subcellular Wiring

MH‧‧‧Silicon pillar (memory hole)

MT‧‧‧Memory Cell Transistor

MT0 ~ MT18‧‧‧Memory Cell Transistor

R‧‧‧ Channel

R1‧‧‧ area

R2‧‧‧ area

R3‧‧‧ area (depression)

RA‧‧‧ Channel

RB‧‧‧Xundao

RBn‧‧‧ is ready. Busy signal

RC‧‧‧Xundao

RD‧‧‧Column Decoder

RD'‧‧‧Column Decoder

RDa‧‧‧Column Decoder

RDb‧‧‧Column Decoder

RDc‧‧‧Column Decoder

REn‧‧‧Read the enable signal

SA‧‧‧Sense Amplifier

SBARY‧‧‧Sub array

SCOM‧‧‧node

SEN‧‧‧node

SGD‧‧‧Select gate line

SGD0 ~ SGD3‧‧‧Select gate line

SGDD0 ~ SGDD3‧‧‧Signal cable

SGS‧‧‧Select gate line

SGSD‧‧‧Signal cable

SL‧‧‧Source Line

SRCGND‧‧‧node

SSRC‧‧‧node

ST‧‧‧Choose a transistor

ST1‧‧‧Select transistor

ST2‧‧‧Select transistor

STB‧‧‧Signal

SLT1‧‧‧Slit

SLT2‧‧‧Slit

SU‧‧‧ String Unit

SU ~ SU3‧‧‧‧ String Unit

TG‧‧‧Signal (signal cable)

V1‧‧‧contact plug

VDD‧‧‧ supply voltage

WEn‧‧‧ write enable signal

WL0 ~ WL18‧‧‧Character line

WLHU‧‧‧Character wire terminal

X‧‧‧ direction

XXL‧‧‧Signal

Y‧‧‧ direction

YLOG‧‧‧ Operation Circuit

Z‧‧‧ direction

Fig. 1 is a block diagram of a memory system of the first embodiment; Fig. 2 is a circuit diagram of blocks included in the semiconductor memory device of the first embodiment; Figs. 3 and 4 are column decoders of the first embodiment and The circuit diagram of the sense amplifier; Figure 5 is the plan layout of the memory cell array and drive circuit of the first embodiment; Figure 6 is the plan layout of the memory cell array of the first embodiment; Figure 7 is the memory of the first embodiment Plan layout of the area under the cell array; Figure 8 is a sectional view schematically showing the memory cell array and the area under the memory cell array of the first embodiment; Figure 9 is a plan layout of the sub-array of the first embodiment; Figure 10 and Figure 11 is the plan layout of the cell unit of the first embodiment; Figures 12 and 13 are the plan layout of the cell area and lane (R) of the first embodiment; Figure 14 is along line 14-14 of Figure 6 Fig. 15 to Fig. 20 are cross-sectional views taken along lines 15-15, 16-16, 17-17, 18-18, 19-19, and 20-20 of Fig. 11, respectively; Sectional views taken along lines 21-21 of Fig. 12 and Fig. 13; Fig. 22 shows the connection between the character line and the column decoder of the first embodiment Layout diagram of the relationship; FIG. 23 is a plan view of the area under the memory cell array of the second embodiment; FIG. 24 is a plan view showing the layout of the area R2 of FIG. 23 in detail; Floor plan Fig. 26 is a sectional view taken along lines 26A-26A and 26B-26B of Fig. 25; Figs. 27 and 28 are plan layout views of the channel R of the first modification example and the second modification example of the first embodiment; and 29 to 31 are plan views of the cell areas of the first modification, the second modification, and the third modification of the third embodiment, respectively.

1. First embodiment

The semiconductor memory device of the first embodiment will be described. In the following, as a semiconductor memory device, a three-dimensional laminated NAND-type flash memory in which memory cells are laminated three-dimensionally on a semiconductor substrate is described as an example.

1.1 About composition

1.1.1 About the overall composition of the memory system

First, the approximate overall configuration of a memory system including a semiconductor memory device according to this embodiment will be described using FIG. 1. FIG. 1 is a block diagram of a memory system according to this embodiment.

As shown in the figure, the memory system 1 includes a NAND flash memory 100 and a controller 200. The NAND-type flash memory 100 and the controller 200 can be combined to form a semiconductor device. For example, a memory card such as an SD ^TM card or an SSD (solid state drive: solid state drive ⁾ can be used as an example. )Wait.

The NAND-type flash memory 100 has a plurality of memory cells and stores data non-volatilely. The controller 200 is connected to the NAND flash memory 100 through a NAND bus, and is connected to the host machine 300 through a host bus. And the controller 200 controls the NAND-type flash memory 100 or responds to a command received from the host machine 300 to access the NAND-type flash memory 100. The host machine 300 is, for example, a digital camera or a personal computer, and the host bus is, for example, a bus according to the SD ^TM interface.

NAND buses transmit and receive signals in accordance with the NAND interface. The specificity of the signal Examples are instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, and ready. Busy signal RBn and input / output signal I / O.

The signals CLE and ALE are signals to notify the NAND flash memory 100 of the input signal I / O to the NAND flash memory 100 as instructions and addresses, respectively. The signal WEn is a signal that is accurately set at a low position and is used for taking input signal I / O into the NAND flash memory 100. In addition, "established" means a state in which a signal (or logic) is made effective (acted), whereas the term "negate" means that a signal (or logic) is made ineffective (ineffective) status. The signal REn is also a signal that stands accurately at a low position and is used to read the input signal I / O from the NAND flash memory 100. Ready. The busy signal RBn is a signal indicating whether the NAND flash memory 100 is in a ready state (a state that can receive a command from the controller 200) or a busy state (a state that cannot receive a command from the controller 200). Quasi indicates busy status. The input / output signal I / O is, for example, an 8-bit signal. In addition, the input / output signal I / O is an entity of data transmitted and received between the NAND flash memory 100 and the controller 200, and includes instructions, addresses, writing data, and reading data.

1.1.2 About the composition of the controller 200

Next, the details of the configuration of the controller 200 will be described using FIG. 1. As shown in FIG. 1, the controller 200 includes a host interface circuit 210, a built-in memory (RAM: Random-Access Memory) 220, a processor (CPU: Central Processing Unit, central processing unit) 230, and a buffer. The memory 240, the NAND interface circuit 250, and an ECC (Error Correcting Code) circuit 260.

The host interface circuit 210 is connected to the host machine 300 via the host bus, and transmits commands and data received from the host machine 300 to the processor 230 and the buffer memory 240, respectively. Furthermore, in response to a command from the processor 230, the data in the buffer memory 240 is transmitted to the host machine 300.

The processor 230 controls the overall operation of the controller 200. For example, when the processor 230 receives a write command from the host machine 300, it responds to the write command to the NAND interface. Route 250 issues a write command. The same applies to reading and erasing. In addition, the processor 230 executes various processes, such as averaging, for managing the NAND flash memory 100.

The NAND interface circuit 250 is connected to the NAND-type flash memory 100 via a NAND bus and controls communication with the NAND-type flash memory 100. And, based on a command received from the processor 230, the signals ALE, CLE, WEn, and REn are output to the NAND flash memory 100. In addition, at the time of writing, the write instruction issued by the processor 230 and the write data in the buffer memory 240 are transmitted as input / output signals I / O to the NAND flash memory 100. When reading, the read instruction issued by the processor 230 is used as the input / output signal I / O to the NAND flash memory 100, and the data read from the NAND flash memory 100 is used as the input and output. The signal I / O is received and transferred to the buffer memory 240.

The buffer memory 240 temporarily holds written data or read data.

The built-in memory 220 is a semiconductor memory such as a DRAM (Dynamic Random Access Memory), and is used as a work area of the processor 230. In addition, the built-in memory 220 holds firmware for managing the NAND flash memory 100, various management tables, and the like.

The ECC circuit 260 performs data error correction (ECC: Error Checking and Correcting) processing. That is, the ECC circuit 260 generates a parity based on the written data when writing the data, generates a syndrome from the parity during reading, detects an error, and corrects the error. In addition, the CPU 230 may have a function of the ECC circuit 260.

1.1.3.1 About the composition of NAND flash memory 100

Next, the configuration of the NAND flash memory 100 will be described. As shown in FIG. 1, the NAND flash memory 100 includes a memory cell array 110, a column decoder 120 (120-0 to 120-3), a driving circuit 130, a sense amplifier 140, an address register 150, and an instruction. Register 160 and sequencer 170.

The memory cell array 110 includes a plurality of non-volatile memory cells such as four blocks BLK (BLK0 ~ BLK3). And the memory cell unit 110 memorizes the data given from the controller 200.

The column decoders 120-0 to 120-3 are set corresponding to the blocks BLK0 to BLK3, respectively, and the corresponding block BLK is selected. In addition, a plurality of blocks BLK can also be selected by a row decoder. Such a structure is described in, for example, US Patent Application No. 13 / 784,512 filed on March 4, 2013, "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Semiconductor memory device) ". The entire application is incorporated herein by reference.

The driving circuit 130 outputs a voltage to any one of the selected blocks BLK0 to BLK3 via the column decoders 120-0 to 120-3.

When data is read out, the sense amplifier 140 senses the data read from the memory cell array 110 and outputs the data DAT to the controller. When data is written, the write data DAT received from the controller 200 is transmitted to the memory cell array 110.

The address register 150 holds the address ADD received from the controller 200. The command register 160 holds the command CMD received from the controller 200.

The sequencer 170 controls the overall operation of the NAND flash memory 100 based on the instruction CMD held by the instruction register 160. In addition, when setting a ROM (Read-Only Memory) fuse, the address of the ROM fuse data is held in the address register 150, and based on the information, the sequencer 170 is stored in the sequencer 170. The ROM fuse register is accessed, and the value of the register is changed. The SetFeature command for the NAND interface is also the same. The SetFeature instruction is an instruction issued by the controller 200 and used to set various parameters of the NAND flash memory 100. If the SetFeature instruction is set in the instruction register, the parameter data sent from the controller 200 after the SetFeature instruction will be set in various registers in the sequencer 170.

1.1.3.2 The circuit configuration of the memory cell array 100.

Next, the circuit configuration of the memory cell array 110 will be described. Figure 2 is a circuit diagram of any block BLK, and other blocks BLK also have the same structure.

As shown in the figure, the block BLK includes, for example, four string units SU (SU0 ~ SU3). Each string unit SU includes a plurality of NAND strings 111.

Each of the NAND strings 111 includes, for example, 19 memory cell transistors MT (MT0 to MT18) and select transistors ST (ST1, ST2).

The memory cell transistor MT includes a laminated gate including a control gate and a charge accumulation layer, and holds data non-volatilely. The number of memory cell transistors MT is not limited to 19, and the number is unlimited. The charge accumulation layer may be formed on a conductive layer (FG structure) or an insulating layer (MONOS structure). The plurality of memory cell transistors MT have their current paths connected in series between the selection transistors ST1 and ST2. The current path of the memory cell transistor MT18 at one end of the series connection is connected to one of the current paths of the selection transistor ST1, and the current path of the memory cell MT0 at the other end is connected to one end of the current path of the selection transistor ST2 .

The gates of the selection transistors ST1 of each of the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3, respectively. On the other hand, the gate of the selection transistor ST2 is commonly connected to the same selection gate line SGS between a plurality of string cells. In addition, the control gates of the memory cell transistors MT0 to MT18 located in the same block are connected in common to the word lines WL0 to WL18, respectively.

That is, the word lines WL0 to WL18 and the selection gate line SGS are connected in common to a plurality of string units SU0 to SU3 in the same block BLK. In contrast, the selection gate line SGD is pressed even in the same block. Each string of units SU0 ~ SU3 is independent.

In addition, the other end of the current path of the selection transistor ST1 of the NAND string 111 located in the same column among the NAND strings 111 arranged in a matrix in the memory cell array 110 is commonly connected to any bit line BL (BL0 ~ BL (L-1), (L-1) is a natural number of 1 or more). That is, the bit line BL is connected to the NAND string 111 in common among the plurality of string units SU, and is further connected to the plurality of regions. The NAND strings 111 are also commonly connected between the blocks BLK. The other end of the current path of the selection transistor ST2 is commonly connected to the source line SL. The source line SL is connected to the NAND string 111 in common among a plurality of blocks, for example.

The data of the memory cell MT located in the same block can be erased in batches. In contrast, the reading and writing of data are performed in batches on a plurality of memory cell MTs that are commonly connected to any word line WL for any string of cells SU in any block.

In addition, erasure of data can be performed in a block BLK unit or a unit smaller than the block BLK. Regarding the erasing method, for example, US Patent Application No. 13 / 235,389, filed on September 18, 2011, "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE" is described. Also, it is described in US Patent Application No. 12 / 694,690, filed on January 27, 2010, "NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE". In addition, US Patent Application No. 13 / 483,610 filed on May 30, 2012, "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE METHOD THEREOF". The entire contents of these applications are incorporated herein by reference.

1.1.3.3 Circuit Configuration of Column Decoder 120

Next, a circuit configuration of the column decoder 120 will be described using FIG. 3. As shown in the figure, the column decoder 120 includes a block decoder 40 and a high withstand voltage n-channel MOS transistor 50 (50-0 to 50-23).

First, the block decoder 40 will be described. The block decoder 40 decodes the block address BA received from the address register 150 when data is written, read, and erased. Furthermore, when the block address BA matches the corresponding block BLK, the signal TG is established. The potential of the established signal TG is set to a voltage at which the transistor 50 is turned on. On the other hand, when the block address BA does not match the block BLK, the signal TG is negated, The potential is set to a voltage (for example, 0 V) in which the transistor 50 is turned off.

Next, the transistor 50 will be described. The transistors 50-0 to 50-18 are used to transmit voltage to the word lines WL0 to WL18 of the selected block BLK. One end of the current path of each of the transistors 50-0 to 50-18 is connected to the word line WL0 to WL18 of the corresponding block BLK, and the other end is connected to the signal lines CG0 to CG18, respectively. Signal line TG.

The transistors 50-19 ~ 50-22 are used for transmitting voltage to the selection gate lines SGD0 ~ SGD3 of the selection block BLK. One end of the current path of each of the transistors 50-19 ~ 50-22 is connected to the selection gate line SGD0 ~ SGD3 of the corresponding block BLK, and the other end is connected to the signal line SGDD0 ~ SGDD3, and the gate is commonly connected to the signal Line TG.

Transistor 50-23 is used to transmit voltage to the selection gate line SGS of the selection block BLK. One end of the current path of the transistor 50-23 is connected to the selection gate line SGS of the corresponding block BLK, the other end is connected to the signal line SGSD, and the gate is commonly connected to the signal line TG.

Therefore, for example, in the column decoder 120 corresponding to the selected block BLK, the transistors 50-0 to 50-23 are turned on. Thus, the word lines WL0 to WL18 are connected to the signal lines CG0 to CG18, the selection gate lines SGD0 to SGD3 are connected to the signal lines SGDD0 to SGDD3, and the selection gate line SGS is connected to the signal line SGSD.

On the other hand, for example, in the column decoder 120 corresponding to the non-selected block BLK, the transistors 50-0 to 50-23 are turned off. Thereby, the word line WL, the selection gate line SGD, and the SGS are separated from the signal lines CG, SGDD, and SGSD.

The signal lines CG, SGDD, and SGSD are commonly used in the column decoders 120-1 to 120-3. In addition, the driving circuit 130 applies a voltage to the signal lines CG, SGDD, and SGS in accordance with the page address PA received from the address register 150. That is, the voltage output from the driving circuit 130 is transmitted to the wirings WL, SGD, and SGS in the selection block via the transistors 50 in any one of the columns of the decoder 120 corresponding to the selection block.

1.1.3.4 Circuit Configuration of Sense Amplifier 140

Next, a circuit configuration of the sense amplifier 140 will be described. As the sense amplifier 140 of this example, although a configuration for discriminating data by sensing a current flowing through a bit line is exemplified below, it may also be a configuration for sensing a voltage.

The sense amplifier 140 includes a sense circuit 10 provided for each bit line BL. FIG. 4 is a circuit diagram of the sensing circuit 10.

As shown in the figure, the sensing circuit 10 generally includes a sensing amplifier section 11, a latch circuit 12, and a connection section 13. Furthermore, two or more latch circuits are provided when each memory cell transistor holds data of two or more bits.

The connection portion 13 connects the corresponding bit line BL and the sense amplifier 11 to control the potential of the bit line BL. The connection section 13 includes n-channel MOS transistors 14 and 15. The transistor 14 is connected to the gate with a signal BLS, and the source is connected to the corresponding bit line BL. The source of the transistor 15 is connected to the drain of the transistor 14, a signal BLC is applied to the gate, and the drain is connected to the node SCOM. The transistor 15 is used to clamp the corresponding bit line BL to a potential corresponding to the signal BLC.

The sense amplifying section 11 senses the data read out to the bit line BL. The sense amplifier section 11 includes n-channel MOS transistors 20 to 26, a p-channel MOS transistor 27, and a capacitor 28.

The transistor 27 is used for charging the bit line BL and the capacitor element 28. A node INV_S is connected to the gate, a drain is connected to the node SSRC, and a power supply voltage VDD is given to the source. The transistor 20 is used to precharge the bit line BL. A signal BLX is given to the gate, the drain is connected to the node SSRC, and the source is connected to the node SCOM. The transistor 22 is used to charge the capacitor 28. The gate is given a signal HLL, the drain is connected to the node SSRC, and the source is connected to the node SEN. The transistor 21 is used to discharge the node SEN when data is sensed. A signal XXL is given to the gate, the drain is connected to the node SEN, and the source is connected to the node SCOM. The transistor 26 is used to fix the bit line BL to a certain potential. The gate is connected to the node INV_S and the drain is connected to the node SCOM. And the source is connected to the node SRCGND.

The capacitive element 28 is charged when the bit line BL is pre-charged, and one electrode is connected to the node SEN, and the other electrode is given a signal CLK.

The transistor 23 is connected to the gate with a signal BLQ, the source is connected to the node SEN, and the drain is connected to the node LBUS. The node LBUS is used to connect the signal path of the sense amplifier 11 and the latch circuit 12. The transistor 24 determines the sensing timing of the data and is used to store the read data to the latch circuit 12. The signal STB is assigned to the gate, and the drain is connected to the node LBUS.

The transistor 25 is used to sense whether the read data is “0” or “1”. The gate is connected to the node SEN, the drain is connected to the source of the transistor 24, and the source is grounded.

The node INV_S is a node in the latch circuit 12, which obtains a level corresponding to the data held by the latch circuit 12. For example, if the selected memory cell is turned on when the data is read, and the node SEN is sufficiently decreased, the node INV_S becomes the "H" level. On the other hand, if the memory cell is selected to be in the OFF state and the node SEN is maintained at a certain potential, the node INV_S becomes the "L" level.

In the above configuration, at the timing when the signal STB is established, the transistor 25 senses the read data based on the potential of the node SEN, and the transistor 24 transmits the read data to the latch circuit 12. Various control signals including the signal STB are given by the sequencer 170, for example.

In addition, as the sensing circuit 10, various configurations can be applied, for example, an application entitled "THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELL" can be applied on March 21, 2011. US Patent Application No. 13 / 052,148. The entire contents of that application are incorporated herein by reference.

1.2 About the Layout and Sectional Structure of NAND Flash Memory 100

Next, a specific example of the planar layout and cross-sectional configuration of the NAND-type flash memory 100 configured as described above is focused on the memory cell array 110, the column decoder 120, and the sense amplifier. The device 140 will be described below.

1.2.1 About the overall composition

First, a rough plan layout and cross-sectional configuration will be described with reference to FIG. 5. FIG. 5 shows a planar layout of the memory cell array 110 and the driving circuit 130. As shown in the figure, the memory cell array 110 includes, for example, four logical planes LP (LP0 to LP3) arranged in the X-axis direction. The logical plane LP is a logical access unit to the memory cell array 110, and multiple logical planes LP can also be accessed at the same time.

The Z-axis direction orthogonal to the X-axis direction is a direction perpendicular to the surface of the semiconductor substrate on which the NAND-type flash memory 100 is formed. The X-axis direction is orthogonal to the Z-axis direction and is one of the in-plane directions of the semiconductor substrate. The Y-axis direction is orthogonal to the Z-axis direction and the X-axis direction, and is a direction different from the X-axis direction in the in-plane direction of the semiconductor substrate.

Each logical plane LP includes, for example, four sub-arrays SBARY arranged in the Y-axis direction. Therefore, in the example of FIG. 5, (4 × 4) sub-arrays SBARY are provided in the memory cell array 110 in the XY plane.

Each of the sub-arrays SBARY includes, for example, four cell areas, two channels C, and two channels R. Four cell regions are arranged in an array of (2 × 2) in the XY plane. Channel C is set between two cell regions adjacent in the X-axis direction, and two cell regions adjacent in the Y-axis direction. Channel R is set in between. The cell area is actually the area for forming the memory cell MT. Moreover, in the cell region, a NAND string 111 is formed by stacking a memory cell MT in the Z-axis direction, and a plurality of blocks BLK are formed by a collection of the NAND string 111. In contrast, the channel C is a connection portion related to the wiring of the bit line BL and the like, and the channel R is a connection portion related to the wiring of the word line or the signal line CG and the like.

In addition, the channels C and R are not only arranged in the sub-arrays, but also between adjacent sub-arrays. This situation is shown in FIG. 6. FIG. 6 shows the area R1 of FIG. 5 in detail. As shown in the figure, the channel R is also arranged in a sub array SBARY belonging to each other and adjacent to each other in the Y axis direction. Between the cells. In addition, the channel C is also provided between cell regions belonging to mutually different sub-arrays SBARY (in other words, the logical plane LP) and adjacent in the X-axis direction.

FIG. 7 shows a planar layout of the column decoder 120 and the sense amplifier 140 (arrangement viewed in the XY plane). The column decoder 120 and the sense amplifier 140 are located directly below the memory cell array 110. In FIG. 7, a configuration example of the column decoder 120 and the sense amplifier 140 in an area overlapping with the two logical planes LP (ie, (4 × 2) sub-arrays SBARY) in the Z-axis direction is shown. The column decoder 120 and the sense amplifier 140 are divided into a plurality of regions and formed on a semiconductor substrate. Hereinafter, the divided regions are referred to as a column decoder RD and a sense amplifier SA. Although the description is omitted in FIG. 4, the sensing circuit 10 includes a plurality of latch circuits, and includes an arithmetic circuit that performs operations using data held by the latch circuits. This arithmetic circuit is shown as an arithmetic circuit YLOG in FIG. 7.

As shown in FIG. 7, two sensing amplifier circuits SA, four column decoders RD, and two operation circuits YLOG are arranged directly below one sub-array SBARY. Moreover, when focusing on a certain sub-array SBARY, if it is the example of FIG. 7, a sense amplifier SA is disposed directly below the cell region 60-1 located on the upper left of the paper surface of FIG. 7. In addition, the column decoder RD, the operation circuit YLOG, and the column decoder are sequentially arranged along the Y-axis direction in the Y-axis direction directly below the cell area 60-2 adjacent to the cell area 60-1 via the channel R. RD. Further, the column decoder RD, the arithmetic circuit YLOG, and the column decoder RD are arranged in order along the Y-axis direction in the X-axis direction directly below the cell region 60-3 adjacent to the cell region 60-1. . A sense amplifier SA is disposed directly below the cell region 60-4 adjacent to the cell region 60-3 in the Y-axis direction.

That is, in the area immediately below the memory cell array 110, the sense amplifier SA, the column decoder RD, and the operation circuit YLOG are regularly arranged. That is, the sense amplifier SA is adjacent to the combination of the two column decoders RD and the operation circuit YLOG in either the Y-axis direction or the X-axis direction. In addition, the combination of the column decoder RD and the operation circuit YLOG is also adjacent to the sense amplifier SA in any of the Y-axis direction and the X-axis direction. That is, in the area immediately below the memory cell array 110, there are staggered arrays in both the X-axis direction and the Y-axis direction. The combination of the sense amplifier SA and the column decoder RD and the operation circuit YLOG. In addition, one sense amplifier SA overlaps one cell region 60, and one combination of the column decoder RD and the operation circuit YLOG overlaps one cell region 60.

FIG. 8 is a cross-sectional view of the memory cell array 110 and the area immediately below the memory cell array 110, and shows a typical structure of the sub-array SBARY.

As shown, a sense amplifier 140 and a column decoder 120 are formed on a semiconductor substrate 500. In addition, an interlayer insulating film 501 is formed on the semiconductor substrate 500 by covering the above, and a memory cell array 110 is formed on the interlayer insulating film 501. In addition, an interlayer insulating film 502 is formed on the interlayer insulating film 501 so as to cover the memory cell array 110.

That is, semiconductor elements (such as MOS transistors) included in the sense amplifier 140 and the column decoder 120 are formed on the semiconductor substrate 500. In the interlayer insulating film 501 covering these semiconductor elements, for example, two metal wiring layers (subcellular wirings M0 and M1) are formed. The wiring M1 is formed on an upper layer than the wiring M0. In addition, the electrical connections between the semiconductor elements in the sense amplifier 140 and the column decoder 120 are performed by wirings M0 and M1, and the electricity of the sense amplifier 140 and the column decoder 120 and the memory cell array 110 is performed. Sexual connection. The wiring M0 is connected to the semiconductor substrate 500 or the gate GC through a contact plug CS, and the wiring M0 and M1 are connected to each other through a contact plug V1.

On the interlayer insulating film 501, a memory cell array 110 is formed. In the cell region, a conductive layer (such as a polycrystalline silicon layer or a metal layer) functioning as a source line SL is first formed on the interlayer insulating film 501, and a current path to form a NAND string 111 is formed on the source line SL (Silicon pillar MH that forms the region of the memory cell transistor MT and the channels of the selected transistors ST1 and ST2). Further, on the source line SL, a plurality of conductive layers (for example, a polycrystalline silicon layer) functioning as the selection gate line SGS, the word line WL, and the selection gate line SGD are formed through an insulating film. A charge storage layer is formed between the selection gate line SGS and the word line WL and the silicon pillar MH so as to surround the silicon pillar MH. The charge storage layer is a floating gate electrode FG formed of, for example, a conductive layer (polycrystalline silicon layer, etc.). Charge accumulation layer It may also be formed by an insulating film. A gate insulating film is provided between the silicon pillar MH and the floating gate electrode FG, and a block insulating film is provided between the floating gate electrode FG and the selection gate GSGS and the word line WL.

In the cell region, a groove DY penetrating from the uppermost word line to the source line SL is provided, and the inside of the groove DY is filled with an interlayer insulating film 502. In the area shown in FIG. 8, although the conductive layer functioning as the word line WL, the selection gate line SGS, and the source line SL is divided into two areas by the groove DY, the two are not shown in the figure. The area connection shown below (connection part CNCT described later). A contact plug C0 connected to the wiring M1 is provided in the groove DY.

The ends of the selection gate line SGS and the word line WL facing the channel R have a stepped shape. That is, the ends of the selection gate line SGS and the character line WL are processed so as to overlap the upper-layer wiring (the character line WL). In this region, a contact plug CC is formed on the selection gate lines SGS, SGD and the word line WL.

In the channel R and the channel C, a contact plug C0 connected to the wiring M1 is formed in the interlayer insulating film 502.

A contact plug C1 is formed on the silicon pillar MH and the contact plug CC. Further, an interlayer insulating film 502 is formed so as to cover the above structure.

An interlayer insulating film 503 is formed on the interlayer insulating film 502, and two metal wiring layers (cell wirings D1 and D2) are formed in the interlayer insulating film 503. The wiring D2 is formed on an upper layer than the wiring D1. For example, the electrical connection between the memory cell array 110 and the column decoder 120 and the sense amplifier 140 is performed through the wiring D1, and the signal controlling the column decoder 120 or the sense amplifier 140 is transmitted through the wiring D2.

In the cell region, a wiring D1 connected to the contact plug C1 is formed on the interlayer insulating film 502, and these functions as selection gate lines SGD and SGS, word lines WL, bit lines BL, and source lines SL. Features. The wiring D2 is connected to the wiring D1 via a contact plug C2 (not shown).

1.2.2 Details about the sub-array SBARY

Next, the details of the configuration of the sub-array SBARY will be described.

1.2.2.1 About the planar composition of the sub-array SBARY

First, the details of the planar configuration of the sub-array SBARY will be described.

<About the plane structure of the cell area>

FIG. 9 shows any one of the sub-arrays SBARY shown in FIG. 5, and the constituents of the cell region are shown in more detail. As shown in the figure, each of the cell regions included in the sub-array SBARY includes a plurality of cell units CU. Each of the cell units CU includes two blocks BLK (block 1, block 2). Each block BLK includes a cell portion CEL, a character line connection portion WLHU, and a connection portion CNCT.

The cell CEL is a layered body including the source line SL, the selection gate lines SGS and SGD, and the word line WL described in FIG. 8, and further includes a memory hole MH inside and a region of the NAND string 111 .

The wiring portion WLHU is a region for forming a contact plug on the word line WL and the selection gate line SGS. The word plug WL is electrically connected to the transistor 50 of the column decoder RD through the contact plug. The selection gate line SGD is not provided in the wiring portion WLHU. Although the details are described later, the reason is that, as shown in FIG. 8, the selection gate line SGD is connected to the transistor 50 of the column decoder RD via the slot DY in the cell region.

The connection part CNCT is a region for physically connecting the character line WL and the selection gate line of the cell CEL, and the character line WL and the selection gate line SGS of the connection part WLHU.

Furthermore, in each block BLK, a cell portion CEL, a connection portion CNCT, and a wiring portion WLHU are arranged along the Y direction. At this time, in one block BLK, they are arranged in the order of the cell CEL, the connection part CNCT, and the wiring part WLHU along the Y direction. In contrast, in the other block BLK, the wiring part is reversed. WLHU, connecting part CNCT, and cell CEL are arranged in order.

In addition, two cell portions CEL in each cell unit CU are adjacent to each other in the X direction. The two cell CELs are physically separated by a slit SLT2 provided along the Y direction. SLT2 has a through The cell CEL selects the structure of the buried insulating layer in the trenches of the gate lines SGS and SGD and the word line WL.

In addition, the two wiring portions WLHU in each cell unit CU are arranged so as to face each other in the Y direction via the two cell portions CEL arranged in the X direction. The width in the X direction of the wiring portion WLHU is substantially equal to, for example, the width in the X direction of the two cell portions CEL and the width in the X direction of the slit SLT2. In addition, the wiring portion WLHU and the cell portion CEL adjacent to each other in the Y direction are physically separated by a groove DY provided in the X direction. The trench DY has a structure in which an insulating layer is buried in a trench penetrating the source line SL, the selection gate lines SGS and SGD, and the word line WL.

The connection part CNCT is provided between the cell part CEL belonging to the same block and the wiring area WLHU. With the connection portion CNCT, as described above, the selection gate line SGS and the character line WL of the cell CEL are physically connected to the selection gate line SGS and the character line WL belonging to the same block BLK as the cell CEL. . In addition, the width in the X direction of the connection portion CNCT is smaller than the width in the X direction of the cell portion CEL. Therefore, there is a slot DY between the cell CEL and the wiring WLHU in the same block BLK. In other words, in a certain cell unit CU, among the two ends of the cell portion CEL in the Y direction, facing the end portion of the wiring portion WLHU belonging to a block BLK different from the cell portion CEL, the entire surface thereof faces the groove DY. On the other hand, facing the end portion of the wiring portion WLHU that belongs to the same block BLK as the cell CEL (in other words, the wiring portion that is physically connected to the cell CEL through the connection portion CNCT), only a part thereof faces the groove DY ( The remaining areas are connected to the connection CNCT). In other words, the structure of the block BLK when viewed in the XY plane has a thinner shape in the connection part CNCT.

In each cell region, the plurality of cell units having the above-mentioned configuration are physically separated by a slit SLT1 provided along the Y direction. The slit SLT1 has a structure in which an insulating layer is buried in a slot penetrating the selection gate lines SGS and SGD and the word line WL, and is an end portion of the wiring portion WLHU of the block BLK of one of the cell units CU The CEL is provided to the end of the wiring section WLHU of the other block BLK. In addition, although the groove DY is formed in such a manner that the self-selected gate line SGD also penetrates the source line SL, the slits SLT1 and SLT2 need only be selected separately. The gate line SGD and the word line WL may be sufficient, and the source line SL may not be separated.

The shape of the XY plane of the cell unit CU sandwiching the slit SLT1 is linearly symmetrical with respect to the slit SLT1. That is, when looking at the situation of some two cell units CU, the block BLK1 of one cell unit CU and the block BLK1 of different cell units CU adjacent in the X direction are separated by a mutual groove DY. The slits SLT1 are arranged opposite to each other. In this area, the two opposite grooves DY are formed by an etching step performed in a manner crossing the slit SLT1, and the grooves formed by the etching step are filled with an insulating layer. Moreover, the cell CEL of the two is provided in a relative manner with the cell CEL of the block BLK2 interposed therebetween.

On the other hand, the block BLK2 is arranged in such a manner that the connection part CNCT and the cell part CEL are opposite to each other through the slit SLT1. On the contrary, the connection portion CNCT is separated between the two grooves DY. Therefore, the grooves DY of the two blocks BLK2 are different from the previously described BLK1, and are formed as physically different grooves in the etching step.

The above-mentioned slit SLT1 is also provided between the adjacent cell areas in the X direction, and this area is the channel C. The slit SLT1 provided in the channel C has a structure that also penetrates the source line SL. Channel C is set in the Y direction between the cell regions.

In addition, in a cell region adjacent to the Y direction, a region in which the source line SL, the selection gate lines SGS and SGD, and the word line WL are removed, and the removed region is filled with an insulating layer are provided. Regional Department Channel R. The channel R is arranged along the X direction between the cell regions.

The planar configuration of the cell region will be described in more detail with reference to FIGS. 10 and 11. FIG. 10 shows a planar layout of two cell units CU, and FIG. 11 shows the wiring layer formed by the on-cell wiring in FIG. 10. In FIG. 10, the illustration of the contact plug CP10 formed in the groove DY is omitted.

First, the cell CEL will be described. As shown in FIG. 10 and FIG. 11, in the cell CEL, a flat gate-like selection gate line SGS and a character line WL extending in the XY plane are stacked, and a word is provided on the uppermost layer of the multilayer body of the character line WL元 线 WL18. On the character line WL18, A selection gate line SGD (SGD0 to SGD3) having a strip shape along the Y direction is set. The side of the gate line SGD is selected to have a concave-convex shape on the XY plane, and more specifically, a waveform shape.

On the selected gate line SGD, a silicon pillar MH illustrated in FIG. 8 is formed. The silicon pillar MH is formed in such a manner that the gate line SGD is selected to reach the source line SL. In addition, as shown in FIG. 10, the silicon pillar MH is disposed in a staggered manner on the selection gate line SGD.

A metal wiring layer IC0 having a stripe shape along the X direction is formed on the silicon pillar MH. This metal wiring layer IC0 corresponds to the cell wiring D1 described in FIG. 8 and functions as a bit line BL.

Further, a contact plug CP10 is provided at an end portion near the side of the connection portion CNCT among the both end portions along the Y direction of the selection gate line SGD. The contact plug CP10 is used to connect the selection gate line SGD to the transistor 50 of the column decoder RD. More specifically, it is used to connect the conductive layer functioning as the selection gate line SGD to the cell wiring D1. By. Further, a contact plug CP12 is provided in the groove DY. Furthermore, a metal wiring layer IC1 connecting the contact plugs CP10 and CP12 is formed using the cell wiring D1. The contact plug CP12 is formed in an insulating layer in the groove DY, and is connected to the subcellular wiring M1. Via the contact plugs CP10 and CP12 and the wiring layer IC1, the selection gate line SGD is electrically connected to the transistor 50 of the column decoder RD.

In addition, a contact plug CP10 provided in a cell portion CEL belonging to a certain block BLK is connected to a contact plug CP12 provided in a slot DY between the contact portion WLHU and a wiring portion WLHU belonging to the same block BLK. That is, although the cell CEL is in contact with the groove DY at both ends along the Y direction, it is connected to the contact plug provided in the two grooves DY and closer to the groove DY of the contact plug CP10. Plug CP12.

In addition, in the example of FIG. 10 and FIG. 11, no contact plug is provided between DY between a cell CEL and a wiring part WLHU belonging to a block BLK different from the block BLK to which the cell CEL belongs. Plug CP12. However, a part of the contact plug CP12 may be provided in the groove DY. Minute.

Next, the wiring portion WLHU will be described. As shown in FIG. 10 and FIG. 11, in the wiring portion WLHU, a flat gate-shaped selection gate line SGS and a character line WL extending in the XY plane are also stacked. In addition, the wiring region WLHU includes, for example, (5 × 4) rectangular regions, and the surfaces of the selection gate lines SGS and the word lines WL0 to WL18 are exposed in each of the regions. In the example of FIGS. 10 and 11, the wiring layer is exposed at every other layer in each row.

More specifically, in a certain row (referred to as the first row), the upper surfaces of the selection gate lines SGS, the character lines WL1, WL3, WL5, and WL7 are exposed. In the row adjacent to the first row (referred to as the second row), the upper surfaces of the word lines WL0, WL2, WL4, WL6, and WL8 are exposed. The upper surfaces of the character lines WL9, WL11, WL13, WL15, and WL17 are exposed in a row adjacent to the second row (referred to as a third row) with the first row interposed therebetween. Further, in a row adjacent to the first row (referred to as a fourth row) with the second row interposed therebetween, the upper surfaces of the character lines WL10, WL12, WL14, WL16, and WL18 are exposed.

Further, in each row, the closer to the area of the connection part CNCT is, the more the upper wiring layer is exposed. That is, the upper surfaces of the word lines WL7, WL8, WK17, and WL18 are exposed in the column closest to the connection part CNCT, and the selection gate gate line SGS and the character line are exposed in the column closest to the connection part CNCT. WL0, WL9, and WL10.

In addition, contact plugs CP11 are formed on (5 × 4) regions, respectively. The contact plug CP11 is connected to a metal wiring layer IC2 formed using the cell wiring D1. The metal wiring layer IC2 is drawn from the wiring portion WLHU to the channel R. The transistor R is connected to the transistor 50 of the column decoder RD at the channel R (for details, see below).

<About the plane structure of the channel R>

Next, the details of the planar configuration of the channel R will be described using FIG. 12 and FIG. 13. Figures 12 and 13 show the planar layout (XY plane) of the three cell CELs and the two channels R located between them, and a point chain line at the end in the Y-axis direction of Figure 12 and the Y of Figure 13 A dot chain line at one end in the axial direction shows the same position.

As described with reference to FIG. 9, in the channel R, the wiring portions WLHU of the cell regions adjacent in the Y direction are opposite to each other. And in the channel R, the metal wiring layer IC2 formed in the wiring portion WLHU of one is connected to the metal wiring layer IC2 formed in the wiring portion WLHU of the other. Furthermore, a contact plug CP21 is provided in the insulating layer provided in the channel R. The contact plug CP21 is used to connect the word line WL to the transistor 50 of the column decoder RD, and more specifically to connect the metal wiring layer IC2 connected to the word line WL to the subcellular wiring M1. . The contact plugs CP21 are respectively connected to the corresponding metal wiring layer IC2, and further connected to the subcellular wiring M1. Via the wiring layer IC2 and the contact plug CP21, the selection gate line SGS and the word line WL are electrically connected to the transistor 50 of the column decoder RD.

That is, the selection gate line SGS, SGD, and the character line WL are stacked in the cell CEL, and the selection gate line SGD is electrically connected via the contact plug CP12 formed in the groove DY provided in the cell CEL. Sexually linked to the area under the memory cell array. On the other hand, the selection gate line SGS and the word line WL are electrically connected to a region under the memory cell array via a contact plug CP21 formed in the channel R.

In addition, in the channel C, although the bit line BL is electrically connected to the area under the memory cell array, since the planar configuration is substantially the same as that of the channel R, detailed description is omitted.

1.2.2.2 Section composition of the sub-array SBARY

Next, the details of the cross-sectional configuration of the sub-array SBARY described with respect to the planar configuration will be described.

<About the cross-sectional structure of the cell area>

First, a cross-sectional structure of a cell region will be described. FIG. 14 is a cross-sectional view taken along line 14-14 of FIG. 6, and FIG. 15 is a cross-sectional view taken along line 15-15 of FIG.

As described above, the column decoder 120 and the sense amplifier 140 are formed on the semiconductor substrate 500, and a cell region is formed in a region above these. In the cell, a source line SL is first provided on an interlayer insulating film (not shown), a selection gate line SGS is formed on the source line SL, and a plurality of word lines WL are stacked on the selection gate line SGS, and There is a choice on it Gate line SGD. Each wiring layer is electrically separated by an insulating layer.

Further, a silicon pillar MH is provided so as to penetrate the selection gate line SGD and the word line WL to reach the source line SL. A contact plug CP13 is provided on the silicon pillar MH, and a metal wiring layer IC0 functioning as a bit line BL is provided on the contact plug CP13.

Next, the wiring portion WLHU will be described using FIG. 15. The wiring part WLJU is the same as the cell part CEL. A source line SL is provided on the interlayer insulating film of the covered decoder 120 and the sense amplifier 140, and a selection gate line SGS is formed on the source line SL. A plurality of word lines WL are stacked on the line SGS. In the wiring portion WLHU, the gate line SGS and the end of the word line WL facing the channel R have a stepped shape. That is, the lower the wiring layer, the longer the length along the Y-direction, and a region that does not overlap the upper wiring layer.

This situation is shown in FIGS. 16 to 20. 16 to 20 are sectional views taken along lines 16-16, 17-17, 18-18, 19-19, and 20-20 of FIG. 11. As shown in the figure, the areas where the lower wiring layer and the upper wiring layer do not overlap correspond to (5 × 4) areas where the contact plug CP11 is formed as illustrated in FIG. 10. In addition, although not shown in FIGS. 16 to 20, an insulating layer is buried around the contact plug CP11 to electrically insulate the contact plugs CP11 from each other.

Next, the groove DY will be described. As shown in FIG. 13, the groove DY physically separates the source line SL, the selection gate line SGS, and the character line WL between the cell portion CEL and the wiring portion CEL. As described previously, an insulating layer is buried in the trench DY. A contact plug CP12 is formed in the insulating layer. The contact plug CP12 reaches a level from the upper wiring D1 (metal wiring layer IC1) to a lower wiring M1. Furthermore, it is connected to the transistor 50 of the column decoder RD via the subcellular wiring M0. The transistor 50 is located directly below the corresponding cell region.

<About Cross-Sectional Structure of Channel C>

Next, the cross-sectional structure of the channel C will be described using FIG. 14. As described above, in the channel C, the same as the channel R, the layer from the source line SL to the selection gate line SGD is removed. Structure, and is buried by an insulating layer. In the channel C, a contact plug CP20 is disposed in the insulating layer.

As shown in FIG. 14, the contact plug CP20 reaches the level from the cell wiring D1 (metal wiring layer IC0: bit line BL) to the cell wiring M1. Furthermore, it is connected to the transistor 14 of the sense amplifier SA via the subcellular wiring M0. The sense amplifier 14 is located directly below the corresponding cell region.

<About Cross-section Structure of Channel R>

Next, the cross-sectional configuration of the channel R will be described using FIG. 21. FIG. 21 is a sectional view taken along line 21-21 in FIG. 12 and FIG. In the above-mentioned channel R, the laminated structure from the source line SL to the selected gate line SGD is removed, and is buried by the insulating layer. In the channel R, a contact plug CP21 is provided in the insulating layer.

Further, as shown in FIG. 21, the selection gate line SGS and the word line WL opposite to each other across the channel R are connected to the metal wiring layer IC2 in common through the contact plug CP11, respectively. Moreover, in the channel R, the metal wiring layer IC2 is connected to the contact plug CP21.

The contact plug CP20 extends from the level of the upper wiring D1 (metal wiring layer IC2) to the level of the lower wiring M1. Furthermore, it is connected to the transistor 50 of the column decoder RD via the subcellular wiring M0. This transistor 50 is also located directly below the corresponding cell region in the same manner as the transistor 50 connected to the selection gate line SGD.

In addition, the contact plug CP21 formed in the slot DY of the cell region located above the sense amplifier SA is also electrically connected directly below the adjacent cell region through the lower region of the channel R through the sub-cell wiring M1 or M0. Decoder RD.

1.2.2.3 About the connection relationship between Channel R and Channel C

As explained in the above 1.2.2.1 and 1.2.2.2, the selection gate line SGS and the word line WL are led out in the channel R under the memory cell array and connected to the column decoder RD. In addition, the bit line BL is led out under the memory cell array in the channel C and is connected to the sense amplifier SA. Furthermore, the selected gate line SGD is led out to the memory cell array in the slot DY in the cell area. And connected to the column decoder RD.

At this time, in the cell region, there are a person who has a column decoder RD and a person who has a sense amplifier SA. Therefore, the selection of the gate lines SGS, SGD, and the character line WL is only required to connect to the column decoder RD when there is a column decoder RD directly below the cell area, but there is no sense of existence of the column decoder RD In the case of measuring the amplifier SA, it is connected to a column decoder RD directly below the adjacent cell area.

In addition, a plurality of channels C are arranged in the memory cell array, and a bit line BL is connected to the sense amplifier SA in any one of the plurality of channels C, and the bit lines BL and the sense amplifier SA are dispersed. Of connection parts.

The above point will be described using FIG. 22. Fig. 22 shows the planar layout of the sub-array SBARY. As shown in the figure, the sub-array SBARY includes cell regions 60-1 to 60-4, and a sense amplifier SA is provided directly below the cell regions 60-1 and 60-4, and the cell regions 60-2 and 60-3 are directly A combination of a column decoder RD and a calculation circuit YLOG is provided below.

The block BLKa of the cell area 60-1 is opposite to the block BLKa of the cell area 60-3 via the channel RA. The word lines WL and the selection gate lines SGS are connected to each other through the metal wiring layer IC2A, The channel RA is connected to a column decoder RDa (transistor 50) directly below the cell area 60-3. In addition, the selection gate line SGD of the block BLKa of the cell region 60-1 and the selection gate line SGD of the block BLKa of the cell region 60-3 are also connected to the column directly below the cell region 60-3 via the slot DY. Decoder RDa. That is, the two transistors BLKa share the transistor 50.

In the cell area 60-3, the word line WL and the selection gate line SGS of the block BLKb of the cell unit CU are formed with the block BLKa together with another sub-array adjacent to the Y-axis direction through the channel RC. The block BLKb of SBARY is connected to each other by a metal wiring layer IC2C, and is connected to a column decoder RDb (transistor 50) directly below the cell region 60-3 via a channel RC. In addition, the selection gate line SGD of the block BLKb is also connected to the column decoder RDb directly below the cell region 60-3 via the slot DY. That is, the two transistors BLKb share the transistor 50.

In addition, the character line and select gate line SGS of BLKb in the cell 60-1 block are separated from each other. The block BLKb of another sub-array SBARY adjacent to the channel RB in the Y-axis direction is connected to each other by a metal wiring layer IC2B, and is connected to a column decoder RDb directly below the adjacent sub-array SBARY via the channel RB ( Transistor 50). In addition, the selection gate line SGD of the block BLKb is also connected to the column decoder RDb directly below the adjacent sub-array SBARY through the slot DY.

The same applies to the cell regions 60-2 and 60-4. That is, the block BLKa of the cell area 60-2 and the block BLKa of the cell area 60-4 are opposed to each other via the channel RA, and the word lines WL and the selection gate line SGS are connected to each other through the metal wiring layer IC2A. And is connected to a column decoder RDa directly below the cell area 60-2 via the channel RA. In addition, the selection gate line SGD of the block BLKa of the cell region 60-2 and the selection gate line SGD of the block BLKa of the cell region 60-4 are also connected to the column directly below the cell region 60-2 through the slot DY. Decoder RDa.

In the cell area 60-2, the character line WL and the selection gate line SGS of the block BLKb are connected to the block BLKb of the other sub-array SBARY adjacent to the Y-axis direction via the channel RB through the metal wiring layer. IC2B is connected to each other, and is connected to a column decoder RDb directly below the cell area 60-2 via a channel RB. In addition, the selection gate line SGD of the block BLKb is also connected to the column decoder RDb directly below the cell region 60-2 through the slot DY.

In addition, the character line and selection gate line SGS of the BLKb block 60-4 of the cell area are adjacent to the block BLKb of the other sub-array SBARY adjacent to the Y-axis direction via the channel RC through the metal wiring layer IC2C. They are connected to each other, and are connected to the column decoder RDb directly below the adjacent sub-array SBARY via the channel RC. In addition, the selection gate line SGD of the block BLKb is also connected to the column decoder RDb directly below the adjacent sub-array SBARY through the slot DY.

In channel C, the bit line BL is connected to the sense amplifier SA. In the example of FIG. 22, among the bit lines BL0 to BL3 passing through the cell regions 60-1 and 60-2, the bit lines BL0 and BL1 are connected to the cell line 60-1 directly below the cell region 60-1. Sense amplifier SA. On the other hand, the bit lines BL2 and BL3 are connected to the sense amplifier SA directly below the cell region 60-1 via the channel CB.

1.3 Effects of this embodiment

According to the configuration of this embodiment, the block size of the memory cell array can be reduced. This effect will be described below.

In NAND-type flash memory, the block size may also become a unit when erasing data, so the requirements for reducing the block size need to be considered according to the situation.

At this time, in order to make full use of the features of the three-dimensional multilayer memory of the type of the stacked character line WL, it is considered to reduce the number of string units without reducing the number of stacked layers of the character line WL. However, in this case, although the block size can be reduced, since the number of layers of the word line WL is not changed, the size of the wiring area of the word line becomes the same area as that before the block size is reduced. Therefore, simply reducing the number of string units may result in useless areas and reduce the degree of integration.

Regarding this point, according to the configuration of this embodiment, as described in FIGS. 9 to 13, the blocks are arranged such that the cell CEL is adjacent to the X axis direction and the word line wiring area WLHU is opposite to the Y axis direction. BLK. Therefore, according to this configuration, the generation of useless empty areas is suppressed, and the block BLK can be efficiently arranged on the one hand, and the block size can be reduced on the other.

The planar structure of the block BLK in this embodiment can be performed by forming a wiring layer functioning as a source line SL, a selection gate line SGS, a word line WL, and a selection gate line SGD on the interlayer insulating film 501. For example, it is formed by the following etching steps. which is:

(1) Etching steps for forming the above-mentioned wiring layer for the channels C and R

(2) The above-mentioned wiring layer etching step for forming the slit SLT1 between the cell units in the cell area

(3) The above-mentioned wiring layer etching step for forming a slit SLT2 between separated cells in each cell unit CU

(4) An etching step for forming the above-mentioned wiring layer in each cell unit CU to form a groove DY provided with a contact for selecting the gate line SGD

In addition, the order of performing the above-mentioned etching steps may be replaced as much as possible, and multiple etching steps may be performed simultaneously. The source lines SL may not be etched in (2) and (3).

As a result, the cell units CU adjacent to each other in the Y-axis direction are located in the wiring area at any position. WLHU is facing. The word lines WL of the two opposite connection areas are connected to the channel R in common and to the column decoder RD. The groove DY is formed so as to intersect the slits SLT1 and SLT2 and also intersect with the channel C.

In addition, in this specification, the "character line WL" in the plan layout and cross-sectional configuration diagrams, for example, in FIG. 8 and the like, means that it is formed in the interlayer insulating film 502 and is provided in a conductive layer that functions as a source line, And a conductive layer between the wiring D1, and the conductive layer is a conductive layer connected to the memory hole MH via a gate insulating film, a charge accumulation layer, and a block insulating film. This point is also the same for selecting the gate lines SGD and SGS. In other words, the word line WL means that a plurality of conductive layers are laminated along the Z-axis direction between a conductive layer functioning as a selective gate line SGS and a conductive layer functioning as a selective gate line SGD. , Such as a polycrystalline silicon layer.

2. Second Embodiment

Next, a semiconductor memory device according to a second embodiment will be described. This embodiment relates to the configuration of the column decoder RD provided at the end of the memory cell array 110 in the first embodiment described above. In the following, only differences from the first embodiment will be described.

2.1 About the layout of the area under the memory cell array

FIG. 23 shows the planar layout of the area under the memory cell array in this embodiment, in other words, the planar layout of the sense amplifier SA, the column decoder RD, and the operation circuit YLOG.

As shown in the figure, a column decoder RD ′ and a dummy region DMY are provided in a region adjacent to a region overlapping the memory cell array 110 in the Y-axis direction. The column decoder RD ′ is disposed in an area adjacent to the sense amplifier SA, and the dummy region DMY is disposed in an area adjacent to the column decoder RD.

FIG. 24 shows the area R2 of FIG. 23 in detail. As shown in the figure, the column decoder RD ′ includes a transistor 50 and has the same configuration as the column decoder RD provided in an area overlapping the memory cell array 110. Further, the word line WL and the selection gate line of the block BLKb provided above the sense amplifier SA adjacent to the column decoder RD ′ in the Y-axis direction are connected via the channel R. SGS.

On the other hand, in the dummy region DMY, a dummy element region AA and a gate electrode (semiconductor layer) GC are formed. These are provided in order to prevent the etching pattern from collapsing significantly during, for example, an etching step when forming the column decoder RD, RD 'or the sense amplifier SA, and are not intended to function as particularly effective semiconductor elements.

2.2 Effects of this embodiment

In the case of using the block layout described in the first embodiment, if the word line WL of the block BLKb located in the cell area on the sense amplifier SA is connected to the column decoder RD directly below the cell area, it must be The sense amplifier SA is penetrated by, for example, subcellular wiring. In this regard, according to this embodiment, the column decoder RD ′ for the block BLKb can be provided on the outside of the memory cell array, thereby suppressing the miscellaneous wiring of the cell.

In addition, the sense amplifier SA and the column decoder RD basically overlap the memory cell array 110 in the Z axis direction. When viewed in the XY plane, the sense amplifier SA and the column decoder RD are covered by the memory cell array 110 and cannot be seen Here. However, according to this embodiment, it can be seen that a column decoder RD ′ having a width substantially the same as the cell region 60 in the X-axis direction is formed with the same repetition period in the X-axis direction.

Furthermore, a dummy area DMY is preferably provided between adjacent column decoders RD '. The device region AA and the gate electrode GC in the dummy region DMY can also be set to electrically float. In addition, it can be fixed at a certain potential (for example, 0V), or can be electrically independent from the surrounding decoders RD, RD ', or the sense amplifier SA.

3. Third Embodiment

Next, a semiconductor memory device according to a third embodiment will be described. This embodiment is the one in the above-mentioned first and second embodiments that forms a laminated structure having a ring shape surrounding the cell area. In the following, only differences from the first and second embodiments will be described.

3.1 About the layout

FIG. 25 shows a planar layout of a cell area and a laminated structure disposed around it.

As shown in the figure, a ring-shaped laminated structure 700 is provided around the cell area so as to surround the cell area. The laminated structure 700 has, for example, a conductive laminated layer formed on the same layer as the wiring layer functioning as the source line SL, the selection gate line SGS, the word line WL, and the selection gate line SGD, like the cell CEL. The resulting structure. The distance between the adjacent cell unit CU and the multilayer structure 700 is, for example, the same as the width of the slit SLT1, the channel C, or the channel R. This region is buried by, for example, an insulating film, and the cell region is electrically separated from the multilayer structure 700.

The laminated structure 700 has a recess on a side wall facing a cell region. The recess is formed in a region adjacent to the groove DY in the X-axis direction as shown as a region R3 in FIG. 25. The depression is formed from the uppermost layer to the lowermost layer of the build-up layer structure 700, and the inside thereof is buried, for example, by an insulating film.

Fig. 26 is a cross-sectional view of Fig. 25, the upper view is a cross-sectional view taken along line 26A-26A, and the lower view is a cross-sectional view taken along line 26B-26B. In addition, the upper and lower figures of FIG. 26 are shown in the same position in the X direction.

As shown in the figure, in the cell CEL, a selection gate line SGS, word lines WL0 to WL18, and a selection gate line SGD are provided on the isolation edge layer 710 on the source line SL. The laminated structure 700 also has the same laminated structure as the cell. In other words, on the wiring layer IC10, the wiring layer IC11, IC12-0 to IC12-18, and IC13 are formed by insulating the edge layer 720. The wiring layer IC10 is formed at the same level (height) as the source line SL, and is formed, for example, from the same material at the same time. The wiring layer IC11 is formed at the same level (height) as the selection gate line SGS, and is formed at the same time using the same material, for example. The wiring layers IC12-0 to IC12-18 are formed at the same level (height) as the word lines WL0 to WL18, and are formed from the same material at the same time, for example. The wiring layer IC13 is formed at the same level (height) as the selection gate line SGD, and is formed at the same time using the same material, for example. It is also possible that the wiring layer IC13 is not formed. An insulating layer 730 is buried between the laminated structure 700 and the cell portion CEL (and the wiring portion WLHU and the connection portion CNCT).

The laminated structure 700 does not actually function as any semiconductor element. Therefore, the wiring IC11, IC12-0 to IC12-18, and IC13 included in the multilayer structure 700 are electrically separated from the source line SL, the selection gate line SGS, the word line WL, and the selection gate line SGD. And it can be fixed at a certain potential (for example, 0V), or it can float electrically.

In this configuration, as shown in the lower diagram of FIG. 26, a recess R3 is formed on a portion facing the groove DY, and an insulating layer 730 is buried in the recess. In other words, the width of the laminated structure 700 along the X-direction is smaller in the area facing the groove DY than in other areas (for example, the area facing the cell CEL).

3.2 Effects of this embodiment

As explained in the first embodiment, the wiring layer that functions as the source line SL, the selection gate line SGS, the character line WL, and the selection gate line SGD is formed when the channel C and the channel R are formed. Etching. At this time, since the areas to be etched are arranged at equal intervals in the memory cell array 110 and the etching widths are also equal, processing can be performed with high accuracy. However, the etching performed at the end of the memory cell array 110 is not so much for the purpose of forming the channels C and R as it is to remove all the wiring layers in the extra areas outside the memory cell array 110 For the purpose. Therefore, at the end of the memory cell array 110, the periodic pattern of the etching pattern may be disordered and the processing accuracy may be reduced.

In this regard, in this embodiment, since the same layered structure 700 as that of the cell area is provided around the memory cell array 110, etching in the same pattern as the channels C and R in the memory cell array 110 can be performed. Therefore, even at the end of the memory cell array 110, processing can be performed with high accuracy.

The etching step for forming the groove DY is usually performed after the etching step for forming the channel C and the channel R. Therefore, when the multilayer structure 700 is provided, a part of the multilayer structure 700 is also etched when the groove DY is formed. As a result, as shown in FIG. 25, a recess R3 is formed in a region facing the groove DY on the inner peripheral surface of the ring-shaped laminated structure.

4. Variations, etc.

As described above, if the semiconductor memory device according to the above embodiment is provided, it includes: a column decoder provided on the semiconductor substrate; and a memory cell array provided above the column decoder and having a first block. The first block is provided with a first region (CEL in FIG. 10) along the in-plane direction from the semiconductor substrate, that is, the first direction (Y direction in FIG. 10), and an in-plane direction that is different from the first direction. The first plane formed in 2 directions (X direction in FIG. 10) extends and has a first width along the second direction (X direction in FIG. 10); the second area (WLHU in FIG. 10) is along the first plane Extend, and have a second width greater than the first width along the second direction (X direction in FIG. 10), and adjacent to the first area (CEL in FIG. 10) in the first direction (Y direction in FIG. 10); And the third region (CNCT in FIG. 10), which extends along the first plane, has a third width smaller than the first width along the second direction (X direction in FIG. 10), and is located in the first region (FIG. 10) Middle CEL) and the second area (WLHU in FIG. 10), and connect the two. The first to third regions include a plurality of first word lines (WL in FIG. 15) laminated along a vertical direction of the semiconductor substrate, that is, a third direction (Z direction in FIG. 10). The first region further includes a first selection gate line (SGD in FIG. 15) provided on the first word line on the uppermost layer. The memory cell array further includes: a first insulating layer (730 in FIG. 26), which fills a first slot (DY in FIG. 10) between the first area (CEL in FIG. 10) and the second area (WLHU in FIG. 10). ), And in the second direction (X direction in FIG. 10) and the third area (CNCT in FIG. 10); the first contact plug (CP12 in FIGS. 10 and 26) is disposed on the first insulating layer (FIG. 10) 26 in 730), and is electrically connected to the column decoder; and the first wiring layer (IC1 in FIGS. 11 and 15), which connects the first selection gate line (SGD in FIGS. 11, 15) and the first contact plug Plug (CP12 in Figures 11 and 15).

The semiconductor memory device of the above embodiment includes a column decoder (120) provided on a semiconductor substrate having a first surface, and a memory cell array provided above the column decoder and provided in a matrix configuration. The group of cell areas (60) includes wiring (WL) connected to the column decoder, and overlaps the column decoder (120, RD) in a plane along the first surface. The column decoder (120) includes: a first transistor (RD ', 50 in Figs. 23-24), It is provided on the outer side of the group of cell regions in a plane along the first surface.

Furthermore, the semiconductor memory device of the above embodiment includes a memory cell array (110 in FIG. 25) including a source line (SL) provided above the first surface of the semiconductor substrate, and a source line provided above the source line. Word line (WL); wall (700 in FIG. 25), which surrounds the memory cell array (110) along a plane along the first surface, and includes a layer span from the source line and a layer of the word line arranged in and A plurality of conductive layers in a direction where the first surface of the semiconductor substrate intersects, and includes depressions (R3 in FIG. 25) extending from the upper surface and the lower surface from the inner surface to the outer periphery; The position of the surface is provided throughout the position of the lower surface, and is in contact with the inner peripheral surface of the wall in the depression.

The embodiment is not limited to those described above, and various changes can be made. For example, although the case where the number of stacked word lines WL is 19 is described as an example in the above embodiment, the number of word lines WL is not limited to this number, but is generally 2 ⁿ (n is a natural number). Moreover, in the above-mentioned embodiment, although the case where the memory holes MH are arranged in a misaligned shape as shown in FIG. 10 and the like is described as an example, it may be a case where a row is arranged in the Y-axis direction.

In addition, in FIG. 12 and FIG. 13 described in the first embodiment, a case where the contact plugs CP21 in the channel R are aligned on a straight line along the X-axis direction is described as an example. However, as shown in FIG. 27, the contact plugs CP21 may be arranged on the XY plane so as to be arranged in an oblique direction with respect to the X-axis direction and the Y-axis direction. In this case, as shown in FIG. 28, the arrangement directions of the contact plugs CP21 corresponding to the plurality of blocks BLK adjacent in the X direction may be opposite to each other. In other words, the line connecting the contact plug CP21 can also be arranged in a zigzag manner at the boundary of the block BLK.

In addition, the configuration of FIG. 25 described in the third embodiment may be a configuration shown in, for example, FIGS. 29 to 31. That is, the laminated structure 700 has two surfaces facing in the X direction facing the groove DY. At this time, the multilayer structure 700 can also be on one side, the wiring portion WLHU of the block BLKa (block located in the upper direction in the Y-axis direction) and the block BLKb (in the Y-axis direction) of the other The slot DY between the cells CEL of the block located in the lower direction) It also faces the slot DY between the wiring portion WLHU of block BLKa and the cell portion CEL of block BLKb.

Also, as shown in FIG. 30, the laminated structure 700 may also face the groove DY between the cell CEL of the block BLKa and the wiring portion WLHU of the block BLKb on one side, and also on the other side. The slot DY between the cell CEL of the block BLKa and the wiring part WLHU of the block BLKb.

Alternatively, as shown in FIG. 31, the multilayer structure 700 may also face the groove DY between the cell CEL of the block BLKa and the wiring portion WLHU of the block BLKb on one side, and face the block on the other side. The slot DY between the wiring part WLHU of BLKa and the cell part CEL of block BLKb.

In addition, each embodiment can be implemented individually or in combination. The second and third embodiments may be performed independently. When the third embodiment is combined with the second embodiment, the laminated structure 700 may overlap at least a part of the column decoder RD ′. In addition, the two may be completely overlapped. In this case, in the XY plane shown in FIG. 24, the column decoder RD ′ and the dummy area DMY are covered by the laminated structure 700 and cannot be seen.

Various configurations can be applied to the memory cell array 110. The structure of the memory cell array 110 is described in, for example, US Patent Application No. 12 / 407,403 filed on March 19, 2009, "Three-Dimensional Laminated Nonvolatile Semiconductor Memory". In addition, US Patent Application No. 12 / 406,524 filed on March 18, 2009, "Three-Dimensional Laminated Nonvolatile Semiconductor Memory," and US Patent Application No. 12 / 679,991 filed on March 25, 2010 are described. "Non-volatile semiconductor memory device and manufacturing method thereof", and US Patent Application No. 12 / 532,030 filed on March 23, 2009, "Semiconductor Memory and Manufacturing Method thereof". The entire contents of these applications are incorporated herein by reference.

Furthermore, the terms "connect" and "couple" used in this embodiment include both a case of a direct connection and a case of any constituent element interposed therebetween.

In the case where one memory cell MT holds two-bit data, its threshold voltage corresponds to any of four levels of data hold. When the four levels are sequentially set to the erasing level, the A level, the B level, and the C level, the selection word line is applied during the read operation of the A level. The voltage is, for example, between 0V and 0.55V. It is not limited to this, and may be any of 0.1V to 0.24V, 0.21V to 0.31V, 0.31V to 0.4V, 0.4V to 0.5V, and 0.5V to 0.55V. The voltage applied to the selected word line during reading at the B level is, for example, between 1.5V and 2.3V. It is not limited to this, and may be any of 1.65V to 1.8V, 1.8V to 1.95V, 1.95V to 2.1V, and 2.1V to 2.3V. The voltage applied to the selected word line during the C-level read operation is, for example, between 3.0V and 4.0V. It is not limited to this, and may be any of 3.0V to 3.2V, 3.2V to 3.4V, 3.4V to 3.5V, 3.5V to 3.6V, and 3.6V to 4.0V. The read operation time (tR) may be, for example, any of 25 μs to 38 μs, 38 μs to 70 μs, and 70 μs to 80 μs.

The write action includes programming and programming verification. In the writing operation, the voltage initially applied to the word line selected during programming is, for example, between 13.7V and 14.3V. It is not limited to this, and may be, for example, any of 13.7V to 14.0V, 14.0V to 14.6V, and the selected character line when writing an odd-numbered character line The voltage initially applied is different from the voltage initially applied to the selected word lines when writing to the even-numbered word lines. When the programming operation is an ISPP method (Incremental Step Pulse Program), the voltage to be boosted is, for example, about 0.5V. The voltage applied to the non-selected word line may be, for example, between 6.0V and 7.3V. It is not limited to this, for example, it may be between 7.3V and 8.4V, and may be 6.0V or less. It is also possible to set the applied bus voltages differently depending on whether the non-selected character lines are odd-numbered character lines or even-numbered character lines. The write operation time (tProg) can be, for example, between 1700 μs to 1800 μs, 1800 μs to 1900 μs, and 1900 μs to 2000 μs.

In the erasing operation, the voltage initially applied to the wafer disposed on the upper portion of the semiconductor substrate and the memory cells disposed thereon is, for example, 12V to 13.6V. It is not limited to this, and may be any of 13.6V to 14.8V, 14.8V to 19.0V, 19.0V to 19.8V, or 19.8V to 21V. The erasing time (tErase) can be, for example, between 3000 μs to 4000 μs, 4000 μs to 5000 μs, and 4000 μs to 9000 μs.

The memory cell may have a structure such as the following. The memory cell has a charge accumulation film arranged through a tunnel insulation film having a film thickness of 4 nm to 10 nm. The charge accumulation film can be a laminated layer of a silicon nitride (SiN) film having a thickness of 2 to 3 nm, or an insulating film such as a silicon oxynitride (SiON) film, and a poly-Si having a thickness of 3 to 8 nm. structure. A metal such as ruthenium (Ru) may be added to the polycrystalline silicon film. The memory cell line has an insulating film on top of the charge accumulation film. This insulating film has, for example, a high-K (high dielectric constant) film with a film thickness of 3 nm to 10 nm, and a silicon oxide having a film thickness of 4 nm to 10 nm sandwiched between the high-K film with a film thickness of 3 nm to 10 nm. (SiO) film. Examples of the material of the High-K (high dielectric constant) film include hafnium oxide (HfO). In addition, the thickness of the silicon oxide film can be made thicker than that of a High-K (high dielectric constant) film. A control electrode having a film thickness of 30 nm to 70 nm is provided on the insulating film through a film for adjusting a work function having a film thickness of 3 nm to 10 nm. Here, the work function adjustment film is, for example, a metal oxide film such as tantalum oxide (TaO), or a metal nitride film such as tantalum nitride (TaN). As the control electrode, tungsten (W) or the like can be used. An air gap can be configured between the memory cells.

Although the foregoing has been described in terms of specific embodiments, these specific embodiments are merely examples and are not intended to limit the scope of the present invention. In fact, the novel methods and systems described above can be implemented in various other forms, and the forms and details of the methods and systems described can be omitted, substituted, and changed without departing from the spirit and scope of the present invention. These forms or modifications are considered to be within the scope of the present invention, and are included in the scope of the following patent applications and their equivalents.

Claims (20)

A semiconductor memory device includes: a column decoder disposed on a semiconductor substrate; and a memory cell array disposed above the column decoder and including a first block; wherein the first block includes: The first region extends along a first plane formed by the first direction of the in-plane direction of the semiconductor substrate and a second direction different from the first direction of the in-plane direction, and along the second direction. Having a first width; a second region extending along the first plane, having a second width greater than the first width along the second direction, and adjacent to the first region in the first direction; and The third region extends along the first plane, has a third width smaller than the first width along the second direction, and is located between the first region and the second region to connect the two; The first to third regions include a plurality of first word lines laminated along the vertical direction of the semiconductor substrate, that is, the third direction, and the first region further includes a first selection provided on the first word line on the uppermost layer. Gate line; and the above memory cell The row further includes: a first insulating layer, which fills a first groove between the first region and the second region, and is in contact with the third region in the second direction; and a first contact plug, which is provided The first insulation layer is electrically connected to the column decoder, and the first wiring layer is connected to the first selection gate line and the first contact plug. For example, the device of claim 1, wherein the memory cell array further includes a second block; and the second block includes a fourth region that extends along the first plane and has a fourth region along the second direction. A fifth region extending along the first plane, having a fifth width larger than the fourth width along the second direction, and adjacent to the fourth region in the first direction; and a sixth region , Which extends along the first plane, has a sixth width smaller than the fourth width along the second direction, and is located between the fourth region and the fifth region to connect the two; the fourth to sixth The region includes a plurality of second word lines stacked along the third direction, and the fourth region further includes a second selection gate line disposed on the second word line of the uppermost layer; the memory cell array further includes: The second insulating layer fills the second groove between the fourth region and the fifth region, and is in contact with the sixth region in the second direction. The second contact plug is disposed in the second region. An insulating layer and electrically connected to the column decoder; and a second wiring layer, which is connected The second selection gate line and the second contact plug; and the first region and the fourth region are filled with a third insulating layer that fills a third slot between the first region and the fourth region, and The second direction is adjacent; the second region and the fifth region are opposed to each other in the first direction with the first region and the fourth region interposed therebetween; the first groove extends to the second region and the fourth region. Between the regions, the second region and the fourth region are separated by the first insulating layer; the second groove extends between the first region and the fifth region, and the first region is separated from the first region. The five regions are separated by the second insulating layer. For example, the device of claim 2, wherein the memory cell array further includes a third block; and the third block includes a seventh region that extends along the first plane and has a seventh region along the second direction. An eighth region extending along the first plane, having an eighth width greater than the seventh width along the second direction, and adjacent to the seventh region in the first direction; and a ninth region , Which extends along the first plane, has a ninth width smaller than the seventh width along the second direction, and is located between the seventh region and the eighth region to connect the two; the seventh to ninth The region includes a plurality of third character lines stacked along the third direction, and the seventh region further includes a third selection gate line disposed on the third character line on the uppermost layer; the memory cell array further includes: A fourth insulating layer, which fills the fourth groove between the seventh region and the eighth region, and is in contact with the ninth region in the second direction; and a third contact plug, which is disposed in the fourth An insulation layer, and is electrically connected to the column decoder; and a third wiring layer, which is connected The selected gate line is in contact with the third contact plug; and the second region and the eighth region are filled with a fifth insulating layer of the fifth slot between the second region and the eighth region, and are disposed in the first region. Two directions are adjacent; the first groove and the fourth groove are located on the same line along the second direction. The device according to claim 3, further comprising: a plurality of bit lines, which are arranged above the first region, the fourth region, and the seventh region in the third direction, and are arranged along the above A strip shape in the second direction; and a fourth contact plug, which is disposed in the fifth insulation layer that fills the fifth slot and is connected to any one of the plurality of bit lines; and the bit line And is electrically connected to the sense amplifier via the fourth contact plug. For example, the device of claim 2, wherein the memory cell array further includes a third block; and the third block includes a seventh region that extends along the first plane and has a seventh width along the second direction. An eighth region extending along the first plane, having an eighth width greater than the seventh width in the second direction, and adjacent to the seventh region in the first direction; and a ninth region, It extends along the first plane and has a ninth width smaller than the seventh width along the second direction, and is located between the seventh region and the eighth region to connect the two; the seventh to ninth The region includes a plurality of third character lines stacked along the third direction, and the seventh region further includes a third selection gate line disposed on the third character line on the uppermost layer; the memory cell array further includes: A fourth insulating layer, which fills the fourth groove between the seventh region and the eighth region, and is in contact with the ninth region in the second direction; and a third contact plug, which is disposed in the fourth An insulation layer, and is electrically connected to the column decoder; and a third wiring layer, which is connected The selected gate line is in contact with the third contact plug; and the second region and the eighth region are filled with a fifth insulating layer of the fifth slot between the second region and the eighth region, and are disposed in the first region. 1 direction is adjacent. The device of claim 5, wherein the memory cell array further includes: a fourth contact plug, which is disposed in the fifth insulating layer; and a fifth wiring layer, which is connected to the fourth contact plug, and has a length direction Along the first direction; the first block is in the second region, and further includes a fifth contact plug disposed on the first character line; the third block is in the eighth region, and further includes A sixth contact plug provided on the third character line; and the fifth wiring layer is led out to the second area and the eighth area, and is connected to the fifth contact plug and the sixth contact plug; The first word line and the third word line are electrically connected to the column decoder through the fifth wiring layer and the fourth contact plug. The device of claim 6, wherein the second region has a plurality of stepped surfaces along the first direction, and the stepped surface has a shape that decreases in height as it approaches the fifth insulating layer; any one of the stepped surfaces is exposed. The first character line; the eighth region has a plurality of stepped surfaces along the first direction, and the stepped surface has a shape that decreases in height as it approaches the fifth insulating layer; and is exposed on the stepped surface Take any of the above-mentioned 3rd character lines. The device according to claim 1, further comprising: a second wiring layer provided in a region between the semiconductor substrate and the memory cell array; and a first word line provided at a lowermost layer among the first word lines. On the source line; the first groove is formed to a depth from the upper surface of the first word line of the uppermost layer to at least the bottom surface of the source line; and the first contact plug is formed from the first wiring The layer reaches the depth of the second wiring layer. For example, the device of claim 2, wherein the first word line of the lowest layer among the first word lines is arranged on the first source line; the second word line of the lowest layer among the second word lines The first source line and the second source line are connected in common to an area directly below the third slot. For example, the device of claim 3, wherein the first word line of the lowest level among the first word lines is set on the first source line; the third word line of the lowest level among the third word lines is set on the first source line. 3 source lines; and the first source line and the third source line are connected in common to the area directly below the fifth slot. The device according to claim 4, further comprising: a fourth wiring layer provided in a region between the semiconductor substrate and the memory cell array; and a first word line provided at a lowermost layer among the first word lines. On the first source line; and the third word line of the lowermost layer among the third word lines is provided on the third source line; the fifth slot is formed from the first word line and the first layer of the uppermost layer The upper surface of the 3 word line reaches at least the depth of the first source line and the bottom surface of the third source line; and the fourth contact plug is formed from the bit line to the fourth wiring layer. depth. The device according to claim 6, further comprising: a sixth wiring layer provided in a region between the semiconductor substrate and the memory cell array; and a first word line provided at a lowermost layer among the first word lines. On the first source line; and the third word line of the lowermost layer among the third word lines is provided on the third source line; the fifth slot is formed from the first word line and the first layer of the uppermost layer The top surface of the 3 word line reaches at least the depth of the bottom surface of the first source line and the third source line; and the fourth contact plug is formed from the fifth wiring layer to the sixth wiring layer. Depth. A semiconductor memory device includes: a column decoder provided on a semiconductor substrate having a first surface; and a memory cell array provided above the column decoder and provided with a group of cell regions arranged in a matrix , Including wiring connected to the column decoder, and overlapping with the column decoder on a plane along the first surface; and the column decoder includes: a first transistor, It is arranged on the plane outside the outer periphery of the group of the cell regions. The device according to claim 13, wherein the column decoder further includes: a second transistor that overlaps the memory cell array on a plane along the first surface; the semiconductor memory device further includes: a sense amplifier, It is disposed on the semiconductor substrate and overlaps the memory cell array on a plane along the first surface. The device according to claim 13, further comprising: a first connection portion provided between one cell region of the group of the cell regions and the first transistor, and a first circuit connecting the wiring and the column decoder. 1Contact plug. For example, the device of claim 15, wherein the group of the above-mentioned cell regions includes adjacent first and second cell regions; the first transistor is located outside the first cell region on a plane along the first surface. The outer side; and the semiconductor memory device further includes a dummy region provided on an outer side of the second cell region on a plane along the first surface, and including an active region and a conductor. The device according to claim 16, wherein the first connection portion is provided between the first cell region and the first transistor; the wiring in the first cell region is electrically connected to the first via the first connection portion. A transistor; and the semiconductor memory device further comprising: a second connection portion provided between the second cell region and the dummy region, and provided to connect the wiring of the second cell region to the second cell. The second contact plug of the above row of decoders directly below the area. A semiconductor memory device includes a memory cell array including a source line disposed above a first surface of a semiconductor substrate, and a character line disposed above the source line; and a wall along the edge The plane of the first surface surrounds the memory cell array, and includes a plurality of conductive layers arranged in a direction intersecting the first surface of the semiconductor substrate from the level of the source line and the level of the word line, and A depression extending from the upper surface to the lower surface and extending from the inner peripheral surface toward the outer periphery; and an insulating layer provided from the position of the upper surface of the wall to the position of the lower surface, and in the depression and the wall The above-mentioned inner peripheral faces are in contact. The device of claim 18, wherein the memory cell array includes: a selection gate line disposed above the word line; a first area and a second area, which are adjacent to each other along the first direction, and include the above The character line and the selection gate line; and a third area for connecting the selection gate line to the wiring in the first area; the depression is formed on the surface of the inner periphery of the wall, and is arranged to face the third area Area. The device of claim 19, wherein the memory cell array includes a plurality of wirings laminated between the source line and the selection gate line in a direction intersecting the first surface of the semiconductor substrate; and the above of the wall The plurality of conductive layers are located on the same layer as the plurality of wirings.