TWI641132B - Semiconductor device and method of manufacturing same - Google Patents

Abstract

The semiconductor device includes a semiconductor substrate having a first conductivity type, and a deep well region is provided in the semiconductor substrate and has a second conductivity type opposite to the first conductivity type. The first well region is provided in the semiconductor substrate and has a second conductivity type, wherein The first well region is located above the deep well region, and a part of the first well region is adjacent to the deep well region. The first doped region, the second doped region, and the third doped region are disposed in the first well region. The doped region has a second conductivity type, and the second doped region has a first conductivity type, and the top layer is disposed in the first well region and has the first conductivity type, wherein the top layer is located between the first and two doped regions, There is a distance between the top layer and the second doped region, and the foregoing distance has a positive linear relationship with the pinch-off voltage of the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device containing a junction field effect transistor and a manufacturing method thereof.

In the semiconductor industry, there are two main types of field effect transistors (FETs), namely insulated gate field effect transistors (IGFETs), commonly referred to as metal oxide semiconductor field effect transistors. (metal oxide semiconductor field effect transistor (MOSFET)) and junction field effect transistor (JFET). The structure configuration of the metal oxide semiconductor field effect transistor and the junction field effect transistor are basically different. For example, the gate of a metal oxide semiconductor field effect transistor includes an insulating layer, that is, a gate oxide layer, between the gate and other electrodes of the transistor. Therefore, the channel current in the metal oxide semiconductor field effect transistor is controlled by the electric field passing through the channel to enhance and deplete the channel region as required. The gate of the junction field-effect transistor and the other electrodes of the transistor form a P-N junction. The junction field-effect transistor can be reverse-biased by applying a predetermined gate voltage. Therefore, by changing the size of the empty area in the channel, the gate P-N interface of the field effect transistor can be used to control the channel current.

Generally, the junction field effect transistor can be used as a voltage controlled resistor or an electronically controlled switch. The P-type junction field-effect transistor contains a large amount of positive carriers or holes in the doped semiconductor material, while the N-type junction field-effect transistor contains a large amount of negative carriers or holes in the doped semiconductor material. electronic. At each end of the junction field effect transistor, a source and a drain are formed by an ohmic contact, and a current flows through a channel between the source and the drain. In addition, by applying a reverse bias to the gate, the current can be blocked or disconnected, also known as "pinch-off."

Although the existing field-effect transistor and its manufacturing method of semiconductor devices have gradually met their intended uses, they have not completely met the requirements in all aspects. Therefore, there are still some problems to be overcome regarding the junction field effect transistor and manufacturing technology of the semiconductor device.

The invention provides an embodiment of a semiconductor device and an embodiment of a manufacturing method thereof, particularly an embodiment of a junction field effect transistor. Usually, the doping concentration in the well area of the junction field effect transistor is adjusted in the manufacturing process, so that the junction field effect transistor generates a specific pinning voltage to meet the requirements of different product applications. However, the doping concentration in the well area is not easy to accurately control, so that the pinch voltage of the produced junction field effect transistor is likely to cause a non-negligible error between the target pinch voltage and the expected pinch voltage target value.

In order to more accurately regulate the clamping voltage of the output field effect transistor, the embodiment of the present invention sets a top layer in the well area of the interface field effect transistor, and the conductivity type and electrical connection of the top layer are electrically connected to the gate electrode. The conductive type of the doped region is the same, and there is a distance between the two. This distance has a positive linear relationship with the pinning voltage of the junction field effect transistor. The pinch-off voltage of the surface-effect transistor is higher. Therefore, according to the embodiment of the present invention, the pinch-off voltage of the junction-type field-effect transistor can be accurately controlled by adjusting the distance.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first conductivity type, and a deep well region is disposed in the semiconductor substrate and has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a first well region disposed in the semiconductor substrate and having a second conductivity type, wherein the first well region is located above the deep well region, and a portion of the first well region is adjacent to the deep well region. The semiconductor device further includes a first doped region, a second doped region, and a third doped region disposed in the first well region, wherein the first doped region and the third doped region have a second conductivity type, and the second The doped region has a first conductivity type. In addition, the semiconductor device includes a top layer disposed in the first well region and having a first conductivity type, wherein the top layer is located between the first doped region and the second doped region, and the top layer and the second doped region are separated by a distance. , Wherein the aforementioned distance has a positive linear relationship with the pinch-off voltage of the semiconductor device.

According to some embodiments, a method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a first conductivity type, and forming a deep well region within the semiconductor substrate, the deep well region having a second conductivity type opposite to the first conductivity type. The method also includes forming a first well region within the semiconductor substrate, the first well region having a second conductivity type, wherein the first well region is formed above the deep well region and a portion of the first well region is adjacent to the deep well region, wherein the depth of the deep well region is It is larger than the depth of the first well region, and the doping concentration of the deep well region is smaller than that of the first well region. The method further includes forming a first doped region, a second doped region, and a third doped region in the first well region, wherein the first and third doped regions have a second conductivity type, and the second doped region The impurity region has a first conductivity type. In addition, the method includes forming in the first well area A top layer having a first conductivity type, wherein the top layer is located between the first doped region and the second doped region, and there is a distance between the top layer and the second doped region, wherein the foregoing distance is sandwiched with the semiconductor device The voltage has a positive linear relationship, and a source electrode, a drain electrode, and a first gate electrode are formed on a semiconductor substrate, wherein the aforementioned distance is adjusted so that the clamping voltage of the semiconductor device reaches a predetermined target value.

The semiconductor device of the present invention can be applied to various types of semiconductor devices. In order to make the features and advantages of the present invention more obvious and easy to understand, the following specifically lists the embodiments applied to the junction field effect transistor and cooperates with the attached drawings As detailed below.

100, 200, 300‧‧‧ semiconductor devices

101‧‧‧ semiconductor substrate

103‧‧‧shielded oxide

105, 113, 125‧‧‧ patterned photoresist

107‧‧‧Shenjing District

109, 121‧‧‧ Pad oxide layer

111, 123‧‧‧ nitride layer

115‧‧‧The first well area

117‧‧‧field oxide layer

119‧‧‧Second Well District

124a, 124b, 124c, 126a, 126b, 126c, 126d

127‧‧‧top floor

127a‧‧‧Part I

127b‧‧‧Part II

127c‧‧‧Part III

127d‧‧‧Part Four

129a‧‧‧first isolation structure

129b‧‧‧Second isolation structure

129c‧‧‧Third isolation structure

131a‧‧‧First electrode

131b‧‧‧Second electrode

132, 232‧‧‧ Spacer

133a‧‧‧First doped region

133b‧‧‧Second doped region

133c‧‧‧ Third doped region

133d‧‧‧ Fourth doped region

135‧‧‧Interlayer dielectric layer

137a, 137b, 137c, 137d, 137e, 137f, 237a, 237b, 237c, 237d, 237e

139a‧‧‧Drain electrode

139b‧‧‧electrode

139c‧‧‧First gate electrode

139d, 239c‧‧‧ source electrode

139e‧‧‧Second gate electrode

229a, 229b‧‧‧Isolation structure

231‧‧‧third gate electrode

233b‧‧‧ doped region

239b, 239d‧‧‧ electrode

D1‧‧‧First Depth

D2‧‧‧Second Depth

d‧‧‧distance

Through the following detailed description and the accompanying drawings, we can better understand the viewpoints of the embodiments of the present invention. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, the size of the different components may be increased or decreased for the sake of clarity.

1A-1I are schematic cross-sectional views showing various stages of forming a semiconductor device according to some embodiments of the present invention; FIG. 2 is a top view showing a semiconductor device according to some embodiments of the present invention, wherein FIG. FIG. 2 is a schematic cross-sectional view of a semiconductor device along line AA ′ in FIG. 2; FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention; and FIG. 4 is another embodiment according to the present invention. A top view of a semiconductor device is shown, in which FIG. 1I is a semiconductor device along line AA ′ in FIG. 4. FIG. 3 is a schematic cross-sectional view of a semiconductor device along line BB ′ in FIG. 4; FIG. 5 is a schematic view showing a top layer and a second dopant in the semiconductor device according to some embodiments of the present invention. A graph of the relationship between the distance between the miscellaneous regions and the pinch-off voltage; and FIG. 6 is a list of element characteristic data showing some examples of the semiconductor device according to some embodiments of the present invention.

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment where the first and second elements are in direct contact, or it may include an additional element formed between the first and second elements. So that they are not in direct contact with the embodiment. In addition, embodiments of the present invention may repeat reference numbers and / or letters in different examples. This repetition is for brevity and clarity, and is not intended to represent the relationship between the different embodiments and / or forms discussed.

Some variations of the embodiments are described below. In different illustrated and illustrated embodiments, similar reference numbers are used to identify similar elements. It can be understood that additional operations may be provided before, during, and after the method, and some of the operations described may be replaced or deleted for other embodiments of the method.

1A-1I are schematic cross-sectional views showing various stages of forming the semiconductor device 100 of FIG. 1I according to some embodiments of the present invention.

According to some embodiments, as shown in FIG. 1A, a semiconductor-based 底 101。 The bottom 101. The semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may include other element semiconductor materials such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 may include an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate 101 may be a lightly doped P-type or N-type substrate. In this embodiment, the semiconductor substrate 101 is a P-type, and the semiconductor device 100 of FIG. 11 is an N-type junction field effect transistor.

Next, referring to FIG. 1A, a screen oxide 103 and a patterned photoresist 105 are sequentially formed on the semiconductor substrate 101. The patterned photoresist 105 exposes a part of the masked oxide layer 103, and the patterned photoresist 105 is used. An N-type or P-type dopant is ion-implanted in the semiconductor substrate 101 to mask the semiconductor substrate 101 to form a deep well region 107 in the semiconductor substrate 101 not covered with the patterned photoresist 105, and then the patterned photoresist 105 is removed. In some embodiments, the shielding oxide layer 103 is made of silicon oxide, and can be formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating. Spin coating or a combination of the foregoing. In this embodiment, the deep well region 107 is N-type and has N-type dopants (such as phosphorus (P) or arsenic (As)) inside.

According to some embodiments, as shown in FIG. 1B, a pad oxide layer 109, a nitride layer 111, and a patterned photoresist 113 are sequentially formed on the semiconductor substrate 101. It is worth noting that the nitride layer 111 and the patterned photoresist 113 constitute a patterned mask. The patterned mask exposes a portion of the pad oxide layer 109. In some embodiments, the pad oxide layer 109 is made of silicon oxide, the nitride layer 111 is made of silicon nitride or silicon oxynitride, and the pad oxide layer 109 and the nitride layer 111 can be formed by thermal oxidation and chemical vapor deposition. (CVD), atomic layer deposition (ALD), spin coating, or a combination thereof.

Referring again to FIG. 1B, an N-type or P-type dopant is ion-implanted into the semiconductor substrate 101 by using a patterned mask composed of the patterned photoresist 113 and the nitride layer 111 to cover the semiconductor of the patterned mask. A first well region 115 is formed in the substrate 101, and then the patterned photoresist 113 is removed. In this embodiment, both the first well region 115 and the deep well region 107 are N-type.

It is worth noting that the distance between the bottom surface of the deep well region 107 and the top surface of the semiconductor substrate 101 is a first depth D1, and the distance between the bottom surface of the first well region 115 and the top surface of the semiconductor substrate 101 is a second depth D2 . In some embodiments, the first depth D1 is in a range of about 9 microns to about 10 microns, and the second depth D2 is about 4 microns. In addition, the doping concentration of the first well region 115 is greater than the doping concentration of the deep well region 107, and the length of the first well region 115 is greater than the length of the deep well region 107.

Subsequently, as shown in FIG. 1C, a field oxide layer 117 is formed on the semiconductor substrate 101 exposed by the nitride layer 111, that is, on the first well region 115, and a part of the field oxide layer 117 is embedded in the semiconductor substrate 101 and Located in the first well area 115. In some embodiments, the field oxide layer 117 is made of silicon oxide and is a local oxidation of silicon (LOCOS) isolation structure formed by a thermal oxidation method. In other embodiments, the field oxide layer 117 may be a shallow trench isolation formed by an etching and deposition process. isolation (STI) structure. After the field oxide layer 117 is formed, the nitride layer 111 shown in FIG. 1B is removed. In addition, in some embodiments, the pad oxide layer 109 on the first well region 115 is combined with the field oxide layer 117 during the process of forming the field oxide layer 117, and the pad oxide layer 109 that does not cover the first well region 115 has a thickness due to its thickness. The difference from the field oxide layer 117 is too great, and is not shown in FIG. 1C.

Referring again to FIG. 1C, a field oxide layer 117 is used to ion implant N-type or P-type dopants in the semiconductor substrate 101 to form a second well region 119 adjacent to the first well region 115. In this embodiment, the second well region 119 is of a P-type and has a P-type dopant (for example, boron (B)) inside. After the second well region 119 is formed, the field oxide layer 117 and the pad oxide layer 109 (not shown) above the second well region 119 are removed. In some embodiments, because a part of the field oxide layer 117 is embedded in the semiconductor substrate 101, the top surface of the first well region 115 of the semiconductor substrate 101 may have a depth of about 200 nm to about 300 nm after the field oxide layer 117 is removed. Slight depression (not shown).

According to some embodiments, as shown in FIG. 1D, a pad oxide layer 121 and a patterned nitride layer 123 are sequentially formed on the semiconductor substrate 101. Specifically, the patterned nitride layer 123 has a plurality of openings 124a, 124b, and 124c that respectively expose the underlying pad oxide layer 121. These openings 124a, 124b, and 124c define the positions of the isolation regions in the subsequent semiconductor device 100. In addition, the materials and processes of the pad oxide layer 121 and the nitride layer 123 may be the same or similar to the pad oxide layer 109 and the nitride layer 111, respectively, and will not be repeated here.

Continuing the foregoing, as shown in FIG. 1E, a patterned photoresist 125 is formed on the pad oxide layer 121 and the nitride layer 123. In some embodiments, the patterned photoresist 125 fills the openings 124b and 124c of the nitride layer 123, but the patterned photoresist 125 At the same time, a plurality of openings 126a, 126b, 126c, and 126d are located in the opening 124a of the nitride layer 123, that is, the patterned photoresist 125 does not fill the opening 124a of the nitride layer 123. The openings 126a, 126b, 126c, and 126d of the patterned photoresist 125 define positions of the top layer 127 formed subsequently in the first well region 115.

Referring again to FIG. 1E, a patterned photoresist 125 is used to ion implant N-type or P-type dopants in the first well region 115 to form a top layer 127. In this embodiment, the top layer 127 is a P-type, and is composed of a first portion 127a, a second portion 127b, a third portion 127c, and a fourth portion 127d. Specifically, the length of the first portion 127a, the second portion 127b, and the third portion 127c of the top layer 127 is shorter than that of the fourth portion 127d, and the distance between the first portion 127a, the second portion 127b, the third portion 127c, and the fourth portion 127d is smaller. The distances are all the same. In addition, the deep well region 107 extends directly below the fourth portion 127d of the top layer 127.

In other embodiments, the top layer 127 may be a continuous layer of structure or consist of at least two discrete sections. In some embodiments, the top layer 127 is composed of at least two discontinuous portions, and the length of these discontinuous portions gradually increases from the first well region 115 toward the second well region 119. In yet another embodiment, the top layer 127 is a continuous layer structure, and the thickness of the top layer 127 in a direction perpendicular to the top surface of the semiconductor substrate 101 in a cross-sectional view is from the first portion 127a to the fourth portion 127d. Gradually. In addition, the doping dose of the top layer 127 is about 1 × 10 ¹³ ions / cm 2. After the top layer 127 is formed, the patterned photoresist 125 is removed.

According to some embodiments, as shown in FIG. 1F, the first isolation structure 129a, the second isolation structure 129b, and the third isolation structure 129c are formed on the semiconductor substrate 101 by using the nitride layer 123 as a mask. See Figures 1E and 1F, first An isolation structure 129a is formed in the opening 124a of the nitride layer 123, a second isolation structure 129b is formed in the opening 124b of the nitride layer 123, and a third isolation structure 129c is formed in the opening 124c of the nitride layer 123. It is worth noting that the first isolation structure 129a completely covers the top layer 127, and the third isolation structure 129c is located above the interface between the first well region 115 and the second well region 119. In addition, the materials and processes of the first isolation structure 129a, the second isolation structure 129b, and the third isolation structure 129c may be the same or similar to those of the field oxide layer 117, and will not be repeated here.

Next, as shown in FIG. 1G, a first electrode 131a and a second electrode 131b may be selectively formed on the first isolation structure 129a and the second isolation structure 129b, respectively. In some embodiments, the first electrode 131a and the second electrode 131b may be made of polycrystalline silicon or other suitable metal conductive materials, and may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or low pressure chemical vapor deposition. (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other suitable processes. It is worth noting that the first electrode 131a and the second electrode 131b can reduce the peak value of the electric field of the semiconductor device, thereby improving the reliability of the semiconductor device.

According to some embodiments, as shown in FIG. 1H, a first doped region 133a, a second doped region 133b, and a third doped region 133c are formed in the first well region 115, and a second well region 119 is formed The fourth doped region 133d. In this embodiment, the first and third doped regions 133a and 133c are N-type, and the second and fourth doped regions 133b and 133d are P-type. In addition, the dopant concentrations of the first, second, third, and fourth doped regions 133a, 133b, 133c, and 133d are approximately the same, and are higher than those of the first well region 115 and the second well region 119.

It is worth noting that the second doped region 133b is separated from the fourth portion 127d of the top layer 127 by a distance d, and the doping concentration of the second doped region 133b is higher than that of the top layer 127. In some embodiments, the doping dose of the second doped region 133b is about 1 × 10 ¹⁵ ions / cm 2. In addition, in the process of forming the first, second, third, and fourth doped regions 133a, 133b, 133c, and 133d, spacers 132 may be formed on both sides of the first electrode 131a. In some embodiments, the spacer 132 may be formed of silicon oxide, silicon nitride, or silicon oxynitride, and may be formed by a deposition and etching process.

Continuing the foregoing, as shown in FIG. 11, an inter-layer dielectric (ILD) layer 135 is formed on the semiconductor substrate 101. In some embodiments, the interlayer dielectric layer 135 is made of silicon oxide, silicon nitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable dielectrics. Formed by electrical materials. In addition, the interlayer dielectric layer 135 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

After the interlayer dielectric layer 135 is formed, a drain electrode 139a, an electrode 139b, a first gate electrode 139c, a source electrode 139d (also referred to as a first source electrode), and a second gate electrode are formed on the interlayer dielectric layer 135. Electrode 139e. In addition, vias 137a, 137b, 137c, 137d, 137e, and 137f are formed in the interlayer dielectric layer 135.

In some embodiments, the drain electrode 139a is electrically connected to the first doped region 133a through the vias 137a and 137b, the electrode 139b is electrically connected to the first electrode 131a through the via 137c, and the first gate electrode 139c is through the via. 137d is electrically connected to the second doped region 133b, the source electrode 139d is electrically connected to the third doped region 133c through the via 137e, and the second gate electrode 139e is electrically connected through the via The hole 137f is electrically connected to the fourth doped region 133d. In some embodiments, the source electrode 139d, the drain electrode 139a, and the via holes 137a, 137b, 137c, 137d, 137e, and 137f may include a metal. In addition, the first gate electrode 139c and the second gate electrode 139e are electrically connected via a conductive line (not shown) above the interlayer dielectric layer 135.

FIG. 2 is a top view showing the semiconductor device 100 according to some embodiments of the present invention. FIG. 1I is a schematic cross-sectional view of the semiconductor device 100 along line A-A 'in FIG. 2. In this embodiment, the semiconductor device 100 is a junction field effect transistor. It should be noted that FIG. 2 does not show the material layers above the first isolation structure 129a, the second isolation structure 129b, the third isolation structure 129c, and the interlayer dielectric layer 135.

FIG. 3 is a schematic cross-sectional view showing a semiconductor device 200 according to other embodiments of the present invention. FIG. 4 is a top view of a semiconductor device 300 according to other embodiments of the present invention. The semiconductor device 300 includes a semiconductor device 100 and a semiconductor device 200. In addition, FIG. 1I is also a schematic cross-sectional view of the semiconductor device 100 along the line AA ′ in FIG. 4, and FIG. 3 is a cross-sectional view of the semiconductor device 200 along the line BB ′ in FIG. 4. schematic diagram. It should be noted that FIG. 4 does not show the material layers of the isolation structures 129a, 129b, 129c and the interlayer dielectric layer 135 in FIG. 1I, and the isolation structures 229a, 229b, and interlayer dielectric in FIG. 3 Material layer above layer 135.

In this embodiment, the semiconductor device 300 includes semiconductor devices 100 and 200. The semiconductor device 100 is a junction field effect transistor, and the semiconductor device 200 is a laterally diffused metal oxide semiconductor (LDMOS). ), And the semiconductor device 300 can withstand ultra high voltage (about 700 volts to about 800 volts).

Referring to FIGS. 3 and 4, the dotted range of FIG. 4 corresponds to the positions where the first well region 115 and the second well region 119 of the semiconductor device 200 and the semiconductor device 100 are located. It is worth noting that the semiconductor device 200 and the semiconductor device 100 The semiconductor substrate 101, the deep well region 107, the first well region 115, the second well region 119, the top layer 127, the interlayer dielectric layer 135, and the drain electrode 139a are shared. In some embodiments, the semiconductor device 200 includes an N-type first doped region 133 a in the first well region 115, and an N-type doped region 233 b and a P-type fourth doped region in the second well region 119. 133d. Furthermore, the semiconductor device 200 includes an isolation structure 229 a on the first well region 115, an isolation structure 229 b on the second well region 119, and a third gate electrode 231 on the semiconductor substrate 101. The third gate electrode 231 may be made of polycrystalline silicon or other metal conductive materials, and the third gate electrode 231 has gaps 232 on both sides.

In addition, the semiconductor device 200 is provided with via holes 237a, 237b, 237c, 237d, and 237e in the interlayer dielectric layer 135, and a drain electrode 139a, an electrode 239b, and a source electrode 239c (also referred to as a first Two source electrodes) and electrode 239d. The drain electrode 139a is electrically connected to the first doped region 133a through the via holes 237a and 237b, the electrode 239b is electrically connected to the third gate electrode 231 through the via hole 237c, and the source electrode 239c is electrically connected through the via hole 237d. The doped region 233b and the electrode 239d are electrically connected to the fourth doped region 133d through the via hole 237e.

FIG. 5 shows the relationship between the distance d between the top layer 127 and the second doped region 133b in the semiconductor device 100 and the pinch-off voltage of the semiconductor device 100 according to some embodiments of the present invention. Curve Illustration.

As shown in FIG. 5, the distance d between the top layer 127 and the second doped region 133 b has a positive linear relationship with the pinch-off voltage. In some embodiments, the distance d is in a range of about 0.34 micrometers to about 1.94 micrometers, and the clamping voltage of the semiconductor device 100, such as a junction field effect transistor, is in a range of about 8 volts to about 24 volts. Because the clamping voltage of the junction field effect transistor has a positive linear relationship with the distance d, the clamping voltage of the junction field effect transistor can be accurately controlled by adjusting the distance d to meet the requirements of different product applications. demand.

FIG. 6 is a device characteristic data list showing some examples of the semiconductor device 100 according to some embodiments of the present invention. As shown in Fig. 6, the target pinch voltage of Example 1 is 8 volts, the target pinch voltage of Example 2 is 18 volts, the target pinch voltage of Example 3 is 19 volts, and the measured results of the pinch voltage of three examples All meet their predetermined target values.

In consideration of process variation, for example, when the doping concentration of the top layer is in the range of 10% to 10% higher than the predetermined doping concentration, the clamping voltage of Example 1 is in the range of 7.12 volts to 9.33 volts. The clamping voltage of the second is in the range of 17.1 volts to 19.35 volts, and the clamping voltage of the third example is in the range of 18.05 volts to 20.25 volts. Overall, the measured results of the clamping voltage of the three examples all fall within the range of 0.8 times to 1.2 times the predetermined target value. Therefore, even if the influence caused by process variation is considered, the distance d can be accurately adjusted by Controls the pinch-off voltage of the semiconductor device.

In addition, it can be seen from FIG. 6 that the measured values of the breakdown voltages of the three examples are all higher than a predetermined target value (770 volts). Considering process variation, for example, when the doping concentration of the top layer is 10% to 10% lower than the predetermined doping concentration When the range is within the range of three, the breakdown voltages of the three examples are all higher than the predetermined target value. Therefore, the semiconductor device of the embodiment of the present invention can withstand ultra-high voltage, for example, about 700 volts to about 800 volts.

The present invention provides some embodiments of the structure of a semiconductor device and a method for manufacturing the same, particularly a junction field effect transistor that is resistant to high voltages (about 700 volts to about 800 volts). In the past, by adjusting the doping concentration in the well region of the junction field effect transistor during the manufacturing process, the junction field effect transistor produced a specific pinning voltage to meet the requirements of different product applications. However, the doping concentration in the well area is not easy to accurately control, so that the pinch voltage of the produced junction field effect transistor is likely to cause a non-negligible error between the target pinch voltage and the expected pinch voltage target value.

In order to more accurately regulate the clamping voltage of the junction field-effect transistor, the embodiment of the present invention sets a top layer in the first well region of the junction field-effect transistor, and the conductivity type and electrical connection of the top layer are electrically connected to the gate. The conductivity type of the second doped region of the electrode is the same, and there is a distance between the two. This distance has a positive linear relationship with the clamping voltage of the junction field effect transistor, that is, as the distance is larger, The pinning voltage of the produced junction field effect transistor is higher. Therefore, according to the embodiment of the present invention, the pinch voltage of the junction field effect transistor can be accurately controlled by adjusting the distance.

In addition, in the embodiment of the present invention, a deep well region is provided below the first well region of the junction field effect transistor, and a part of the first well region is adjacent to the deep well region. With the arrangement of the first well region and the deep well region, the embodiment of the present invention makes it easier for the current of the junction field effect transistor to be pinched in a direction perpendicular to the surface of the semiconductor substrate.

The foregoing outlines several embodiments in order to provide Those with ordinary knowledge in the domain can better understand the viewpoints of the embodiments of the present invention. Those having ordinary knowledge in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

Claims (12)

A semiconductor device includes: a semiconductor substrate having a first conductivity type; a deep well region disposed in the semiconductor substrate having a second conductivity type opposite to the first conductivity type; a first well region provided with Within the semiconductor substrate and having the second conductivity type, wherein the first well region is located above the deep well region, and a portion of the first well region is adjacent to the deep well region, and the length of the first well region is greater than the deep well region A first doped region, a second doped region, and a third doped region are disposed in the first well region, wherein the first doped region and the third doped region have the first doped region Two conductivity types, and the second doped region has the first conductivity type; and a top layer, which is disposed in the first well region and has the first conductivity type, wherein the top layer is located in the first doped region and the There is a distance between the second doped regions and between the top layer and the second doped region, and the distance has a positive linear relationship with the pinch-off voltage of the semiconductor device. The semiconductor device according to item 1 of the patent application scope, wherein the deep well region extends directly below the top layer. The semiconductor device according to item 1 of the patent application scope further includes: a first source electrode, a drain electrode and a first gate electrode, which are disposed on the semiconductor substrate, wherein the first doped region is electrically Is electrically connected to the drain electrode, the second doped region is electrically connected to the first gate electrode, and the third doped region is electrically connected to the first source electrode. The semiconductor device according to item 1 of the application, wherein the doping concentration of the second doped region is higher than that of the top layer. The semiconductor device according to item 1 of the patent application scope, wherein the top layer includes at least two discontinuous portions and wherein the length of the discontinuous portions gradually increases from the first doped region toward the second doped region. . The semiconductor device according to item 1 of the patent application scope further includes a first isolation structure disposed between the first doped region and the second doped region, and the first isolation structure completely covers the top layer. ; And a second isolation structure disposed between the second doped region and the third doped region; a first electrode disposed on the first isolation structure; and a second electrode disposed on the first Two isolation structures. The semiconductor device according to item 3 of the scope of patent application, further comprising: a second well region disposed in the semiconductor substrate and laterally adjacent to the first well region, wherein the second well region has the first conductivity A fourth doped region disposed in the second well region and having the first conductivity type; and a second gate electrode disposed on the semiconductor substrate, wherein the second gate electrode is electrically connected To the fourth doped region and the first gate electrode. The semiconductor device according to item 7 of the scope of patent application, further comprising: a laterally diffused metal oxide semiconductor field effect transistor, including: a second source electrode, a third gate electrode, and the drain electrode. On the semiconductor substrate, the third gate electrode covers a portion of the first well region, a portion of the second well region, and a portion of the semiconductor substrate between the first well region and the second well region. A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first conductivity type; forming a deep well region in the semiconductor substrate, the deep well region having a second conductivity type opposite to the first conductivity type; A first well region is formed in the semiconductor substrate, the first well region has the second conductivity type, wherein the first well region is formed above the deep well region and a portion of the first well region is adjacent to the deep well region, wherein The depth of the deep well region is greater than the depth of the first well region, and the doping concentration of the deep well region is less than the doping concentration of the first well region; a first doped region, a first doped region are formed in the first well region; Two doped regions and a third doped region, wherein the first doped region and the third doped region have the second conductivity type, and the second doped region has the first conductivity type; A top layer is formed in a well region, the top layer having the first conductivity type, wherein the top layer is located between the first doped region and the second doped region, and the top layer is separated from the second doped region A distance, wherein the distance and the semiconductor A clamping voltage provided has a positive linear relationship; and a source electrode, a drain electrode, and a first gate electrode are formed on the semiconductor substrate; wherein the distance is adjusted so that the clamp of the semiconductor device The stop voltage reaches a predetermined target value. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, wherein the first doped region is electrically connected to the drain electrode, the second doped region is electrically connected to the first gate electrode, and The third doped region is electrically connected to the source electrode. The method for manufacturing a semiconductor device according to item 9 of the application, wherein the doping concentration of the first doped region, the second doped region, and the third doped region is greater than the doping concentration of the top layer. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, further comprising: forming a second well area in the semiconductor substrate, wherein the second well area is laterally adjacent to the first well area, and the first Two well regions have the first conductivity type; a fourth doped region is formed in the second well region, the fourth doped region has the first conductivity type; and a second gate is formed on the semiconductor substrate An electrode, the second gate electrode is electrically connected to the fourth doped region and the first gate electrode.