TWI640084B - Electronic write-erase type rewritable read-only memory with low voltage difference and operation method thereof - Google Patents

Abstract

The invention discloses a low-voltage difference electronic write erasing rewritable read-only memory and a method for operating the same, which is provided with at least one transistor structure on a semiconductor substrate, and the transistor structure has a first conductive gate And using the ion implantation of the shielding portion to remove the conventional lightly doped drain (LDD) structure, and the undoped region is formed in the semiconductor substrate below the two sides of the first conductive gate, which can be increased. The transistor or the electric field between the substrate and the gate, thereby reducing the voltage difference between writing and erasing, and according to the structure, the operation method of the component is proposed. The invention can be applied to a single gate transistor structure.

Description

Electronic write-erase type rewritable read-only memory with low voltage difference and operation method thereof

The invention relates to an electronic write-erase rewritable read-only memory technology, in particular to a low-voltage difference electronic write-erase rewritable read-only memory that does not have a lightly doped drain (LDD) structure. Body and its operation method.

Nowadays, with the development of computer information products, electronically erasable programmable read-only memory (EEPROM) and non-volatile memory such as flash memory are all electronic means A semiconductor storage device that is repeatedly rewritten requires only a specific voltage to erase data in the memory in order to write new data, and the data will not disappear after the power is turned off, so it is widely used in various electronic products.

Since the non-volatile memory system is programmable, it uses stored charge to change the gate voltage of the transistor of the memory, or does not store charge to leave the gate voltage of the transistor of the original memory. The erase operation is to remove the charge stored in the non-volatile memory, so that the non-volatile memory returns to the gate voltage of the transistor of the original memory. For current non-volatile memory, a high voltage difference is required during erasure, which will increase the area and the complexity of the process.

In addition, please refer to FIG. 1A and FIG. 1B, which are cross-sectional views showing the fabrication of a standard metal-oxide-semiconductor field-effect transistor (MOS) structure in a sub-micron process. As shown in FIG. 1A, after a gate stacked structure of the gate dielectric layer 51 and the conductive gate 52 is formed on the semiconductor substrate 50, a light ion doping process is performed with the conductive gate 52 as a shield to form a light ion doping process. Ionic doped region 53. As shown in FIG. 1B, a spacer 54 is formed on both sides of the conductive gate 52, and the spacer 54 and the conductive gate 52 are used as a shield. A heavy ion doping process is performed to form a source 55 and a drain. Electrode 56 structure; the light ion-doped region 53 is a lightly doped drain (LDD) 57 region.

Under the condition that the stability of the memory element is not affected and the complexity of the existing process is not increased, the present invention specifically addresses a deficiency of the foregoing prior art, and particularly proposes a low-current and low-voltage electronic write-erase type rewritable Read-only memory and how to operate this memory architecture.

The main purpose of the present invention is to provide a low-voltage-difference electronic write erasable rewritable read-only memory and a method for operating the same, which utilizes a lightly doped drain ( LDD) area is removed to increase the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference between erasing or writing, and using the method of the present invention to achieve a large number of memory cell erasures And written effect.

Another object of the present invention is to provide an electronic write-erase type rewritable read-only memory with a low voltage difference and a method for operating the same. The substrate / well-to-gate voltage difference allows electrons to pass through the dielectric layer (oxide layer) to achieve the purpose of low current writing or erasing.

In order to achieve the above object, the present invention proposes a low-voltage-difference electronic write-erase rewritable read-only memory, which mainly includes a semiconductor substrate on which at least one transistor structure and a capacitor structure are disposed. The transistor The structure includes a first dielectric layer on a surface of a semiconductor substrate, a first conductive gate disposed on the first dielectric layer, two undoped regions located in a semiconductor substrate below two sides of the first conductive gate, and at least two The first ion-doped regions are respectively located in a semiconductor substrate below two sides of the first conductive gate and are separated from the aforementioned undoped regions, so as to serve as a source and a drain, respectively. The capacitor structure is located on the surface of the semiconductor substrate and is isolated from the transistor structure. The capacitor structure includes a second ion-doped region in the semiconductor substrate, a second dielectric layer on the surface of the second ion-doped region, and a second The conductive gate is stacked on the second dielectric layer, and the second conductive gate is electrically connected to the first conductive gate as a single floating gate.

The present invention uses an ion implantation method that shields a part of a region to remove a lightly doped drain (LDD) region in a conventional transistor structure, thereby forming an undoped region, which can increase the distance between the transistor or the substrate and the gate. The electric field reduces the voltage difference between writing and erasing.

When the transistor structure of the present invention is an N-type transistor, the first ion-doped region or the second ion-doped region is an N-type doped region, and the semiconductor substrate is a P-type semiconductor substrate or has P Semiconductor substrate of a well. When the transistor structure is a P-type transistor, the first ion-doped region or the second ion-doped region is a P-type doped region, and the semiconductor substrate is an N-type semiconductor substrate or an N-type well. Semiconductor substrate.

In addition, the capacitor structure may further have a lightly doped drain (LDD) to replace the well structure. The lightly doped drain is located in a semiconductor substrate adjacent to the second ion doped region under one side of the second conductive gate. When the transistor is an N-type transistor, the operation method of the present invention includes applying a gate voltage V _g and a source to the first conductive gate or single floating gate, source, drain, and semiconductor substrate, respectively. The voltage V _s , the drain voltage V _d and the substrate voltage V _sub satisfy the following conditions: when writing, V _sub = ground, V _s = V _d = 0 or greater than 0V, and V _g = high voltage (HV) , Or satisfy V _sub = ground, V _s = V _d = high voltage, and V _{g is} greater than 2V; and when erasing, satisfy V _sub = ground, V _s = V _d = high voltage, and V _g = 0 or floating Connected or less than 2V.

When the transistor is a P-type transistor, the operation method of the present invention includes applying a gate voltage V _g and a source to the first conductive gate or single floating gate, source, drain, and semiconductor substrate, respectively. The voltage V _s , the drain voltage V _d and the substrate voltage V _sub satisfy the following conditions: when writing, V _sub = high voltage, V _s = V _d = high voltage or less, and V _g = 0, or Meet V _sub = high voltage, V _s = V _d = 0, and V _g = less than 2 V above the high voltage; and when erasing, satisfy V _sub = high voltage, V _s = V _d = 0, and V _g = floating or Less than 2V within high voltage.

The specific embodiments and the accompanying drawings are used for detailed descriptions below to make it easier to understand the purpose, technical content, and effects achieved by the present invention.

The invention mainly provides a low-voltage-difference electronic write-erase rewritable read-only memory and an operation method thereof. The light-doped drain (LDD) in a conventional transistor structure is removed, and an undoped is formed. Area to increase the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference between erasing or writing, and using the operating method of the present invention, simultaneously applying an operating voltage to the gates connected to all memory cells , Source and drain to achieve the effect of erasing and writing a large number of memory cells.

As shown in FIG. 2, the electronic write erasable rewritable read-only memory according to the present invention mainly includes: a semiconductor substrate 10, and at least one transistor structure 12 is formed on the semiconductor substrate 10. The transistor structure 12 includes a first dielectric layer 14 located on the surface of the semiconductor substrate 10. A first conductive gate 16 is disposed on the first dielectric layer 14. Two undoped regions 17 are located on the first conductive gate 16. In the semiconductor substrate 10 below the two sides, at least two first ion-doped regions (18, 20) are respectively located in the semiconductor substrate 10 below the two sides of the first conductive gate 16 and separated from the undoped region 17, Let them be the source 18 and the drain 20, respectively. Among them, the present invention allows electrons to pass through the dielectric layer (oxide layer) through the voltage difference between the source / drain to the gate, or the voltage difference between the substrate / well to the gate to achieve low current. The purpose of writing or erasing.

Continuing, a spacer 22 is further provided on the two side walls of the first dielectric layer 14 and the second conductive gate 16 of the transistor structure 12, and before the spacer 22 is formed, a spacer is used to shield In the way of doping region 17, light ion doping is performed first, and then spacer 22 is used as a shield. Isotype ions are implanted for heavy ion doping to increase the concentration of the first ion doped region. The ion-doped regions 18 and 20 do not have a lightly doped drain (LDD) region. Therefore, the present invention can achieve the purpose of low current writing or erasing without affecting the stability of the memory element and avoiding increasing the complexity of the existing process.

The electronic write-erase rewritable read-only memory according to the present invention further includes a capacitor structure, so that the second conductive gate of the capacitor structure is electrically connected to the first conductive gate as a single floating gate. . The detailed application of various structures and operation methods will be explained in order as follows.

First, please refer to FIG. 3, the single memory cell structure of the electronic write-erase rewritable read-only memory includes a P-type semiconductor substrate 30 on which an N-type transistor 32 and an N-type well ( N-well) capacitor 34 is separated by an isolation element 36. The N-type transistor 32, such as an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), includes a first dielectric layer 320 on the surface of the P-type semiconductor substrate 30, and a first conductive gate 322 stacked on the first Above the dielectric layer 320, two undoped regions 323 are located in the P-type semiconductor substrate 30 below two sides of the first conductive gate 322, and two N-type ion-doped regions are located in P below the two sides of the first conductive gate 322. The semiconductor substrate 30 is separated from the undoped region 323 to serve as its source 324 and drain 326, respectively, and a channel is formed between the source 324 and the drain 326. The N-type well capacitor 34 includes a second ion-doped region in the P-type semiconductor substrate 30 and serves as an N-type well 340. A second dielectric layer 342 is located on the surface of the N-type well 340 and is on the second dielectric layer 342. A second conductive gate electrode 344 is disposed on the top to form a capacitor structure of the top plate-dielectric layer-bottom plate. The first conductive gate 322 of the N-type transistor 32 and the second conductive gate 344 of the N-type well capacitor 34 are electrically connected and isolated by the isolation element 36 to form a single floating gate. ) Structure of 38.

Secondly, please refer to FIG. 4 again. The single memory cell structure of the electronic write-erase rewritable read-only memory includes a P-type semiconductor substrate 30 on which an N-type transistor 32 and an N-type capacitor are disposed. 34 ', the two are separated by an isolation element 36. The N-type transistor 32, such as an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), includes a first dielectric layer 320 on the surface of the P-type semiconductor substrate 30, and a first conductive gate 322 stacked on the first Above the dielectric layer 320, two undoped regions 323 are located in the P-type semiconductor substrate 30 below two sides of the first conductive gate 322, and two N-type ion-doped regions are located in P below the two sides of the first conductive gate 322. The semiconductor substrate 30 is separated from the undoped region 323 to serve as its source 324 and drain 326, respectively, and a channel is formed between the source 324 and the drain 326. The N-type capacitor 34 ′ includes a second ion-doped region in the P-type semiconductor substrate 30, a second dielectric layer 342 is located on the surface of the P-type semiconductor substrate 30, and a second dielectric layer 342 is disposed on the second dielectric layer 342. The conductive gate 344 is formed to form a capacitor structure of the top plate, the dielectric layer and the bottom plate, and the N-type capacitor 34 'further includes a lightly doped drain (LDD) 345 to replace the role of the N-type well 340 in FIG. 3, The lightly doped drain electrode 345 is located in the P-type semiconductor substrate 30 adjacent to the second ion doped region under one side of the second conductive gate 344. The first conductive gate 322 of the N-type transistor 32 and the second conductive gate 344 of the N-type capacitor 34 'are electrically connected and isolated by the isolation element 36 to form a single floating gate. ) Structure of 38.

Please refer to FIG. 3 and FIG. 4 at the same time. Regardless of the memory cell structure shown in FIG. 3 or FIG. 4, when this electronic write-erase type rewritable read-only memory has an N-type transistor 32 In addition, there is no lightly doped drain (LDD) in the N-type transistor 32 to increase the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference of erasing or writing. At this time, the operation method of the present invention includes: applying a gate voltage V _g , a source to the first conductive gate 322 or the single floating gate 38, the source 324, the drain 326, and the P-type semiconductor substrate 30, respectively. The pole voltage V _s , the drain voltage V _d, and the substrate voltage V _sub simultaneously satisfy the following conditions: at the time of writing, V _sub = ground, V _s = V _d = 0 or greater than 0 V, and V _g = high voltage ( HV), or V _sub = ground, V _s = V _d = high voltage, and V _{g is} greater than 2V; and when erasing, V _sub = ground, V _s = V _d = high voltage, and V _g = 0 Or floating or less than 2V.

Please refer to FIG. 5 again. The single memory cell structure of the electronic write-erase rewritable read-only memory includes an N-type semiconductor substrate 40 on which a P-type transistor 42 and a P-type well (N -well) capacitor 44, which is separated by an isolation element 46 therebetween. A P-type transistor 42, such as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), includes a first dielectric layer 420 on the surface of the N-type semiconductor substrate 40, and a first conductive gate 422 stacked on the first dielectric. Above the electrical layer 420, two undoped regions 423 are located in the N-type semiconductor substrate 40 below the two sides of the first conductive gate 422, and two N-type ion-doped regions are located in the N-type below the two sides of the first conductive gate 422. In the semiconductor substrate 40, a channel is formed between the source 424 and the drain 426 with the source 424 and the drain 426 respectively. The P-type well capacitor 44 includes a second ion-doped region in the N-type semiconductor substrate 40 and serves as a P-type well 440. A second dielectric layer 442 is located on the surface of the P-type well 440 and is on the second dielectric layer 442. A second conductive gate 444 is disposed on the top to form a capacitor structure of the top plate, the dielectric layer and the bottom plate. The first conductive gate 422 of the P-type transistor 42 and the second conductive gate 444 of the P-type well capacitor 44 are electrically connected and separated by an isolation element 46 to form a single floating gate. ) Structure of 48.

Next, as shown in FIG. 6, the single memory cell structure of the electronic write-erase rewritable read-only memory includes an N-type semiconductor substrate 40 on which a P-type transistor 42 and a P-type capacitor 44 ′ are disposed. The two are separated by an isolation element 46. A P-type transistor 42, such as a P-type metal-oxide-semiconductor field-effect transistor (MOSFET), includes a first dielectric layer 420 on the surface of the N-type semiconductor substrate 40, and a first conductive gate 422 stacked on the first dielectric. Above the electrical layer 420, two undoped regions 423 are located in the N-type semiconductor substrate 40 below the two sides of the first conductive gate 422, and two N-type ion-doped regions are located in the N-type below the two sides of the first conductive gate 422. In the semiconductor substrate 40, a channel is formed between the source 424 and the drain 426 with the source 424 and the drain 426 respectively. The P-type capacitor 44 ′ includes a second ion-doped region in the N-type semiconductor substrate 40, a second dielectric layer 442 is located on the surface of the N-type semiconductor substrate 40, and a second dielectric layer 442 is disposed on the second dielectric layer 442. The conductive gate 444 is formed to form a capacitor structure of the top plate, the dielectric layer and the bottom plate, and the P-type capacitor 44 ′ further includes a lightly doped drain (LDD) 445 to replace the role of the P-type well 440 in FIG. 5, The lightly doped drain electrode 445 is located in the N-type semiconductor substrate 40 adjacent to the second ion doped region under one side of the second conductive gate 444. The first conductive gate 422 of the P-type transistor 42 and the second conductive gate 444 of the P-type capacitor 44 'are electrically connected and separated by an isolation element 46 to form a single floating gate. ) Structure of 48.

Please refer to Figure 5 and Figure 6 at the same time. Regardless of the memory cell structure shown in Figure 5 or Figure 6, when this electronic write-erase rewritable read-only memory has a P-type transistor 42 In addition, there is no lightly doped drain (LDD) in the P-type transistor 42 to increase the electric field between the transistor or the substrate and the gate, thereby reducing the voltage difference of erasing or writing. At this time, the operation method of the present invention includes: applying a gate voltage V _g and a source to the first conductive gate 422 or the single floating gate 48, the source 424, the drain 426, and the N-type semiconductor substrate 40, respectively. The voltage V _s , the drain voltage V _d and the substrate voltage V _sub simultaneously satisfy the following conditions: when writing, V _sub = high voltage, V _s = V _d = high voltage or less, and V _g = 0, or V _sub = high voltage, V _s = V _d = 0, and V _g = less than 2 V above the high voltage; and when erasing, V _sub = high voltage, V _s = V _d = 0, and V _g = floating Or less than 2V of high voltage.

The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand and implement the content of the present invention. Any equal changes or modifications made according to the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

10‧‧‧ semiconductor substrate

12‧‧‧ transistor structure

14‧‧‧ first dielectric layer

16‧‧‧The first conductive gate

17‧‧‧ undoped region

18‧‧‧ source

20‧‧‧ Drain

22‧‧‧ spacer

30‧‧‧P-type semiconductor substrate

32‧‧‧N type transistor

320‧‧‧ first dielectric layer

322‧‧‧First conductive gate

3221‧‧‧Floating gate

3222‧‧‧Control dielectric layer

3223‧‧‧Control gate

323‧‧‧ undoped region

324‧‧‧Source

326‧‧‧ Drain

34‧‧‧N Well Capacitor

34’‧‧‧N type capacitor

340‧‧‧N Well

342‧‧‧Second dielectric layer

344‧‧‧Second conductive gate

345‧‧‧ lightly doped drain

36‧‧‧Isolation element

38‧‧‧Single floating gate

40‧‧‧N-type semiconductor substrate

42‧‧‧P-type transistor

420‧‧‧first dielectric layer

422‧‧‧First conductive gate

4221‧‧‧Floating gate

4222‧‧‧Control dielectric layer

4223‧‧‧Control gate

423‧‧‧ undoped region

424‧‧‧Source

426‧‧‧Drain

44‧‧‧P-type well capacitor

44’‧‧‧P type capacitor

440‧‧‧P well

442‧‧‧Second dielectric layer

444‧‧‧Second conductive gate

445‧‧‧ lightly doped drain

46‧‧‧Isolation element

48‧‧‧Single floating gate

50‧‧‧ semiconductor substrate

51‧‧‧Gate dielectric layer

52‧‧‧ conductive gate

53‧‧‧ light ion doped region

54‧‧‧ spacer

55‧‧‧Source

56‧‧‧ Drain

57‧‧‧ lightly doped drain

1A and 1B are cross-sectional views of a MOS structure with a lightly doped drain (LDD) fabricated in the prior art. FIG. 2 is a schematic diagram of the structure of a low-voltage-difference electronic write-erase rewritable read-only memory provided by the present invention. FIG. 3 is a schematic diagram of a single memory cell structure with an N-type transistor and a single floating gate structure according to the present invention. FIG. 4 is a schematic diagram of a single memory cell structure with an N-type transistor and a single floating gate structure according to the present invention. FIG. 5 is a schematic diagram of a single memory cell structure with a P-type transistor and a single floating gate structure according to the present invention. FIG. 6 is a schematic diagram of a single memory cell structure with a P-type transistor and a single floating gate structure according to the present invention.

Claims (12)

An electronic write-erase type rewritable read-only memory with low voltage difference includes: a semiconductor substrate; at least one transistor structure formed on the semiconductor substrate; the transistor structure includes a first dielectric layer located on the semiconductor substrate; On the surface of the semiconductor substrate, a first conductive gate is located on the first dielectric layer, two undoped regions are located in the semiconductor substrate below two sides of the first conductive gate, and at least two first ions are doped. A region is located in the semiconductor substrate below the two sides of the first conductive gate and is separated from the undoped regions to serve as a source and a drain, respectively; and a capacitor structure is located on the surface of the semiconductor substrate and is in contact with The at least one transistor is isolated from each other. The capacitor structure includes a second ion-doped region inside the semiconductor substrate, a second dielectric layer on a surface of the second ion-doped region, and a second conductive gate stacked. On the second dielectric layer, and the second conductive gate is electrically connected to the first conductive gate as a single floating gate. The low-voltage-difference electronic write-erase type rewritable read-only memory according to item 1 of the claim, wherein when the transistor structure is an N-type transistor, the first ion-doped regions and the first The two ion-doped regions are N-type doped regions, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate having a P-type well; and when the transistor structure is a P-type transistor, the first ions are The doped region and the second ion doped region are P-type doped regions, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate having an N-type well. The low-voltage-difference electronic write-erase rewritable read-only memory according to claim 1, wherein the capacitor structure further includes a lightly doped drain (LDD) located at one of the second conductive gates. Inside the semiconductor substrate adjacent to the second ion-doped region under the side. The low-voltage-difference electronic write-erase type rewritable read-only memory according to claim 1, wherein the first dielectric layer of the transistor structure and the two sidewalls of the first conductive gate are further provided. There are two spacers, and the undoped regions are located in the semiconductor substrate under the spacers. The low-voltage-difference electronic write-erase rewritable read-only memory as described in claim 4, wherein the first ion-doped regions are masked with a photomask before the spacers are formed. In the non-doped region mode, a light ion doping is performed first, and then the spacers are used as a shield, and the same-type ions are implanted to perform a heavy ion doping to increase the concentration of the first ion doped region. The low-voltage-difference electronic write-erase rewritable read-only memory as described in item 1 of the claim, wherein the transistor structure is a metal oxide half field effect transistor (MOSFET). An operation method of an electronic write-erase type rewritable read-only memory with low voltage difference. The electronic write-erase type rewritable read-only memory includes a semiconductor substrate with at least one N-type transistor structure thereon. And a capacitor structure, the N-type transistor structure has a first conductive gate, two undoped regions and at least two first ion-doped regions, and the undoped regions are located on two sides of the first conductive gate In the semiconductor substrate below, the first ion-doped regions are located in the semiconductor substrate below the two sides of the first conductive gate and are separated from the undoped regions to serve as a source and a sink, respectively. The capacitor structure has a second ion-doped region, a second dielectric layer, and a second conductive gate. The second ion-doped region is located in the semiconductor substrate, and the second dielectric layer is located in the first substrate. On the surface of the two ion-doped region, the second conductive gate is disposed on the second dielectric layer, and the second conductive gate is electrically connected to the first conductive gate as a single floating gate. The method includes: the first conductive gate or the single floating gate, the Electrode, the drain electrode and the semiconductor substrate a gate voltage applied to each V _g, the source voltage V _s, and the drain voltage V _d is the substrate voltage V _sub, and the following conditions: at the time of writing, the ground satisfies V _sub = , V _s = V _d = 0 or greater than 0V, and V _g = high voltage (HV), or satisfy V _sub = ground, V _s = V _d = high voltage, and V _{g is} greater than 2V; and when erasing, satisfy V _sub = ground, V _s = V _d = high voltage, and V _g = 0 or floating or less than 2V. The operation method of the low-voltage-difference electronic write-erase rewritable read-only memory according to claim 7, wherein the first ion-doped regions and the second ion-doped regions are N-type A doped region, and the semiconductor substrate is a P-type semiconductor substrate or a semiconductor substrate having a P-type well. The operation method of the low-voltage-difference electronic write-erase rewritable read-only memory according to claim 7, wherein the capacitor structure further includes a lightly doped drain (LDD) on the second conductive gate. Inside the semiconductor substrate adjacent to the second ion-doped region under one of the electrodes. An operation method of a low-voltage-difference electronic write-erase type rewritable read-only memory, the electronic write-erase type rewritable read-only memory includes a semiconductor substrate with at least one P-type transistor structure provided thereon And a capacitor structure, the P-type transistor structure has a first conductive gate, two undoped regions, and at least two first ion-doped regions, and the undoped regions are located on two sides of the first conductive gate In the semiconductor substrate below, the first ion-doped regions are located in the semiconductor substrate below the two sides of the first conductive gate and are separated from the undoped regions to serve as a source and a sink, respectively. The capacitor structure has a second ion-doped region, a second dielectric layer, and a second conductive gate. The second ion-doped region is located in the semiconductor substrate, and the second dielectric layer is located in the first substrate. On the surface of the two ion-doped region, the second conductive gate is disposed on the second dielectric layer, and the second conductive gate is electrically connected to the first conductive gate as a single floating gate. The method includes: the first conductive gate or the single floating gate, the Electrode, the drain electrode and the semiconductor substrate a gate voltage applied to each V _g, the source voltage V _s, and the drain voltage V _d is the substrate voltage V _sub, and the following conditions: at the time of writing, to meet the high-voltage V _sub = , V _s = V _d = high voltage or less than high voltage, and V _g = 0, or satisfy V _sub = high voltage, V _s = V _d = O, and V _g = less than high voltage 2V; and when erasing, satisfy V _sub = high voltage, V _s = V _d = 0, and V _g = float or less than 2V of high voltage. The operation method of the low-voltage-difference electronic write-erase rewritable read-only memory according to claim 10, wherein the first ion-doped regions and the second ion-doped regions are P-type A doped region, and the semiconductor substrate is an N-type semiconductor substrate or a semiconductor substrate having an N-type well. The operation method of the low-voltage-difference electronic write-erase rewritable read-only memory according to claim 10, wherein the capacitor structure further includes a lightly doped drain (LDD) on the second conductive gate Inside the semiconductor substrate adjacent to the second ion-doped region under one of the electrodes.