TWI539466B - Semiconductor memory device - Google Patents

Description

Semiconductor memory component

The present invention relates to a semiconductor memory device having a compression test mode.

Semiconductor memory components are widely used in various electronic products and computer systems to store and read data. There are many types of semiconductor memory components, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), or Synchronous Dynamic Random Memory (Synchronous Dynamic Random Memory). Access Memory, SDRAM).

In recent years, the trend of semiconductor memory components has been highly integrated, so tens of millions of memory cells will be integrated into a single memory component to store more data. Individual memory cells need to be tested during the fabrication of semiconductor memory components. As the integration density of semiconductor memory components increases, so does the test time used to determine the pass or fail state of the overall memory cell.

One method commonly used to reduce test time is to compress test methods. The compression test method compresses data stored in multiple memory cells. From The data read by the plurality of cells of each memory bank is compressed into a plurality of specific data bits or a single data bit by a data compression circuit in the memory element. In a write operation of a data compression test, a test machine provides the same data to multiple memory banks via a test channel. The data is then read from each memory bank and compressed by a compression circuit. Thereafter, the compressed data of the memory bank is output to the test machine via the channel. In this way, the test machine can judge the pass or failure state of the unit cell based on the compressed data, and repair the failed unit cell if necessary.

In the read operation of the traditional data compression test, all memory banks of the memory component are simultaneously activated. Therefore, the peak currents required for the memory components can be large and can interfere with each other. In addition, compressed data from all memory banks is output once in a single channel. Since it is impossible to judge the failure state of a single record library, it is impossible to repair a specific memory bank.

Accordingly, it is necessary to improve the data compression test method of the semiconductor memory device to solve the above problem.

It is an object of the present invention to provide a semiconductor memory device having a compression test mode. The semiconductor memory device includes a memory unit, i data pads, a sequential circuit, a compression circuit, and a signal distribution circuit. The memory unit includes m memory banks, and the memory banks are divided into n actuation groups, wherein each memory library includes a plurality of sense amplifiers to sense and amplify data between the bit lines. The data pads are used in a normal mode Output the data of these memories. The timing circuit is configured to continuously generate n control signals, each control signal for activating a plurality of sense amplifiers of one of the n actuation groups. The compression circuit is configured to compress data in each memory bank sensed and amplified by the sense amplifiers in a compression test mode to generate m one-bit compressed data. The signal distribution circuit is configured to alternately allocate the one-bit compressed data between j test pads, wherein m, n, i, j are positive integers, and i data pads include j test pads, and the number of j The number of test channels equal to one test machine.

10,10’,10”,10”’,10””‧‧‧ memory unit

100,100',100",100"',100""‧‧‧ semiconductor memory components

12_0-12_7‧‧‧ memory bank

14_0-14_7‧‧‧Sense Amplifier

20‧‧‧Conversion unit

22_0-22_15‧‧‧Transition circuit

30_0-30_15‧‧‧Material Pad

40‧‧‧Compression circuit

50,50’,50”‧‧‧Signal distribution circuit

501‧‧‧Multiplexer

502‧‧‧Multiplexer

503‧‧‧Selector

504‧‧‧Selector

520‧‧‧Selector

521‧‧‧Selector

522‧‧‧Selector

523‧‧‧Selector

530,530’‧‧‧Multiple units

5302‧‧‧ and gate circuit

5304‧‧‧ and gate circuit

531‧‧‧Multiplex unit

5312‧‧‧ and gate circuit

532‧‧‧Multiplex unit

533‧‧‧Multiple units

60, 60', 60", 60"', 60"" ‧ ‧ clock circuit

BSW‧‧‧ memory bank selection switching unit

CP‧‧‧ Compressor

LIO0-LIO7‧‧‧Local Input/Output Bus

GIO‧‧‧ global input/output bus

SW1-SW18‧‧‧ switch

X0-X3‧‧‧ line

XIO0-XIO3‧‧‧ line

1 shows a block diagram of a semiconductor memory device operating in a normal mode in conjunction with an embodiment of the present invention.

2 shows a partial block diagram of the semiconductor memory device operating in a compression test mode in conjunction with an embodiment of the present invention.

3 shows a block diagram of the semiconductor memory device operating in a compression test mode in conjunction with an embodiment of the present invention.

4 is a block diagram showing the signal distribution circuit in accordance with an embodiment of the present invention.

Figure 5 shows a circuit diagram of such a multiplexer and selector incorporating an embodiment of the present invention.

6 is a block diagram showing the memory unit in accordance with an embodiment of the present invention.

Fig. 7 is a timing chart showing the operation of the memory element shown in Fig. 6.

Figure 8 is a block diagram showing the memory unit in accordance with another embodiment of the present invention.

Fig. 9 is a timing chart showing the operation of the memory element shown in Fig. 8.

Figure 10 is a block diagram showing the memory unit in accordance with still another embodiment of the present invention.

Fig. 11 is a timing chart showing the operation of the memory element shown in Fig. 10.

Figure 12 shows a block diagram of a memory component operating in a compression test mode in conjunction with another embodiment of the present invention.

Figure 13 shows a block diagram of the signal distribution circuit incorporating an embodiment of the present invention.

Figure 14 shows a block diagram of the signal distribution circuit incorporating an embodiment of the present invention.

Figure 15 is a circuit diagram showing first to fourth multiplex units in the signal distribution circuit in accordance with an embodiment of the present invention.

Figure 16 is a block diagram showing the memory unit in accordance with an embodiment of the present invention.

Fig. 17 is a timing chart showing the operation of the memory element shown in Fig. 16.

Figure 18 is a partial circuit diagram showing the signal distribution circuit in accordance with an embodiment of the present invention.

Fig. 19 is a timing chart showing the operation of the memory unit of Fig. 6 in conjunction with the multiplex unit of Fig. 18.

Figure 20 is a timing chart showing the operation of the memory unit of Figure 8 in conjunction with the multiplex unit of Figure 18.

1 shows a block diagram of a semiconductor memory device 100 operating in a normal mode in conjunction with an embodiment of the present invention. Referring to FIG. 1, the memory component 100 includes a memory unit 10, a memory bank selection switching unit BSW, a conversion unit 20, and a plurality of data pads 30_n.

The memory component 100 is a DDR2 SDRAM in this embodiment. Referring to FIG. 1, the memory unit 10 in the memory element 100 includes eight memory banks 12_0 to 12_7 and 16 data pads 30_0 to 30_15. The memory element 100 inputs and outputs data in the normal mode by means of the library data pads 30_0 to 30_15. For the sake of brevity, only the first, second, seventh and eighth databases 12_0, 12_1, 12_6, 12_7 and the first, second, fifteenth and sixteenth data pads 30_0, 30_1 are shown in FIG. , 30_14, 30_15.

Referring to Figure 1, each memory bank includes a plurality of sense amplifiers SA0-63 to sense and amplify data between bit lines. For ease of reference, the number 14_0 is assigned to the plurality of sense amplifiers of the first memory bank 12_0, the number 14_1 is assigned to the plurality of sense amplifiers of the second memory bank 12_1, and the number 14_6 is assigned to the seventh memory bank. The plurality of sense amplifiers of 12_6 and the number 14_7 are assigned to the plurality of sense amplifiers of the eighth memory bank 12_7.

Referring to Figure 1, a local input/output bus is only provided to the corresponding sense amplifier in each bank of memory. For example, from the first memory The data output from the library 12_0 will be sensed and amplified by the 64 sense amplifiers 14_0 and then supplied to the first local input/output bus LIO0<0:63>, and the data output from the second memory bank 12_1 will be The 64 sense amplifiers 14_1 are sensed and amplified and supplied to the second local input/output buss LIO1<0:63>. Referring to FIG. 1, each local input/output bus LIO0<0:63>, LIO1<0:63>, ..., LIO6<0:63>, and LIO7<0:63> are 64 local input/output The line consists of. Therefore, a local input/output line carries one bit of data at a time.

The first to eighth local input/output buss LIO0<0:63>, LIO1<0:63>, . . . , LIO6<0:63>, and LIO7<0:63> are used by the memory bank. The selection switching unit BSW is connected to a global input/output bus GIO<0:63>. Referring to FIG. 1, the global input/output bus banks GIO<0:63> are collectively supplied to the memory banks 12_0 to 12_7. The global input/output bus GIO<0:63> consists of 64 global input/output lines. Therefore, a global input/output line carries one bit of data at a time. In the normal mode, only one selected memory bank is activated, so the sense amplifier in the selected memory bank is enabled to provide data to the global input/output bus GIO by the switching unit BSW. <0:63>. For example, if the first memory bank 12_0 is selected to be activated, the 64-bit data carried on the local input/output bus LIO0<0:63> is transmitted to the global domain by the switching unit BSW. Input/output bus GIO<0:63>. Then, if the second memory bank 12_1 is selected to be activated, the 64-bit data carried on the local input/output line LIO1<0:63> is transmitted to the global input/output by the switching unit BSW. Bus GIO<0:63>. Therefore, the data contained in the global input/output bus GIO<0:63> will only correspond to one of the memory banks 12_0 to 12_7 at a time in the normal mode.

Referring to FIG. 1, the conversion unit 20 includes a plurality of conversion circuits COV 22_0 to 22_15. As known to those skilled in the art, DDR2 SDRAM uses a four-bit prefetch operation to output four bits of data to a data pad during two clock cycles. Therefore, in the read operation in the normal mode, each of the conversion circuits COV 22_0 to 22_15 receives the four-bit parallel data carried on the four global input/output lines and converts them into a serial form. Then, the output signals of the conversion circuits COV 22_0 to 22_15 are output to the outside through the data pads 30_0 to 30_15. In the write operation in the normal mode, each of the conversion circuits COV 22_0 to 22_15 receives the serial data from the data pads 30_0 to 30_15 and converts them into a side-by-side format. Then, the output signals of the conversion circuits COV 22_0 to 22_15 are written to the global input/output bus GIO<0:63>.

2 shows a partial block diagram of the semiconductor memory device 100 operating in a compression test mode in conjunction with an embodiment of the present invention. Referring to FIG. 2, the memory device 100 includes the memory unit 10 and a compression circuit 40. When the memory component operates in the compression test mode, the same data is simultaneously written into the plurality of memory banks of the memory unit. Then, a part of the memory bank is started at the same time, and the data is simultaneously read by the activated memory bank and compressed by the compression circuit 40.

For the sake of brevity, only the first and second databases 12_0 and 12_1 are shown in FIG. In the reading operation in the compression test mode, the switches (not shown) in the switching unit BSW are all disconnected. Therefore, the data contained in these local input/output bus banks LIO0<0:63>, LIO1<0:63>, ..., LIO6<0:63>, and LIO7<0:63> will not be used by The switching unit BSW is transferred to the global input/output bus bar GIO<0:63>. Referring to Figure 2, the compression circuit 40 is responsible for compressing the data on the local input/output bus banks LIO0 <0:63> and LIO1 <0:63> to output two bit metadata C0 and C1. Therefore, the data C0 and C1 represent the compression results of the memory banks 12_0 and 12_1, respectively.

Referring to Figure 2, the compression circuit 40 includes a plurality of compressors CP. In the present embodiment, each compressor CP in the compression circuit 40 is an eight to one compressor. That is, each compressor CP can receive eight bit parallel data on eight local input/output lines to output one bit compressed data to the corresponding global input/output line. In this way, the compressed data read from the memory bank 12_0 is output to the global input/output lines GIO<0:7>, and the compressed data read from the memory bank 12_1 is output to the global input/output line GIO< 8:15>. Therefore, the compression results of the memory banks 12_0 to 12_7 are sequentially output to the global input/output bus GIO<0:63>.

In this embodiment, the memory unit 10 includes first to eighth memory banks 12_0 to 12_7, eight local input/output buss LIO0<0:63> to LIO7<0:63>, and one global input/ Output bus GIO<0:63>. However, the number of memory banks and the number of local input/output bus banks GIO<0:63> The number of destination or global input/output buss GIO<0:63> can be adjusted according to different designs. For example, when the memory unit 10 is designed to include first to fourth memory banks 12_0 to 12_3, four local input/output buss LIO0<0:63> to LIO3<0:63> and one global input/output sink When GIO<0:63>, the compression results of the first to fourth memory banks 12_0 to 12_3 are sequentially output to the partial lines on the global input/output bus GIO<0:63>, for example, the first to 32. Input/output lines GIO<0> to GIO<31>.

3 shows a block diagram of the semiconductor memory device 100 operating in a compression test mode in conjunction with an embodiment of the present invention. Referring to FIG. 3, the memory device 100 includes the compression circuit 40, a signal distribution circuit 50, a sequential circuit 60, a driving unit 70, and the data pads 30_0 and 30_1.

In the present embodiment, the test machine (not shown) will only allocate two test channels (not shown) in the compression test mode to test the memory component 100. Therefore, only two data pads of the data pads 30_0 to 30_15 shown in FIG. 1 are used as test pads. Accordingly, the signal distribution circuit 50 is responsible for alternately distributing the signals C0 to C7 output by the compression circuit 40 to the test pads 30_0 and 30_1, wherein the data C0 to C7 represent the compression results of the memory banks 12_0 to 12_7, respectively. In an embodiment of the present invention, the signal distribution circuit 50 outputs data to the line X0 in the order of C0, C2, C4, and C6, and outputs the data to the line X1 in the order of C1, C3, C5, and C7. Next, the drive circuits (DRI) 72 and 74 in the drive unit 70 drive the data on the lines X0 and X1 to the outside by the test pads 30_0 and 30_1 in the compression test mode.

4 shows a block diagram of the signal distribution circuit 50 in connection with an embodiment of the present invention. Referring to FIG. 4, the signal distribution circuit 50 includes multiplexers (MUX) 501 and 502 and selectors (SEL) 503 and 504. The multiplexer 501 receives signals C0, C2, C4, and C6 output from the compression circuit 40, and the multiplexer 502 receives signals C1, C3, C5, and C7 output from the compression circuit 40. The selector 503 is connected between the multiplexer 501 and the drive circuit 72 shown in FIG. 3, and the selector 504 is connected between the multiplexer 502 and the drive circuit 74 shown in FIG.

Figure 5 shows a circuit diagram of the multiplexers 501 and 502 and selectors 503 and 504 incorporating an embodiment of the present invention. Referring to FIG. 5, the multiplexer 501 includes switches SW1, SW2, SW3, and SW4, and the multiplexer 502 includes switches SW5, SW6, SW7, and SW8, wherein the switches SW1 to SW8 are according to the sequential circuit 60 of FIG. The output signals S2<0> and S2<1> are turned on. The selector 503 includes switches SW9 and SW10, and the selector 504 includes switches SW11 and SW12, wherein the switches SW9 to SW12 are turned on according to the signals D0<0> and D0<1> output by the sequential circuit 60.

As described above, the memory unit 10 can include the memory banks 12_0 to 12_7 shown in FIG. 1. The memory banks 12_0 to 12_7 can be divided into complex arrays in which a plurality of sense amplifiers in each group are simultaneously activated according to the enable signal SAE output by the sequential circuit 60. Figure 6 shows a block diagram of the memory unit 10' incorporating an embodiment of the present invention. Elements in Fig. 6 that function similarly to Figs. 1 and 3 are shown with the same numerals. Referring to FIG. 6, the memory banks 12_0 to 12_7 will be divided into first to eighth actuation groups GROUP_0 to GROUP_7. Therefore, in this embodiment, each consistent motion group is composed of one memory bank.

Referring to FIG. 6, a sequence circuit 60 receives a bank control signal BA<2:0> and a clock signal XCLK from a memory controller (not shown), and outputs a plurality of control signals SAE<0:7> to Start the sense amplifiers in the different actuation groups. Fig. 7 is a timing chart showing the operation of the memory element 100' shown in Fig. 6. Referring to FIGS. 6 and 7, the first to eighth control signals SAE<0> to SAE<7> are sequentially activated to sequentially enable the sense amplifiers in the different actuation groups. Therefore, the sense amplifier in the first actuation group GROUP_0 will be enabled during the first two clock cycles, and the sense amplifier in the second actuation group GROUP_1 will be caused during the next two clock cycles. Can,..., and the sense amplifier in the final consistent group GROUP_7 will be enabled during the final two clock cycles.

Since the sense amplifiers in the different actuation groups are sequentially enabled, the data read from the memory banks in the different actuation groups are sequentially output to the local input/output bus LIO0<0:63> to LIO7<0:63>. Referring to FIG. 6, the compression circuit 40 compresses the data on the local input/output bus banks LIO0<0:63> to LIO7<0:63> to output one bit of the compressed data C0 to C7 one by one. 7 is shown. Since the memory element 100' is a DDR2 SDRAM in this embodiment, each bit compressed data C0 to C7 is output to the signal distribution circuit 50 during two clock cycles, and thereafter maintains a logic one. Level.

Referring to Figures 5 and 7, when one of the signals C0, C1, C2 and C3 When enabled, the signal S2<0> output from the sequential circuit 60 is switched to the level of the logic 1, so the switches SW1, SW3, SW5 and SW7 are turned on in response to the timing signal S2<0>. In this example, signals C0 and C2 are transmitted to the selector 503 via switches SW1 and SW3, and signals C1 and C3 are transmitted to the selector 504 via switches SW5 and SW7.

Referring to FIG. 7, the timing signals D0<0> and D0<1> output from the sequential circuit 60 are enabled every two clock cycles, and the rising edge of the timing signal D0<0> leads the timing signal D0<1>. A rising edge of a clock cycle. Referring to Figures 5 and 7, signal C0 is enabled during the first two clock cycles. Then, when the first pulse of the timing signal D0<0> is generated, the enabled signal C0 is transmitted to the line X0. Signal C1 is enabled during the next two clock cycles. Next, when the second pulse of the timing signal D0<0> is generated, the enabled signal C1 is transmitted to the line X1. Signal C2 is enabled during the next two clock cycles. Then, when the third pulse of the timing signal D0<1> is generated, the enabled signal C2 is transmitted to the line X0. Signal C3 is enabled during the next two clock cycles. Next, when the fourth pulse of the timing signal D0<1> is generated, the enabled signal C3 is transmitted to the line X1.

During the subsequent clock cycle, signals C4, C5, C6, and C7 are continuously enabled every two clock cycles, and the signal S2<1> output from the timing circuit 60 transitions to a logic one level. The switches SW2, SW4, SW6 and SW8 are turned on in response to the timing signal S2<1>. Referring to FIG. 5 and FIG. 7, when the fifth pulse of the timing signal D0<0> is generated, the enabled signal C4 is transmitted to the line X0; When the sixth pulse of the signal D0<0> is generated, the enabled signal C5 is transmitted to the line X0; when the seventh pulse of the timing signal D0<1> is generated, the enabled signal C6 is transmitted to the line. X0; When the eighth pulse of the timing signal D0<1> is generated, the enabled signal C7 is transmitted to the line X1.

In the above embodiment, the memory banks 12_0 to 12_7 in the memory unit 10' are divided into first to eighth actuation groups GROUPO_0 to GROUP_7. In other embodiments of the present invention, the memory banks 12_0 to 12_7 may be divided into first to fourth actuation groups GROUPO_0, GROUP_1, GROUP2, and GROUP_3, as shown in FIG. In this embodiment, each consistent group consists of two memory banks.

Referring to FIG. 8, the sequential circuit 60 sequentially outputs four control signals SAE<0>, SAE<1>, SAE<2>, and SAE<3> to sequentially activate the sense amplifiers in the different actuation groups. Figure 9 shows a timing diagram of the operation of the memory element 100" shown in Figure 8. Referring to Figures 8 and 9, the sense amplifier in the first actuation group GROUPO will be enabled during the first two clock cycles. Therefore, the compressed data C0 and C1 are output to the signal distribution circuit 50 during the first two clock cycles. The sense amplifier in the second actuation group GROUP_1 will be caused during the next two clock cycles. Therefore, the compressed data C2 and C3 are output to the signal distribution circuit 50 during the next two clock cycles.

Referring to Figure 9, when one of the signals C0, C1, C2, and C3 is enabled, the clock signal S2 <0> output from the sequential circuit 60" is switched to the level of logic 1. Referring to Figures 5 and 9, When the first pulse of the timing signal D0<0> is generated, The enabled signals C0 and C1 are transmitted to line X0 and line X1, respectively. When the second pulse of the timing signal D0<1> is generated, the enabled signals C2 and C3 are transmitted to the line X0 and the line X1, respectively.

Referring to Figures 8 and 9, the sense amplifiers in the third actuation group GROUP_2 will be activated during the next two clock cycles, thus producing compressed signals C4 and C5. Next, the sense amplifiers in the final coincidence group GROUP_3 are enabled during the next two clock cycles, thus producing compressed signals C6 and C7. When one of the signals C4, C5, C6 and C7 is enabled, the clock signal S2<1> output from the sequential circuit 60" is switched to the level of logic 1. Referring to Figures 5 and 9, when the timing signal D0 When the third pulse of <0> is generated, the enabled signals C4 and C5 are respectively transmitted to the line X0 and the line X1. When the last pulse of the timing signal D0<1> is generated, the enabled signal C6 and C7 will be transferred to line X0 and line X1 respectively.

In other embodiments of the present invention, the memory banks 12_0 to 12_7 in the memory unit 10"' may be divided into first and second actuation groups GROUP_0 and GROUP_1, as shown in Fig. 10. Therefore, each movement The group consists of four memory banks. The sequential circuit 60"' outputs two control signals SAE<0> and SAE<1> in sequence to activate the sense amplifiers in the different groups, respectively.

Figure 11 shows a timing diagram of the operation of the memory element 100"' shown in Figure 10. Referring to Figures 10 and 11, the sense amplifier in the first actuation group GROUPO will be caused during the first two clock cycles. Therefore, the compressed data C1, C2, C3 and C4 will be output to the signal distribution circuit 50 during the first two clock cycles. The sense amplifier in the second actuation group GROUP_1 will be followed. The two clock cycles are enabled during the period. Therefore, the compressed data C4, C5, C6 and C7 are output to the signal distribution circuit 50 during the next two clock cycles.

Referring to Figure 11, when signals C0, C1, C2, and C3 are enabled, the clock signal S2<0> output from the sequential circuit 60"' will transition to the level of logic 1. Referring to Figures 5 and 11, when timing When the first pulse of signal D0<0> is generated, the enabled signals C0 and C1 are respectively transmitted to line X0 and line X1. When the first pulse of timing signal D0<1> is generated, it is enabled. Signals C2 and C3 are transmitted to line X0 and line X1, respectively.

The sense amplifiers in the second actuation group GROUP_1 are activated during the next two clock cycle periods, thus producing compressed data C4, C5, C6 and C7. When signals C4, C5, C6 and C7 are enabled, the clock signal S2<1> output from the sequential circuit 60"' will transition to the level of logic 1. Referring to Figures 5 and 11, when the timing signal D0 < When the second pulse of 0> is generated, the enabled signals C4 and C5 are respectively transmitted to the line X0 and the line X1. When the second pulse of the timing signal D0<1> is generated, the enabled signal C6 and C7 will be transferred to line X0 and line X1 respectively.

In the above embodiment, the test machine (not shown) will only allocate two test channels (not shown) in the compression test mode to test the memory element 100. However, the invention should not be limited thereto. Figure 12 shows a block diagram of a memory component operating in a compression test mode in conjunction with another embodiment of the present invention. Elements having functions similar to those of Figs. 1 and 3 in Fig. 12 are shown by the same numerals, and the details of the circuits will not be described again. Referring to Figure 12, the test machine is assigned four test channels to test the memory component 100"" in the compression test mode. because Therefore, among the data pads 30_0 to 30_15 shown in FIG. 1, four data pads 30_0 to 30_3 are regarded as test pads.

Referring to Fig. 12, the signal distribution circuit 50' alternately distributes the signals C0 to C7 output from the compression circuit 40 between the test pads 30_0 and 30_3. Figure 13 shows a block diagram of the signal distribution circuit 50' incorporating an embodiment of the present invention. Referring to Fig. 13, the signal distribution circuit 50' includes first to fourth selectors (SEL) 520, 521, 522 and 523. The selector 520 receives signals C0 and C4 from the compression circuit 40. The selector 521 receives signals C1 and C5 from the compression circuit 40. The selector 522 receives signals C2 and C6 from the compression circuit 40. The selector 523 receives signals C3 and C7 from the compression circuit 40.

Referring to Fig. 13, the selector 520 includes switches SW1 and SW2 which are turned on in accordance with signals D0<0> and D0<1> outputted by the sequential circuit 60"". The data C0 and C4 are transmitted to the line X0 through the switches SW1 and SW2. The selector 521 includes switches SW3 and SW4 that are turned on according to signals D0<0> and D0<1> outputted by the sequential circuit 60"". The data C1 and C5 are transmitted to the line X1 through the switches SW3 and SW4. The selector 522 includes switches SW5 and SW6 that are turned on according to signals D0<0> and D0<1> outputted by the sequential circuit 60"". The data C2 and C6 are transmitted to the line X2 via the switches SW5 and SW6. The selector 523 includes switches SW7 and SW8 that are turned on in accordance with signals D0<0> and D0<1> outputted by the sequential circuit 60"". The data C3 and C7 are transmitted to the line X3 via the switches SW7 and SW8.

As described above, the signal distribution circuit 50 is fixedly distributed between the two test pads to distribute the signals C0 to C7 outputted by the compression circuit 40, and the signal distribution circuit 50' is fixedly distributed between the four test pads. C0 to C7, wherein the number of test pads is the same as the number of test channels provided by the test machine in the compression test mode. If the number of test channels changes with the test conditions, some additional switches are needed to select the data path. Figure 14 shows a block diagram of the signal distribution circuit 50" incorporating an embodiment of the present invention, wherein the signal distribution circuit 50" can alternately distribute signals C0 through C7 between one, two or four test pads.

Referring to Fig. 14, the signal distribution circuit 50" includes first to fourth multiplex units 530, 531, 532, and 533 and first to fourth selectors 520, 521, 522, and 523 as shown in Fig. 13. The first multiplex unit 530 receives the signal C0. To C7, the second multiplex unit 531 receives signals C1, C3, C5 and C7, the third multiplex unit 532 receives signals C2 and C6, and the fourth multiplex unit 533 receives signals C3 and C7. The selector 520 is connected between the first multiplex unit 530 and the driving circuit 72 shown in FIG. 12, and the second selector 521 is connected between the second multiplex unit 531 and the driving circuit 74 shown in FIG. The third selector 522 is connected between the third multiplex unit 532 and the driving circuit 76 shown in FIG. 12, and the fourth selector 523 is connected to the fourth multiplex unit 533 and the one shown in FIG. Between the drive circuits 78.

Figure 15 shows a circuit diagram of first to fourth multiplex units 530, 531, 532 and 533 in the signal distribution circuit 50" in accordance with an embodiment of the present invention. Figure. In the present embodiment, the signal distribution circuit 50" alternately distributes the signals C0 to C7 between two or four test pads, so the first multiplex unit 530 does not use the signals C1, C3, C5 and C7. Referring to FIG. 15, the first multiplex unit 530 includes two switches SW1 and SW2, a gate circuit 5302, and a multiplexer 501 shown in FIG. 5. The second multiplex unit 531 includes two switches SW3 and SW4, one. And a gate circuit 5312 and a multiplexer 502 shown in FIG. 5, the third multiplex unit 532 includes two switches SW5 and SW6, and the fourth multiplex unit 533 includes two switches SW7 and SW8.

The operation mode of the signal distribution circuit 50" will be described below with reference to Fig. 14 and Fig. 15. In the compression test mode, if compressed data of a plurality of memory banks is output to two test channels of the test machine, output to the circuit 50 A pad select signal PS2 will be enabled to a logic 1 level, and a pad select signal PS4 output to the circuit 50" will be enabled to a logic 0 level. In this case, all of Figure 15 The switches SW1 to SW8 are turned off, and the multiplexers 501 and 502 are enabled in response to the signal S2<0:1>. The signal distribution circuit 50" operates in a manner similar to that of the signal distribution circuit 50 of FIG. The mode of operation, and the details of the circuit will not be described.

On the other hand, if the compressed data of the plurality of memory banks is output to the four test channels of the test machine, the pad selection signal PS2 outputted to the circuit 50" is enabled to the level of the logic 0, and is output to The pad select signal PS4 of the circuit 50" is enabled to a level of logic 1, which causes all of the switches SW1 through SW8 to conduct. In this case, the multiplexers 501 and 502 will not be enabled in response to the logic 0 output signals of the AND gates 5302 and 5312, respectively. The signals C0 and C4 will be divided It is not transmitted to the selector 520 via the switches SW1 and SW2. The signals C1 and C5 are transmitted to the selector 521 via switches SW3 and SW4, respectively. The signals C2 and C6 are transmitted to the selector 522 via switches SW5 and SW6, respectively. The signals C3 and C7 are transmitted to the selector 523 via switches SW7 and SW8, respectively. The signal distribution circuit 50" operates in a manner similar to that of the signal distribution circuit 50' of Figure 13, and the details of the circuit will not be described again.

As previously mentioned, the memory banks 12_0 to 12_7 in the memory unit can be divided into 8 groups, 4 groups or 2 groups of actuation groups. In another embodiment of the present invention, the memory banks 12_0 to 12_7 are divided into one actuation group, so that the plurality of sense amplifiers in the memory banks 12_0 to 12_7 are output according to the sequential circuit 60"". The enable signal SAE<0> is activated at the same time. Figure 16 shows a block diagram of the memory unit 10"" incorporating an embodiment of the present invention. Referring to FIG. 16, the sequential circuit 60"" receives the bank control signal BA<2:0> and the clock signal XCLK from a memory controller (not shown), and outputs a control signal SAE<0> to start. All of the sense amplifiers in the memory unit 10"".

Fig. 17 is a timing chart showing the operation of the memory element 100"" shown in Fig. 16. Referring to Figure 17, all of the sense amplifiers in the memory unit 10"" are simultaneously enabled during two clock cycles. Therefore, the data read by the first to eighth memory banks are simultaneously output to the local input/output buss LIO0<0:63> to LIO7<0:63> in FIG. Next, the compression circuit 40 is responsible for compressing the data on the local input/output bus banks LIO0<0:63> to LIO7<0:63> to simultaneously output the one-bit compressed data C0 to C7, as shown in FIG.

In this embodiment, the signal distribution circuit alternately distributes signals C0 through C7 between the four test pads. Therefore, referring to FIG. 12 and FIG. 17, when the first pulse of the timing signal D0<0> is generated, the enabled signal C0 is transmitted to the line X0, and the enabled signal C1 is transmitted to the line X1, which is enabled. Signal C2 is transmitted to line X2 and enabled signal C3 is transmitted to line X3. Next, the drive circuits 72 to 78 in the drive unit 70 drive the data on the lines X0 to X3 to the lines XIO0 to XIO3. The data on the lines XIO0 to XIO3 are output to the outside through the test pads 30_0 to 30_3 as shown in FIG.

In another embodiment of the present invention, the signal distribution circuit alternately distributes the signals C0 to C7 output by the compression circuit 40 to a single test pad in the compression test mode. In this embodiment, some additional switches are needed to change the data transmission path. Figure 18 shows a partial circuit diagram of the signal distribution circuit 50"" incorporating an embodiment of the present invention, wherein the signal distribution circuit 50"' includes the same component multiplex units 531, 532 and 533 and selector 520 shown in Figure 14. For the sake of brevity, since the multiplex units 531, 532, and 533 are not enabled in this embodiment, they are not depicted in FIG.

Referring to Fig. 18, the first multiplex unit 530' includes two switches SW1 and SW2, two AND gate circuits 5302 and 5304, and multiplexers 501 and 505. The multiplexer 505 includes switches SW11, SW12, SW13, SW14, SW15, SW16, SW17 and SW18. The switches SW11 and SW15 are responsive to a signal S4<0>, the switches SW12 and SW16 are responsive to a signal S4<1>, the switches SW13 and SW17 are responsive to a signal S4<2>, and the switches SW14 And SW18 respond to a signal S4<3>, wherein the signals S4<0>, S4<1>, S4<2>, and S4<3> are from the clock circuit 60.

The operation mode of the signal distribution circuit 50"' will be described below. In this embodiment, since the compressed data of the plurality of memory banks is output to the test machine only through a single test channel, the pad is output to the circuit 50"'. The select signals PS2 and PS4 are enabled to a logic 0 level, and the pad select signal PS1 output to the circuit 50"' is enabled to a level of logic 1. In this case, the multiplex units 531, 532 and 533 will not be enabled, so no data will be transmitted to the outside by test pads 30_1 to 30_3.

In addition, the multiplexer 501 in the multiplex unit 530' is not enabled in response to the logic 0 output level of the AND gate 5302, and the multiplexer 505 is responsive to the logic 1 output bit of the AND gate 5304. Let it be. Therefore, the signals C0 and C1 are transmitted to the selector 520 via the switches SW11 and SW15, respectively. The signals C2 and C3 are transmitted to the selector 520 via switches SW12 and SW16, respectively. The signals C4 and C5 are transmitted to the selector 520 via switches SW13 and SW17, respectively. The signals C6 and C7 are transmitted to the selector 520 via switches SW14 and SW18, respectively.

Referring now to Figure 6, if the memory banks 12_0 to 12_7 in the memory unit 10' are divided into the first to eighth actuation groups GROUP# to GROUP_7, the compressed data of the actuation groups GROUP# to GROUP_7 will be Two clock cycles are outputted one after the other to the signal distribution circuit. Figure 19 shows the memory unit 10' of Figure 6 in combination with the multiplex unit of Figure 18. Timing diagram of the 530' operation. Referring to FIG. 19, when any one of the compressed signals C0 and C1 is enabled, the clock signal S4<0> output from the sequential circuit 60 is switched to the level of the logic 1, so that the switches SW11 of FIG. 18 and SW15 is turned on in response to the signal S4<0>. In this example, enabled signals C0 and C1 are transmitted to the selector 520 via the switches SW11 and SW15, respectively.

Referring to Figure 19, compressed data C0 will be generated during the first two clock cycles. Then, when the first pulse of the timing signal D0<0> is generated, the enabled signal C0 is transmitted to the line X0. Signal C1 is generated during the next two clock cycles. Then, when the second pulse of the timing signal D0<1> is generated, the enabled signal C1 is transmitted to the line X0.

Referring to FIG. 19, when any one of the compressed signals C2 and C3 is enabled, the clock signal S4<1> output from the sequential circuit 60 is switched to the level of logic 1; when any of the signals C4 and C5 is compressed When one is enabled, the clock signal S4<2> output from the timing circuit 60 is switched to the level of the logic 1; and when any of the compression signals C6 and C7 is enabled, the output from the timing circuit 60 is output. The clock signal S4<3> will switch to the level of logic 1.

Therefore, signals C2, C3, C4, C5, C6, and C7 are generated sequentially every two clock cycles, and the generated signals C2, C3, C4, C5, C6, and C7 are at timing signal D0<0>. The pulse wave corresponding to D0<1> is transmitted to the line X0 as shown in FIG.

In another embodiment of the present invention, the memory banks 12_0 to 12_7 in the memory unit are divided into first to fourth actuation groups GROUP_0 to GROUP_3, as shown in Figure 8. Figure 20 is a timing chart showing the operation of the memory unit 10' of Figure 8 in conjunction with the multiplex unit 530' of Figure 18. Referring to FIG. 20, when the compressed signals C0 and C1 of the memory banks 12_0 and 12_1 in the first actuation group GROUPO_0 are generated, the clock signal S4<0> output from the sequential circuit 60 is switched to the bit of the logic 1. When the compressed signals C2 and C3 of the memory banks 12_2 and 12_3 in the second actuation group GROUP_1 are generated, the clock signal S4<1> outputted from the sequential circuit 60 is switched to the level of the logic 1; When the compressed signals C4 and C5 of the memory banks 12_4 and 12_5 in the third actuation group GROUP_2 are generated, the clock signal S4<2> output from the sequential circuit 60 is switched to the level of the logic 1; When the compressed signals C6 and C7 of the memory banks 12_6 and 12_7 in the fourth actuation group GROUP_3 are generated, the clock signal S4<3> output from the sequential circuit 60 is switched to the level of the logic 1.

Referring to Fig. 20, the signals C0, C1, C2, C3, C4, C5, C6 and C7 in different actuation groups are sequentially generated every two clock cycles, and thus the time output from the timing circuit 60 The pulse signals S4<0>, S4<1>, S4<2> and S4<3> are sequentially generated every two clock cycles. In this way, the generated signals C0, C1, C2, C3, C4, C5, C6 and C7 are transmitted to the line X0 when the pulse waves corresponding to the timing signals D0<0> and D0<1> are generated, as shown in FIG. Show. Next, as shown in FIG. 12, the drive circuit 72 drives the data on line X0 to line XIO0. The data on the line XIO0 is output to the outside through the test pad 30_0 in the order of C0, C1, C2, C3, C4, C5, C6 and C7.

The technical content and technical features of the present invention have been disclosed above, however A person skilled in the art will be able to make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

100‧‧‧Semiconductor memory components

30_0, 30_1‧‧‧ test pad

40‧‧‧Compression circuit

50‧‧‧Signal distribution circuit

60‧‧‧Sequence Circuit

70‧‧‧ drive unit

72‧‧‧ drive circuit

74‧‧‧ drive circuit

X0-X1‧‧‧ line

XIO0-XIO1‧‧‧ line

Claims (9)

A semiconductor memory device comprising: a memory unit comprising m memory banks, the memory banks being divided into n actuation groups, wherein each memory bank comprises a plurality of sense amplifiers for sensing and Amplifying data between bit lines; i data pads for outputting data of the memory in a normal mode; a sequential circuit for continuously generating n control signals, each control signal for starting n a plurality of sense amplifiers of one of the actuation groups; a compression circuit for compressing the data sensed and amplified by the sense amplifiers in each memory bank in a compression test mode to generate m a one-bit compressed data; and a signal distribution circuit for alternately allocating the one-bit compressed data between the j test pads; wherein m, n, i, j are positive integers, and n is a factor of m j is a factor of i; wherein i data pads comprise j test pads, and the number of j is equal to the number of test channels of a test machine; and wherein, among the n actuation groups that are activated, When the number of memory banks is greater than 1, the j test pads are the same One-bit compressed data of the memory bank in one of the groups is output; and wherein, when the number of memory banks in one of the n actuation groups being activated is equal to 1, the j test pads The one-bit compressed data of the memory bank in the one group is sequentially output in clock cycles of different delays. The semiconductor memory component of claim 1, wherein each memory bank includes a plurality of local input/output lines connected to a plurality of sense amplifiers, The compression circuit includes a plurality of first compression circuits and a plurality of second compression circuits, and the memory unit includes a plurality of global input/output bus lines, wherein a portion of the sense amplifiers in each memory bank senses The amplified data is output to a corresponding local input/output line, and one of the first compression circuits compresses data on the corresponding local input/output line to output the first compressed data to the global input/output bus lines. One of the second compression circuits compresses the first compressed data from the first compression circuits to output one of the one-bit compressed data. The semiconductor memory device of claim 1, wherein the memory unit comprises first to eighth memory banks, the compression circuit generating a plurality of first, second, third, fourth, fifth, and third respectively 6. One-dimensional compressed data of the seventh and eighth memory banks C0, C1, C2, C3, C4, C5, C6 and C7, and the signal distribution circuit sequentially generates the one-bit compressed data. The sequences are alternately assigned to j test pads. The semiconductor memory device of claim 3, wherein when j=2, the test pads are composed of a first test pad and a second test pad, the memory banks being divided into 8 actuation groups, the sequential circuit The eight control signals are continuously generated, so that the sense amplifiers in one of the eight actuation groups are alternately activated every two clock cycles, and the compression circuit sequentially generates eight directions every two clock cycles. One bit of the memory bank in the dynamic group compresses the data, and the signal distribution circuit sequentially outputs the one-bit compressed data C0, C2, C4, C6 to the first test pad with different delayed clock cycles. And outputting the one-bit compressed data C1, C3, C5, and C7 to the second test pad in sequence with different delayed clock cycles. The semiconductor memory device of claim 3, wherein when j=2, the test pads are composed of a first test pad and a second test pad, the memory banks being divided into four actuation groups, the sequential circuit Four control signals are continuously generated, so that the sense amplifiers in one of the four actuation groups are alternately activated every two clock cycles, and the compression circuit sequentially generates four directions every two clock cycles. One bit of the memory bank in the dynamic group compresses the data, and the signal distribution circuit sequentially outputs the one-bit compressed data C0, C2, C4, C6 to the first test pad, and the one bit The meta-compressed data C1, C3, C5, C7 are sequentially output to the second test pad, wherein the first test pad and the second test pad simultaneously output the memory in one of the four actuation groups at a time The one-bit compression data of the library. The semiconductor memory device of claim 3, wherein when j=2, the test pads are composed of a first test pad and a second test pad, the memory banks being divided into two actuation groups, the sequential circuit Two control signals are continuously generated, so that the sense amplifiers in one of the two actuation groups are alternately activated every two clock cycles, and the compression circuit sequentially generates two directions every two clock cycles. One bit of the memory bank in the dynamic group compresses the data, and the signal distribution circuit sequentially outputs the one-bit compressed data C0, C2, C4, C6 to the first test pad every other clock cycle, and The one-bit compressed data C1, C3, C5, and C7 are sequentially output to the second test pad every other clock cycle, wherein the first test pad and the second test pad simultaneously output two The one-bit compressed data of the memory bank in one of the groups. According to the semiconductor memory component of claim 3, wherein when j=4, the test pads are composed of a first test pad, a second test pad, a third test pad, and a fourth test Forming a pad, the sense amplifiers in the memory banks are simultaneously activated, and the compression circuit simultaneously generates the one-bit compressed data C0, C1, C2, C3, C4, C5, C6 and C7, and the signal The distribution circuit sequentially outputs the one-bit compressed data C0 and C4 to the first test pad every other clock cycle, and sequentially outputs the one-bit compressed data C1 and C5 to the first every other clock cycle. Two test pads, the one-bit compressed data C2 and C6 are sequentially output to the third test pad every other clock cycle, and the one-bit compressed data C3 and C7 are sequentially output every other clock cycle Up to the fourth test pad, and wherein the first test pad, the second test pad, the third test pad, and the fourth test pad simultaneously output the one-bit compressed data C0 to C3, The first test pad, the second test pad, the third test pad, and the fourth test pad simultaneously output the one-bit compressed data C4 to C7. The semiconductor memory device of claim 3, wherein when j=1, the test pads are composed of a first test pad, the memory banks are divided into 8 actuation groups, and the sequential circuit continuously generates 8 a control signal that alternately activates the sense amplifiers in one of the eight actuation groups every two clock cycles, the compression circuit sequentially generating memory in the eight actuation groups every two clock cycles One bit of the volume library compresses the data, and the signal distribution circuit sequentially outputs the one-bit compressed data C0, C1, C2, C3, C4, C5, C6 and C7 to the first delayed clock cycle with different delays A test pad. The semiconductor memory device of claim 3, wherein when j=1, the test pads are composed of a first test pad, the memory banks are divided into four actuation groups, and the sequential circuit continuously generates four Controlling the signal to initiate the sensing of one of the four actuation groups in turn every two clock cycles And the compression circuit sequentially generates one bit compressed data of the memory banks in the four actuation groups every two clock cycles, and the signal distribution circuit compresses the one-bit compressed data C0, C1, C2 , C3, C4, C5, C6 and C7 are sequentially output to the first test pad every one clock cycle.