TWI538375B - Resonant converter system, method for resonant conversion and method of controlling resonant converter - Google Patents

Description

Resonance converter system, method of resonance conversion, and method of controlling resonance converter

This invention relates to a DC/DC converter system and, more particularly, to a synchronous rectifier control technique for a resonant converter.

The features and advantages of the subject matter will be apparent from the following detailed description of the embodiments of the invention.

While the following detailed description is set forth with reference to the exemplary embodiments

In general, the present invention provides control techniques for a resonant converter. In one control technique, a switcher of a rectifier portion of the resonant converter is controlled to emulate a diode, for example, each switch is controlled to conduct when an internal diode of the switch begins to conduct, and Each switch is controlled to open when the current through the switch approaches a zero crossing. In this manner, the forward bias of each switch can be controlled such that the voltage drop across the switch is much less than a conventional diode forward voltage drop while still preventing switching through a synchronous rectifier. The negative current of the device is used to achieve protection of the circuit. The control technique can predict the gate drive signal based on the previous on-time of the synchronous rectifier switch and repeatedly delay or subtract the delay from the gate drive signal to cause the falling edge of the gate drive signal to be substantially The upper zero point is matched to the current through the switch. This prediction technique can be used to compensate for component tolerances and/or errors introduced by circuit components when the switching frequency of a frequency converter stage is at or below a resonant frequency (f0). Variability. When the switching frequency of the inverter stage is higher than the resonance frequency (f0), the synchronous rectifier switch continues to be turned on after the switch in the inverter stage is turned off, and the synchronous on-time is mainly determined by the switching frequency of the inverter stage. This may generate a negative current through the rectifier switch when the synchronous rectifier is controlled based only on the synchronous on-time of the previous switching cycle, and thus, in another control technique, based on one of the conduction states for controlling the inverter-level switcher The pulse signal controls the switch of the rectifier portion to compensate for a truncated resonant period, for example, each rectifier switch is controlled such that the rectifier switch is turned on less than or equal to the current through the rectifier switch Short zero crossing point. Each of these control techniques can be employed simultaneously to achieve current protection across all operating frequencies.

FIG. 1 illustrates a resonant converter system 100 in accordance with various embodiments of the present invention. The converter system 100 of FIG. 1 includes a primary side stage 102 that includes a frequency converter circuit, and a secondary side stage 104 that includes a synchronous rectifier circuit, and the system 100 generally receives and receives an input DC voltage (VIN) and generates One of the output DC voltages (VOUT) is operated by a DC/DC resonant converter circuit. In one embodiment, the primary side 102 of the frequency converter circuit includes two switches Q1 and Q2 configured in a half bridge configuration. The conduction states of the switches Q1 and Q2 are controlled by a gate control circuit 106 that includes an controllable oscillator (OSC) that sets an on/off frequency for each of the switches. The switch control circuit 106 can also include a delay mechanism (e.g., DELAY as shown) to prevent each switch from turning on at the same time. One of the resonant tank circuits including the transformer 108, the resonant capacitor Cr and the resonant inductor Lr operates to generate a sine wave by the square wave generated by the free switchers Q1 and Q2 shape. The resonant frequency (f0) of system 100 is typically controlled by resonant capacitor Cr and resonant inductor Lr. In general, the gain of the DC/DC converter system 100 can be controlled by a comparison of the switching frequency (fs) of the switches Q1 and Q2 with the resonant frequency (f0). In some embodiments, the gain of system 100 is larger at fs < f0 and smaller at fs > f0. Of course, in other embodiments, the frequency converter circuit can include, for example, a full bridge frequency converter topology, a push-pull frequency converter topology, a class C frequency converter topology, and the like.

The synchronous rectifier circuit of the secondary side stage 104 includes rectifier switches SR1 and SR2 that are electrically coupled to the secondary side of the transformer 108 and configured to function as one of the sinusoidal signals at the secondary side of the transformer 108. Full wave rectifier operation. The SR switch can include a MOSFET device that is biased in a source-to-drain direction (as shown) with an inscribed diode. The conduction state of the switch SR2 can be controlled by the synchronous rectifier (SR) control circuit 110, and the conduction state of the switch SR1 can be controlled by the SR control circuit 112. In general, SR control circuits 110 and 112 are configured to generate gate control signals to control the conduction of SR2 and SR1, respectively, to minimize the in-line contact time and to reduce or eliminate the negative across the SR switch. Current, as explained below.

FIG. 2 illustrates a synchronous rectifier control circuit 110 in accordance with an embodiment of the present invention. It should be understood that, initially, since control circuits 110 and 112 are generally configured to generate complementary gate control signals, operation of circuit 110 is similar to operation of 112, except that circuit 112 is based on one of the inverted clocks as shown in FIG. Except for signal (SR_CLK2) timing. Therefore, the following description of control circuit 110 applies equally to circuit 112, but the gate control signal generated by circuit 110 The number is different from the gate control signal of circuit 112 by approximately 180 degrees. The input to the SR control circuit 110 includes the drain voltage (VDS_SR) of the SR switch and the clock signal (OSC) from the oscillator. The SR control circuit 110 includes a zero crossing approximation circuit 208 that is configured to generate an SR turn-on signal 209 that indicates one of the turn-on states of the SR switch. When the SR switch is conducting, the voltage drop across the switch is near zero volts, and when the SR switch is open, the voltage drop across the SR switch is high (usually greater than the inscribed diode across the SR switch) 218 voltage drop). The SR control circuit 110 also includes a sample and hold circuit 210 that is configured to sample the on time (indicated by signal 209). To prevent current zero crossing through the SR switch, the sample and hold circuit is also configured to generate a proportional SR turn-on signal 211 (SR_CND_P). Signal 211 is generated as a fraction of signal 209, which may be, for example, 90% of the on-time indicated by signal 209.

The SR control circuit 110 also includes a delay control circuit 212 that is configured to add or subtract a predetermined delay time to the falling edge of the signal 211 to produce a predicted gate control signal 213 (VPRD). Delay control circuit 212 utilizes a clock signal and a high detect signal (generated by circuit 208 and generally indicating when the gate voltage of the SR switch is high). A predicted gate control signal 213 is generated based on the on-time of the SR switch in a previous conduction cycle. Therefore, if the on-time of the SR switch in the current switch cycle is too long (so that the current through the switch crosses zero), the delay control circuit 212 can reduce the delay time of the signal 213 such that the SR switch is under The conduction time in one cycle is shortened. Conversely, if the SR switch is too short in the current switch cycle (so that the current through the switch is zero The delay control circuit 212 can add more delay to the signal 213 to make the SR switch's turn-on time longer in the next cycle, before there is a dead time in which the SR switch is disconnected.

The sample and hold circuit 210 and the delay control circuit 212 ensure that the current through the SR switch does not cross zero, but permits the current to complete its resonant cycle determined by f0. Thus, when switching in the frequency converter stage 102 occurs at f0 or below f0, the delay control circuit 212 can be configured to add (or subtract) a delay to the SR turn-on signal 209 to achieve the SR switch. Switching at or near the zero crossing of the current through the switch. When switching in the inverter stage occurs above f0, the inverter switch (Q1 or Q2) will open before the corresponding SR switch (this means that the resonant period in the resonant tank is reduced or truncated). Thus, in some embodiments, the SR control circuit 110 can also include an allowable switching window (ASW) circuit 214 that allows the switching window (ASW) circuit 214 to be configured to be based on the disconnection of the frequency converter level switch (by the clock) An ASW signal 215 is generated by the time difference between the signal OSC setting and the end of the SR on time. Thus, the ASW circuit 214 is configured to receive the clock signal (OSC) and the SR turn-on signal 209 from the primary stage 102 and determine the time difference between the end of the clock signal and the end of the SR turn-on signal 209. An ASW signal 215 is generated that includes a delay time applied to the clock signal such that the ASW signal 215 approximates the end of the SR turn-on signal 209. Similar to the predicted gate drive signal 213, the ASW signal 215 can be generated using a repetitive technique, for example, the ASW signal 215 can be based on the on-time of the SR switch in a previous conduction cycle. The SR control circuit 110 can also include a "AND" gate configured to "AND" the ASW signal 215 and the predicted gate drive signal 213 to generate the SR gate drive signal 217. Road 216.

FIG. 3 illustrates a timing diagram 300 of various signals in accordance with an embodiment of the present invention. This timing diagram is generally broken down into two parts: the left side 320 is the nth conduction cycle, and the right side 322 is the (n+1)th conduction cycle. Current waveform 302 depicts the current through the SR switch, which is labeled ISD_SR. Voltage waveform 304 depicts the drain-to-source voltage drop across the SR switch, which is labeled VDS_SR. In the first portion of voltage waveform 304, the switch is closed and thus the voltage drop across the switch is high. When current begins to flow through the SR switch, the inverting diode 218 of the switch begins to conduct and the voltage drop across the switch decreases rapidly. At this time, in order to minimize the time period during which the in-line diode 218 is turned on, it is advantageous to control the SR switch to close the switch and start the conduction through the switch. The total SR on-time waveform 306 closely matches the zero crossing of the current waveform 302 and the voltage waveform 304. The SR on time 306 is measured in the nth cycle 320 and a proportional SR on waveform 308 is generated as one of the SR on time 306 substantial fractions and applied to the next conduction cycle 322 (as indicated by the arrows). In this example, the predicted gate drive waveform 310 is generated to add a delay to the falling edge of the proportional SR turn-on waveform 308 to minimize the dead time between the proportional SR turn-on signal waveform 308 and the actual SR turn-on time 306. Of course, if too much delay is added, the delay can be subtracted from the proportional SR turn-on signal 308 in the next turn-on cycle such that the predicted gate drive waveform 310 substantially matches the SR turn-on time 306. This handler can continue over. The ASW waveform 312 and the gate drive signal waveform 314 are also shown.

FIG. 4A illustrates a sample and hold circuit 210 in accordance with an embodiment of the present invention. With continued reference to FIG. 2, the sample and hold circuit 210 of this embodiment is The SR pass signal 209 is configured to receive the SR turn-on signal 209 and to sample the SR turn-on signal (209) by charging the sampling capacitor CSRT. The proportional SR turn-on 211 is generated as one of the selected values of the SR turn-on signal 209. 4B illustrates a timing diagram 450 of various signals along with the operation of the sample and hold circuit of FIG. 4A. The SR on signal waveform and the proportional SR on signal waveform are respectively shown as 306 and 308. Waveform 452 depicts the voltage ramp (VCRST) of the sampling capacitor CSRT and is also shown to generate a 90% threshold for the proportional SR on signal.

FIG. 5A illustrates a delay control circuit 212 in accordance with an embodiment of the present invention. With continued reference to FIG. 2, the delay control circuit 212 is configured to generate a predicted gate drive signal 213 to add (or subtract) a selected delay time period to the end (falling edge) of the proportional SR turn-on signal 211 based on the SR turn-on ON time, As indicated by the high detection signal. The delay control circuit 212 of this embodiment includes a 4-bit weighted counter configured to impart a selectable delay time to the end of the proportional SR turn-on signal 211. Figure 5B illustrates a timing diagram of various signals along with the operation of the delay control circuit of Figure 5A. The first set of timing diagrams 560 illustrates instances where the dead time (TD) is greater than a programmed or predetermined dead time (TPD) and thus a delay is added. For example, waveform 308 depicts a scaled SR turn-on signal, and waveform 310 depicts a predicted gate drive signal that includes a delay added to minimize dead time. The second set of timing diagrams 562 illustrates instances where the dead time (TD) is less than a programmed or predetermined dead time (TPD) and thus the delay is subtracted. For example, waveform 308 depicts a proportional SR turn-on signal, and waveform 310 depicts a small delay (in the n+1th cycle, compared to the nth loop) to minimize to ensure that the SR switch is not worn. Predictive gate drive that occurs after the zero crossing of the current of the SR switch signal.

FIG. 6A illustrates an ASW circuit 214 in accordance with an embodiment of the present invention. In this embodiment, the ASW circuit 214 includes a delay selector circuit 212 that is configured to control the timing of the gate control signal 217 when the switch in the frequency converter stage 202 is operating above the resonant frequency of the resonant tank circuit. With continued reference to FIG. 2, the ASW circuit 214 is configured to generate an ASW signal 215 by measuring the time difference between the turn-off of the frequency converter switch (set by the clock signal OSC) and the end of the SR turn-on time and The end of the clock signal (falling edge) is added with a number of selectable delay time units to produce the ASW signal 215 in the presence of any difference. In this example, the delay selector circuit includes a plurality of selectable delay circuits, each of which can add a predetermined amount of delay to the falling edge of the clock signal. The delay time can be added so that additional delay can be generated by enabling more delay circuits and less delay can be generated by enabling fewer delay circuits. Each delay circuit can be configured to generate the same delay time or a different (eg, weighted) delay time.

FIG. 6B illustrates a timing diagram 650 of various signals along with the operation of the delay selector circuit of FIG. 6A. The current waveform 302 illustrates the timing of the frequency converter stage switch (indicated by the clock waveform 652) ending before the resonance period, ie, fs > f0. The portion of the current waveform 302 shown at the end of the signal (between the end of the waveform 652 and the end of the waveform 306) indicates a substantially linear current waveform. Waveform 654 illustrates one of the first delay time periods produced by one of the delay circuits. Similarly, waveforms 656 and 658 illustrate the delay time periods produced by the second and third circuits, respectively. Note that the addition of the delay time period of waveform 658 will cause ASW signal 312 to be in the current waveform. After the end. Thus, in this example, to prevent zero crossing of the current through the SR switch, delay time periods 654 and 656 can be added to the clock signal 652 to generate the ASW signal 312.

According to one aspect, the invention features a resonant converter system. The resonant converter system includes a first stage, a transformer, and a second stage. The first stage includes a frequency converter circuit and a resonant tank circuit configured to generate an AC signal from a DC input signal. The transformer is configured to transform the AC signal. The second stage includes a synchronous rectifier (SR) circuit including a plurality of SR switches each having an inscribed diode. The SR control circuit is configured to generate a gate control signal to control the turn-on state of the SR switch to minimize in-line diode turn-on time and to reduce or eliminate negative current across one of the SR switchers.

According to another aspect, the invention features a method comprising: converting a DC input signal to an AC-converted signal having a first voltage; and transforming the AC-converted signal into a second And converting one of the voltages to a DC output voltage signal, wherein the rectifying comprises controlling one of a plurality of synchronous rectifier (SR) switches each having an inscribed diode The conduction state is such as to minimize the in-line contact time and reduce or eliminate a negative current across one of the SR switches.

According to yet another aspect, the invention features a method of controlling a resonant converter. The method includes controlling an on state of a plurality of synchronous rectifier (SR) switches of a rectifier portion of the resonant converter, each of the SR switches having an inscribed diode, wherein each switching Controlled by The turn-on is turned on when the inline diode associated with the switch begins to conduct, and each switch is controlled to open when the current through the switch approaches a zero crossing.

The term "switch" can be embodied as MOSFET switches (eg, individual NMOS and PMOS components), BJT switches, and/or other switching circuits known in the art. In addition, as used in any embodiment herein, the term "circuitry or circuit" may include, for example, hardwired circuitry, programmable circuitry, state, in a single form or in any combination. The circuit and/or the circuitry contained in a larger system (for example, an element that can be included in an integrated circuit).

The terms and expressions used herein are used to describe and not to limit the terms, and the use of such terms and expressions is not intended to exclude any equivalents of the features shown and described. It will be appreciated that various modifications may be made within the scope of the patent application. Therefore, the scope of the patent application is intended to cover all such equivalents. Various features, aspects, and embodiments have been set forth herein. The features, aspects, and embodiments are susceptible to being combined with each other and are susceptible to variations and modifications, as will be understood by those skilled in the art. Accordingly, the invention is considered to be inclusive of such combinations, variations and modifications.

100‧‧‧Resonant Converter System / Converter System / System / DC / DC Converter System

102‧‧‧Primary/primary/inverter/primary

104‧‧‧secondary level

106‧‧‧ gate control circuit / switcher control circuit

108‧‧‧Transformers

110‧‧‧Synchronous Rectifier (SR) Control Circuit / Control Circuit / Circuit

112‧‧‧Synchronous Rectifier (SR) Control Circuit / Control Circuit / Circuit

208‧‧‧zero crossing approximation circuit/circuit

209‧‧‧Synchronous rectifier turn-on signal/signal

210‧‧‧Sampling and holding circuit

211‧‧‧Synchronous rectifier turn-on signal/signal

212‧‧‧ Delay Control Circuit / Delay Selector Circuit

213‧‧‧Predicted gate control signals

214‧‧‧allowable switching window (ASW) circuit

215‧‧‧allowable switching window signal

216‧‧‧"and" gate circuit

217‧‧‧Synchronous rectifier gate drive signal / gate control signal

218‧‧‧Inline diode

300‧‧‧ Timing diagram

302‧‧‧ Current waveform

304‧‧‧Voltage waveform

306‧‧‧Synchronous rectifier on-time

308‧‧‧Synchronous rectifier turn-on waveform

310‧‧‧Predicted gate drive waveform/waveform

312‧‧‧ Allowable switching window waveform/allowable switching window signal

314‧‧‧ brake drive signal waveform

320‧‧‧nth conduction cycle/nth cycle

322‧‧‧(n+1) conduction cycle/conduction cycle

450‧‧‧ Timing diagram

452‧‧‧ waveform

560‧‧‧First set of timing diagrams

562‧‧‧Second set of timing diagrams

650‧‧‧ Timing diagram

652‧‧‧clock waveform/waveform/clock signal

654‧‧‧ Waveform/Delay Time Period

656‧‧‧ Waveform/Delay Time Period

658‧‧‧ waveform

Cr‧‧‧Resonance Capacitor

C _SRT ‧‧‧Sampling capacitor

I _{SD_SR ‧‧‧current} through the synchronous rectifier switch

Lr‧‧‧Resonance Inductors

Q1‧‧‧Switcher/Inverter Switcher

Q2‧‧‧Switch/Inverter Switcher

SR_CLK2‧‧‧Inverted clock signal

SR_CND_P‧‧‧Synchronous rectifier turn-on signal

SR1‧‧‧Rectifier Switcher/Switcher

SR2‧‧‧Rectifier Switcher/Switcher

T _D ‧‧‧No-load time

T _PD ‧‧‧ scheduled dead time

V _CRST ‧‧‧ voltage ramp up

V _{DS_SR} ‧‧‧汲polar voltage / drain to source voltage drop

VIN‧‧‧ input DC voltage

VOUT‧‧‧ output DC voltage

V _PRD ‧‧‧Predicted gate control signal

1 illustrates a resonant converter system in accordance with various embodiments of the present invention; and FIG. 2 illustrates a synchronous rectifier control circuit in accordance with an embodiment of the present invention; 3 illustrates a timing diagram of various signals in accordance with an embodiment of the present invention; FIG. 4A illustrates a sample and hold circuit in accordance with an embodiment of the present invention; and FIG. 4B illustrates a sample and hold circuit in conjunction with FIG. 4A. A timing diagram of the various signals that operate together. Figure 5A illustrates a delay control circuit in accordance with an embodiment of the present invention; Figure 5B illustrates a timing diagram of various signals along with the operation of the delay control circuit of Figure 5A. 6A illustrates a delay selector circuit in accordance with an embodiment of the present invention; and FIG. 6B illustrates a timing diagram of various signals along with the operation of the delay selector circuit of FIG. 6A.

100‧‧‧Resonant Converter System / Converter System / System / DC / DC Converter System

102‧‧‧Primary/primary/inverter/primary

104‧‧‧secondary level

106‧‧‧ gate control circuit / switcher control circuit

108‧‧‧Transformers

110‧‧‧Synchronous Rectifier (SR) Control Circuit / Control Circuit / Circuit

112‧‧‧Synchronous Rectifier (SR) Control Circuit / Control Circuit / Circuit

Cr‧‧‧Resonance Capacitor

Lr‧‧‧Resonance Inductors

Q1‧‧‧Switcher/Inverter Switcher

Q2‧‧‧Switch/Inverter Switcher

SR_CLK2‧‧‧Inverted clock signal

SR1‧‧‧Rectifier Switcher/Switcher

SR2‧‧‧Rectifier Switcher/Switcher

VIN‧‧‧ input DC voltage

VOUT‧‧‧ output DC voltage

Claims (11)

A resonant converter system comprising: a first stage comprising a frequency converter circuit configured to generate an AC signal from a DC input signal and a resonant tank circuit; a transformer configured to The AC signal is transformed; a second stage includes a synchronous rectifier (SR) circuit, the synchronous rectifier (SR) circuit includes: a plurality of SR switches, and each switch includes an inscribed diode; An SR control circuit configured to generate a gate control signal to control an on state of the SR switches to minimize an in-line diode turn-on time and to reduce or eliminate one of the SR switches a negative current, wherein the SR control circuit includes: a zero crossing approximation circuit configured to generate an SR turn-on signal indicating one of the turn-on states of the SR switch; and an allowable switching window (ASW) A circuit configured to generate an ASW signal based on a time difference between a turn-off of one of the first stages of the switch and an end of the SR turn-on signal. The system of claim 1, further comprising a sample and hold circuit configured to sample an on time of the SR turn-on signal and further configured to generate a ratio proportional to the SR turn-on signal One ratio SR turns on the signal. The system of claim 2, further comprising a delay control circuit configured to add or subtract a predetermined delay time to a falling edge of the proportional SR turn-on signal and further configured to generate a prediction Gate control signal. The system of claim 3, further comprising a "and" gate configured to "AND" the ASW signal and the predicted gate control signal to generate an SR gate drive signal to control the SR The conduction state of the switch. A method for resonant conversion, comprising: converting a DC input signal into an AC-converted signal having a first voltage; and transforming the AC-converted signal into an AC-transformed signal having a second voltage; Rectifying the second AC transformed signal into a DC output voltage signal, wherein the rectifying comprises controlling a conducting state of a plurality of synchronous rectifier (SR) switches each having an inscribed diode to enable the inscribed diode Minimizing on-time and reducing or eliminating a negative current across one of the SR switches; generating a plurality of SR-on signals based on a zero-crossing approximation, each SR-on signal indicating one of the plurality of SR switches a turn-on state; and generating an allowable switching window (ASW) signal based at least in part on a time difference between one end of one of the clock signals OSC and one of the ends of the SR turn-on signal. The method of claim 5, further comprising generating a ratio of the SR turn-on signal proportional to the SR turn-on signal. The method of claim 6, further comprising adding or subtracting a falling delay edge to one of the proportional SR turn-on signals to generate a prediction Gate control signal. The method of claim 7, wherein the DC input signal is converted to the AC converted signal using a frequency converter circuit and a resonant tank circuit, the method further comprising generating an SR gate drive signal to control the conduction state of the SR switch, Wherein when the switching frequency (fs) of the inverter circuit is at or below the resonance frequency (f0), the SR gate driving signal is based on the predicted gate control signal, and wherein the SR gate driving signal system is when fs is higher than f0 Based on the ASW signal. A method of controlling a resonant converter, the method comprising: controlling an on state of a plurality of synchronous rectifier (SR) switches of a rectifier portion of the resonant converter, each of the SR switches having an internal Connected to a diode, wherein each switch is controlled to conduct when the inline diode associated with the switch begins to conduct, and each switch is controlled to approach a current through the switch Disconnecting at zero crossing; and repeatedly adding or delaying a signal indicative of a predicted on-time of one of the SR switches to generate a predicted gate drive signal, wherein the predicted gate drive signal One of the falling edges of each substantially matches the zero crossing of the current through an associated SR switch. The method of claim 9, wherein the predictive gate drive signal is used to control the SR switch when the switching frequency (fs) of one of the resonant converters is at or below a resonant frequency (f0) The conduction state. The method of claim 10, further comprising controlling the conduction state of the SR switches based on a clock signal when fs is higher than f0.