TWI538109B - Integrated circuit and method for fabricating and operating the same - Google Patents

Description

Integrated circuit and its making and operating method 【0001】

The present invention relates to a non-volatile memory device. In particular, there is a stereo vertical gate memory array (3D).

【0002】

The NAND memory array uses a high voltage switching transistor to isolate the erase voltage from the array and from the sense amplifier. Although the read and write uses a relatively low voltage, the erase operation couples a high-intensity voltage to the array. High voltage switching transistors are therefore used to electrically decouple the array from the sense amplifier to prevent junction breakdown.

[0003]

In general, in the erase operation of a 2D NAND memory array, the potential of the PWI region having the highest p-type doping concentration in the triple-well increases. Typical planar NAND memory components are arranged in such a way that four sets of high voltage electrical switching field effect transistors (MOSFETs) are placed outside the PWI region to electrically separate the array from the erase voltage.

[0004]

In another arrangement of planar NAND memory arrays, the memory array and the four switching field effect transistors share the PWI area to prevent large voltage differences and allow low voltage design rules to be applied to the four switching field effects. Crystal. The latest arrangement is to add an additional high-voltage switch field effect transistor outside the PWI area and reduce the number of high-voltage switch field effect transistors from four to one. Therefore, although an additional transistor is added, the overall area is made smaller.

[0005]

The stereo NAND memory structure also benefits from the configuration of the high voltage switching transistor to protect the sensing circuit from high-intensity erase voltage. However, stereo NAND memory may lack PWI regions that are used in planar NAND memory structures to provide high voltage switching circuitry to reduce area consumption.

[0006]

Therefore, in the stereo NAND memory structure, the high voltage switching transistor circuit consumes a large amount of area. In an example of a memory array with eight bit lines, each planar line is configured with two planar switching transistors, and 16 planar switching transistors are required to electrically couple the bit lines to the erase voltage line. Or write to the read voltage line.

【0007】

Therefore, there is a need to reduce the area consumed by the switching transistor of the stereo NAND memory array.

[0008]

The different embodiments disclosed in the present technology reduce the area consumed by the switching transistor of a stereo NAND memory array. The stereo NAND memory array has a three-dimensional voltage switching transistor having a lower aggregate area than a planar voltage switching transistor (eg, a transistor formed in a substrate). . In some embodiments, both the stereo NAND memory array and the stereo voltage switching transistor use a vertical gate memory structure.

【0009】

In one aspect of the present technology, the integrated circuit includes a stereo NAND memory array having a plurality of memory transistors, and a plurality of bit lines, wherein different bit lines are coupled to different parts of the stereo NAND memory array. And a plurality of pairs of transistors in a stack of semiconductor layers. The different layers in the semiconductor stack include different pairs of transistors in a plurality of pairs of transistors. Each of the plurality of transistor pairs includes a first transistor and a second transistor, and both have first, second, and third source/deuterium extreme points. Wherein the first transistor comprises first and third source/deuterium extreme points; the second transistor comprises second and third source/deuterium extreme points. The first source/deuterium pole is electrically coupled to an erase voltage line. The second source/deuterium pole is electrically coupled to one of a plurality of write/read voltage lines. The third source/汲 pole is electrically coupled to one of the plurality of bit lines.

[0010]

In some embodiments of the present technology, the first gate controls all of the first transistors in the plurality of transistor pairs; and the second gate controls all of the second transistors in the plurality of transistor pairs.

[0011]

In some embodiments of the present technology, the first gate controls whether a plurality of bit lines are coupled to a first source/汲 terminal of the plurality of transistor pairs; and the second gate controls the plurality of bits Whether the line is coupled to a second source/汲 terminal of the plurality of transistor pairs.

[0012]

In some embodiments of the present technology, the stereo NAND memory array includes a plurality of stacks of semiconductor strips disposed as transistor channels of different memory transistors in the stereo NAND memory array. The semiconductor stack includes: a first semiconductor strip stack structure configured to serve as a transistor channel of a plurality of different transistor pairs; and a second semiconductor strip stack structure configured to be a plurality of electrodes The crystal pair has a different transistor channel of the second transistor.

[0013]

In some embodiments of the present technology, a plurality of semiconductor strips in a first semiconductor strip stack structure, a plurality of semiconductor strips in a second semiconductor strip stack structure, and a plurality of conductor strip stack structures A plurality of semiconductor strips share a plurality of plane positions.

[0014]

In some embodiments of the present technology, different bit lines of the plurality of bit lines are electrically coupled to different planar positions of the stereo NAND memory array.

[0015]

Some embodiments of the present technology further include circuitry for generating a first set of voltages for the erase voltage line and a second set of voltages for the write/read voltage lines.

[0016]

In some embodiments of the present technology, the plurality of semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the bit lines adjacent to the plurality of bit lines.

[0017]

In some embodiments of the present technology, the plurality of semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the bit lines of the plurality of bit lines that are not adjacent thereto.

[0018]

Some embodiments of the present technology further include circuitry for performing the following actions:

[0019]

(i) opening a plurality of first transistors; and turning off the plurality of second transistors;

[0020]

(ii) opening a plurality of second transistors; and turning off the plurality of first transistors.

[0021]

Another aspect of the present technology is a method of operating a plurality of bit lines. The bit lines are electrically coupled to the stereo NAND memory array including the plurality of memory transistors, wherein the different bit lines are electrically coupled to different portions of the stereo NAND memory array, and the method includes

[0022]

The bit line is electrically coupled to one of the following:

[0023]

(i) a first set of voltages coupled by a first plurality of transistors of at least one first memory operating pattern in the stereo NAND memory array, wherein the first plurality of transistors has a first a semiconductor strip stack structure;

[0024]

(ii) a second set of voltages coupled by a second plurality of transistors of at least one second memory operating pattern in the stereo NAND memory array, wherein the second plurality of transistors has a first The second semiconductor strip stack structure; and the second memory operation type is different from the first memory operation type.

[0025]

In some embodiments of the present technology, the semiconductor strips in the first semiconductor strip stack structure are disposed as transistor channels of different transistors of the first plurality of transistors; and located in the second semiconductor strip A strip of semiconductor strips in a stacked structure is provided as a transistor channel of a different transistor of the second plurality of transistors; and the array of stereo NAND memories includes a plurality of stacked layers of semiconductor strips, which are arranged as Transistor channels of different memory transistors in a stereo NAND memory array. In some embodiments of the present technology, a plurality of semiconductor strips in a first semiconductor strip stack, a plurality of semiconductor strips in a second semiconductor strip stack structure, and a plurality of conductor strip stack structures The plurality of semiconductor strips share a plurality of planar positions. Among them, different plane positions are set corresponding to different transistor channels.

[0026]

In some embodiments of the present technology, the first memory operation type includes erasing; and the second memory operation type includes at least one of writing and reading. In some embodiments of the present technology, the first memory operation type includes erasing; and the second memory operation type includes writing and reading.

[0027]

In some embodiments of the present technology, different bit lines of the plurality of bit lines are coupled to different planar positions in the stereo NAND memory array.

[0028]

Some embodiments of the present technology further include circuitry for generating a first set of voltages suitable for a first memory mode of operation and a second set of voltages suitable for a second memory mode of operation.

[0029]

In some embodiments of the present technology, the plurality of semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the bit lines adjacent thereto in the plurality of bit lines.

[0030]

In some embodiments of the present technology, the plurality of semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the bit lines of the plurality of bit lines that are not adjacent thereto. For example, write and/or read memory operations can be performed by odd or even bit lines/all bit lines.

[0031]

Some embodiments of the present technology further include the following actions performed by circuitry:

[0032]

(i) opening a first plurality of transistors and turning off the second plurality of transistors to couple the first set of voltages to the plurality of bit lines to perform at least the first memory mode;

[0033]

(ii) opening a plurality of second transistors, and turning off the plurality of first transistors, thereby coupling the second set of voltages to the plurality of bit lines to perform at least the second memory operation type.

[0034]

Yet another aspect of the present technology is an integrated circuit comprising:

[0035]

A stereo NAND memory array having a plurality of memory transistors and a plurality of bit lines, wherein different bit lines of the plurality of bit lines are electrically coupled to different parts of the stereo NAND memory array, and are located at the first a plurality of first transistors in the semiconductor strip stack structure and a plurality of second transistors in the second semiconductor strip stack structure. A plurality of bit lines are switchably coupled to the only one of the complex array voltages. The complex array voltage includes at least:

[0036]

(i) a first set of voltages coupled by a first plurality of transistors of at least one first memory mode of operation in the stereo NAND memory array;

[0037]

(ii) a second set of voltages coupled by a second plurality of transistors of at least one second memory operating pattern in the stereo NAND memory array, and the second memory operating mode and the first The memory operation type is different.

[0038]

The other aspect of the technology is the method of making this integrated circuit.

[0039]

The above-described embodiments and other objects, features and advantages of the present invention will become more apparent and understood.

【0159】

20‧‧‧Stack structure
22, 22.0-22.7‧‧‧ dielectric layer
24, 24.0-24.7‧‧‧ conductive layer
26‧‧‧Dielectric substrate
28‧‧‧etch stop layer
30‧‧‧hard mask
32, 32.0-32.7‧‧‧ contact opening
38‧‧‧Open etching zone
40‧‧‧Closed curtain
52‧‧‧First photoresist mask
54‧‧‧second photoresist mask
56‧‧‧Second photoresist mask
100‧‧‧Three-dimensional NAND memory array
112, 113, 114, 115‧‧‧ semiconductor circuits
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A‧‧‧ bit line contact pads
109, 119‧‧‧ tandem selection gate structure
120‧‧‧Global bit line
125-1...125-N‧‧‧ character line
126, 127‧‧‧ Grounding selection line
130, 160-167‧‧‧ voltage switch transistor
132‧‧‧Read voltage line
134‧‧‧wipe/precharge/shadow voltage line
140, 146, 148‧‧‧ conductive plugs
142‧‧‧First transistor gate
144‧‧‧Second transistor gate
150, 152, 154‧‧‧ source/bungee
230‧‧‧Vertical gate voltage switching transistor
232‧‧‧The whole bit line is padded
234‧‧‧First set of vertical gate voltage switching transistors
236‧‧‧Write and read voltage lines on the pad
238‧‧‧Second set of vertical gate voltage switching transistors
240, 265‧‧‧ erasing/pre-charging/shading voltage line falling pad
244‧‧‧First odd array vertical gate voltage switching transistor
245‧‧‧First even array vertical gate voltage switching transistor
246‧‧‧ odd write and read voltage lines fall on the mat
247‧‧‧ Even write and read voltage line even pads
248‧‧‧Second odd array vertical gate voltage switching transistor
249‧‧‧Second even array vertical gate voltage switch
250‧‧‧odd erase/precharge/shadow voltage line pad
251‧‧‧ even erase/precharge/shadow voltage line pad
252‧‧‧odd write and read voltage lines
253, 255 even erase / pre-charge / shield voltage line
254‧‧‧odd erase/precharge/mask voltage erase/precharge/shadow voltage line
BIAS_SEL 262, BIAS_SEL 255, BIAS_SEL 272, BIAS_SEL 273, BIAS_SEL 274, BIAS_SEL 275, BIAS_SEL 310, BIAS_SEL 320‧‧‧ voltage lines
312, 314, 322, 324‧‧‧ transistors
322‧‧‧Second transistor
350, 351‧‧ ‧ sense amplifier
BL_BIAS 340‧‧‧voltage line
300, 301, 330, 459, BL1-BL8‧‧‧ bit line
458‧‧‧plane decoder
460‧‧‧Three-dimensional NAND flash memory array
461‧‧ ‧ row decoder
462‧‧‧ character line
463‧‧ ‧ page buffer
464‧‧‧Sequence selection line
465‧‧ ‧ busbar
466‧‧‧ Column decoder data out/input structure
468‧‧‧ bias voltage
469‧‧‧ state machine
471‧‧‧ data input line
474‧‧‧Other circuits
472‧‧‧ data output line
475‧‧‧ integrated circuit
BLi1, BLi3, BLi5, BLi7 ‧‧‧Read voltage lines
P1-P8‧‧‧ semiconductor strip
ML1, ML2, ML3‧‧‧ metal layer

[0040]

1 is a block diagram showing an integrated circuit of a stereo NAND memory array and a voltage switching transistor located in a substrate.
FIG. 2 is another block diagram showing the integrated circuit of FIG. 1 showing the voltage switch transistor in the substrate as having a relatively large size.
FIG. 3 is a perspective view showing a structure of a stereoscopic vertical gate NAND flash memory stereo memory array, which can be used as an embodiment of the stereo memory array of FIG. 1.
4 is a perspective view showing a pair of voltage switch transistors which can be applied to the voltage switch transistor in FIG. 1. FIG. 5 is a diagram showing a plurality of pairs of voltages which can be applied to the substrate in FIG. A perspective view of the structure of the switching transistor.
Figure 6 is a block diagram showing an integrated circuit having a stereo NAND memory array and a vertical gate voltage switching transistor.
Figure 7 is a block diagram showing another block diagram of the integrated circuit of Figure 6, which depicts the vertical gate voltage switching transistor as having a relatively small size.
Fig. 8 is a more detailed block diagram showing the integrated circuit of Fig. 6, and further shows a plurality of sets of vertical gate voltage switching transistors and a plurality of sets of landing pads.
Fig. 9 is a perspective view showing the structure of an embodiment of the integrated circuit of Fig. 8.
Fig. 10 is a perspective view showing the structure of the bit line and the bit line landing pad in the integrated circuit of Fig. 9.
Figure 11 is a perspective view showing the structure of a first group of vertical gate voltage switching transistors in the integrated circuit of Figure 9.
Fig. 12 is a perspective view showing the structure of the write and read voltage lines and the write and read voltage line drop pads of the integrated circuit in Fig. 9.
Figure 13 is a perspective view showing the structure of a second group of vertical gate voltage switching transistors in the integrated circuit of Figure 9.
Fig. 14 is a perspective view showing the structure of the erase voltage line and the erase voltage line drop pad of the integrated circuit in Fig. 9.
Figure 15 is a block diagram showing another detailed block diagram of the integrated circuit of Figure 6, showing that it is accessed by odd or even bit lines instead of all bit lines as shown in Figure 8. Access.
Figure 16 is a perspective view showing the structure of the write and read voltage lines and the write and read voltage line drop pads of the integrated circuit in Fig. 15, which are accessed by even bit lines. Instead of accessing through all bit lines as shown in Figure 12.
Figure 17 is a perspective view showing the structure of the write and read voltage lines and the writing and reading voltage line landing pads of the integrated circuit in Fig. 15, which are accessed by odd bit lines. Instead of accessing through all bit lines as shown in Figure 12.
Figure 18 is a perspective view showing the erase voltage line of the integrated circuit in Fig. 15 and the structure of the erase voltage line drop pad, which is accessed by the even bit line instead of the 14th The figure shows access through all bit lines.
Figure 19 is a perspective view showing the erase voltage line of the integrated circuit in Fig. 15 and the structure of the erase voltage line drop pad, which are accessed by odd bit lines instead of the 14th The figure shows access through all bit lines.
Figure 20 is a perspective view showing the structure of the even-numbered landing pads of the integrated circuit in Figure 15 in place of the even-numbered landing pads shown in Figures 16 and 18.
Fig. 21 is a perspective view showing the structure of the odd-numbered landing pads of the integrated circuit in Fig. 15 for replacing the odd-numbered landing pads shown in Figs. 17 and 19.
Figure 22 is a block diagram showing the routing conductive lines of one of the integrated circuits accessed in all of the bit lines in Figure 8.
Fig. 23 is a block diagram showing the wiring of another wiring layer in the integrated circuit which is accessed by all the bit lines in Fig. 8.
Fig. 24 is a block diagram showing the wiring of the wiring layer of the integrated circuit which is accessed by the even and odd bit lines in Fig. 15.
Fig. 25 is a block diagram showing the wiring of another wiring layer of the integrated circuit which is accessed by the even and odd bit lines in Fig. 15.
Figure 26 is a simplified circuit diagram of a pair of vertical gate switch transistors that can be used for write or read operations.
Figure 27 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for writing or reading operations in an integrated circuit that is accessed in all bit lines in Figure 8.
Figure 28 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for write or read operations in an integrated circuit accessed in even and odd bit lines in Figure 15.
Figure 29 is a simplified circuit diagram of a pair of vertical gate switch transistors that can be used to perform an erase operation.
Figure 30 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for erase operations in an integrated circuit that is accessed in all bit lines in Figure 8.
Figure 31 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for erase operations in an integrated circuit accessed in even and odd bit lines in Figure 15.
Figure 32 is a simplified circuit diagram showing an integrated circuit having a vertical gate switching transistor.
Figure 33 is a cross-sectional view showing the structure of different mask combinations that can produce landing zones of different depths.

[0041]

The following description will refer to specific structural embodiments and methods. It is to be understood that the invention is not limited to the specific embodiments and methods, and the invention may be practiced with other features, elements, methods and embodiments. The disclosure of the preferred embodiments is only for the purpose of clearly illustrating the technical features of the present invention and is not intended to limit the scope of the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. In the different embodiments, the same elements will be denoted by the same element symbols.

[0042]

1 is a block diagram showing an integrated circuit of a stereo NAND memory array and a voltage switching transistor located in a substrate.

[0043]

The stereo NAND memory array 100 is coupled to the voltage switching transistor 130 located in the substrate by a global bit line 120. Depending on the switching mode of the transistor 130, the global bit line 120 is coupled to the write and read voltage lines 132 for carrying the write and read voltages, or to the erase voltage for carrying the erase voltage. Line 134.

[0044]

FIG. 2 is another block diagram showing the integrated circuit of FIG. 1 showing the voltage switch transistor in the substrate as having a relatively large size.

[0045]

The voltage switch transistor 130 located in the substrate is depicted as having an X-dimension dimension corresponding to the dimensions of the stereo NAND memory array 100 in the X-axis direction. The voltage switching transistor 130 located in the substrate is depicted as having an aggregate Y-dimension of about 150 micrometers (μm) in the Y-axis direction.

[0046]

FIG. 3 is a perspective view showing a structure of a stereoscopic vertical gate NAND flash memory stereo memory array, which can be used as an embodiment of the stereo memory array of FIG. 1.

[0047]

This component includes stacks of active lines in the active layer of the array and is interleaved with the insulating lines. The insulating material is removed in the drawing to expose other structures. For example, insulated lines between semiconductor lines of the same stacked structure, and insulated lines between different semiconductor line stack structures are removed.

[0048]

In the present embodiment, the multilayer array is formed on an insulating layer and includes a plurality of word lines 125-1, ..., 125-N conformal to the plurality of stacked structures. The plurality of stacked structures includes a plurality of semiconductor lines 112, 113, 114, and 115 on a plurality of planes. The semiconductor lines on the same planar layer are electrically coupled to each other by bit line contact pads (eg, bit line contact pads 102B).

[0049]

The bit line contact pads 112A, 113A, 114A, and 115A at the proximal end of the pattern are broken by semiconductor lines, such as semiconductor lines 112, 113, 114, and 115. As shown, the bit line contact pads 112A, 113A, 114A, and 115A are electrically connected to different bit lines located in the upper patterned metal layer (eg, ML3) by an interlayer contact and via a high voltage. A switching transistor is coupled to the decoding circuit to select a planar layer in the array. These bit line contact pads 112A, 113A, 114A, and 115A may be formed on the stepped substrate structure. And it is patterned while defining a plurality of stacked structures.

[0050]

The bit line contact pads 102B, 103B, 104B, and 105B at the far end of the pattern are broken by semiconductor lines, such as semiconductor lines 112, 113, 114, and 115. As shown, the bit line contact pads 102B, 103B, 104B, and 105B are electrically connected by interlayer contacts to different bit lines located in the upper patterned metal layer (eg, ML3) and connected via a high voltage switching transistor. To the decoding circuit to select the planar layer in the array. These bit line contact pads 102B, 103B, 104B, and 105B may be formed on the stepped substrate structure. It is patterned while defining a plurality of stacked structures.

[0051]

In this embodiment, each of the semiconductor circuit stack structures is electrically coupled to one of the bit line contact pads 112A, 113A, 114A, and 115A or the bit line contact pads 102B, 103B, 104B, and 105B instead of two. By. The semiconductor line (stack of semiconductor lines) has one of two opposite directions: a bit line end-to-source line end and a source line end-to-bit line end. For example, the semiconductor line stack structures 112, 113, 114, and 115 have a bit line end-to-source line end direction; and the semiconductor line stack structures 102, 103, 104, and 105 have source line end-to-bit lines. The direction of the end.

[0052]

One end of the semiconductor line stack structures 112, 113, 114, and 115 are disconnected by the bit line contact pads 112A, 113A, 114A, and 115A, passing through the series select gate structure 119, the ground select line 126, and the word line (by 125- 1 to 125-N), the ground selection line 127, and the other end is disconnected by the source line 128. The semiconductor line stack structures 112, 113, 114, and 115 do not touch the bit line contact pads 102B, 103B, 104B, and 105B.

[0053]

One end of the semiconductor line stack structures 102, 103, 104, and 105 are disconnected by the bit line contact pads 102B, 103B, 104B, and 105B, passing through the series select gate structure 109, the ground select line 127, and the word line (by 125- 1 to 125-N), ground selection line 126, and the other end is disconnected by the source line (masked by other portions of the figure). The semiconductor line stack structures 102, 103, 104, and 105 do not touch the bit line contact pads 112A, 113A, 114A, and 115A.

[0054]

A memory material layer is disposed over the interface regions of the surface intersections of the semiconductor lines 12-115 and 102-105 and the word lines 125-1 through 125-N. Ground select lines 126 and 127 are similar to word lines and are conformal to these stacked structures.

[0055]

One end of each semiconductor line stack is disconnected by a bit line contact pad and the other end is disconnected by a source line. For example, one end of the semiconductor line stack structures 112, 113, 114, and 115 is disconnected by the bit line contact pads 112A, 113A, 114A, and 115A, and the other end is disconnected by the source line 128.

[0056]

A bit line and a string selection line are formed on the metal layers ML1, ML2, and ML3. The bit line is coupled to a planar decoder (not shown) located in the peripheral region of the circuit through a high voltage switch transistor. The serial select line is coupled to a serial select line decoder (not shown) located in a peripheral region of the circuit.

[0057]

Ground select lines 126 and 127 can be patterned in the same process portion defining word lines 125-1 through 125-N. A ground selection element is formed over the interface region of the intersection of the surface of the plurality of stacked structures and ground selection lines 126 and 127. Tandem select gate structures 119 and 109 may be patterned in the same process portion defining word lines 125-1 through 125-N. The tandem selection elements are formed on the interface region of the intersection of the surface of the plurality of stacked structures and the tandem selection gate structures 119 and 109. These components are all coupled to a decoding circuit to select a string that is located in a particular stack structure in the array.

[0058]

Figure 4 is a perspective view showing the structure of a pair of voltage switch transistors that can be applied to the substrate in Figure 1.

[0059]

The conductive plug 140 is coupled to a voltage between the global word line and the source/drain 150.

[0060]

The first transistor gate 142 is switchably electrically coupled to the source/drain 150 and the source/drain 152. When the first transistor gate 142 receives a turn-on voltage, the first transistor electrically couples the conductive plug 140 to the conductive plug 146. When the first transistor gate 142 receives a turn-off voltage, the first transistor electrically separates the conductive plug 140 from the conductive plug 146. The conductive plug 146 is electrically coupled to the write and read voltage lines for carrying the write and read voltages.

[0061]

The second transistor gate 144 is switchably electrically coupled to the source/drain 150 and the source/drain 154. When the second transistor gate 144 receives a turn-on voltage, the second transistor electrically couples the conductive plug 140 to the conductive plug 148. When the second transistor gate 144 receives a turn-off voltage, the second transistor electrically separates the conductive plug 140 from the conductive plug 148. The conductive plug 148 is electrically coupled to the erase voltage line for carrying the erase voltage.

[0062]

The first transistor gate 142 and the second transistor gate 144 of the voltage switching transistor located in the substrate are depicted as having a Y-axis dimension of about 1.6 microns. This Y-axis direction dimension corresponds to the size of the gate length. Source/drain 150, source/drain 152, and source/drain 154 are depicted as having a Y-axis dimension of about 2.1 microns.

[0063]

Figure 5 is a perspective view showing the structure of a plurality of pairs of voltage switch transistors that can be applied to the substrate in Figure 1 and located in the substrate.

[0064]

Each pair of voltage switching transistors 160-167 located in the substrate may be an example of a single pair of voltage switching transistors as depicted in FIG. 4, electrically coupled to an erase voltage line, individual bit lines, Individual write and read voltage lines. The case of these multiple pairs of voltage switching transistors highlights the total amount of voltage switching transistors in the substrate that occupy the area of the wafer.

[0065]

Figure 6 is a block diagram showing an integrated circuit having a stereo NAND memory array and a vertical gate voltage switching transistor.

[0066]

The stereo NAND memory array 100 is coupled to the vertical gate voltage switching transistor 230 by a global bit line 120. Depending on the switching mode of the transistor 230, the global bit line 120 is coupled to the write and read voltage lines 132 for carrying write and read voltages, or coupled to carry erase/precharge/shadow (erase/pre-charge/shielding) voltage erase/precharge/shadow voltage line 134. Among them, the pre-charge and mask voltages are also applicable to the write and/or read modes.

[0067]

In some other embodiments, the erase/precharge/shadow voltage lines used to carry the erase/precharge/mask voltage can be used to carry erase/precharge erase/precharge voltage lines for carrying The erase/mask voltage erase/mask voltage line or the erase voltage line used to carry the erase voltage is replaced. In some other embodiments, the pre-charge voltage and/or the occlusion voltage may be carried by another one or more sets of voltage lines.

[0068]

The vertical gate voltage switching transistor 230 separates the erase voltage from other circuitry, such as sense amplifiers.

[0069]

Figure 7 is a block diagram showing another block diagram of the integrated circuit of Figure 6, which depicts the vertical gate voltage switching transistor 230 as having a relatively small size.

[0070]

The vertical gate voltage switching transistor 230 is depicted as having an X-axis dimension corresponding to the dimensions of the stereo NAND memory array 100 in the X-axis direction. The vertical gate voltage switching transistor 230 is depicted as having a total dimension of about 2 microns in the Y-axis direction, substantially less than the Y-axis direction total size of the embodiment of the voltage switching transistor 130 in the substrate of about 150 microns. .

[0071]

The semiconductor stacked structure in the stereo NAND memory array 100 and the semiconductor stacked structure in the vertical gate voltage switching transistor 230 can share process steps such as formation and patterning, so the vertical gate voltage switching transistor 230 does not need to exceed Additional process steps required to fabricate the stereo NAND memory array 100.

[0072]

Fig. 8 is a more detailed block diagram showing the integrated circuit of Fig. 6, and further shows a plurality of sets of vertical gate voltage switching transistors and a plurality of sets of falling pads.

[0073]

The stereo NAND memory array 100 is coupled to the global bit line landing pad 232 by a global bit line 120. The global bit line landing pad 232 is electrically coupled to one of the source/deuterium extremes in both the first set of vertical gate voltage switching transistors 234 and the second set of vertical gate voltage switching transistors 238.

[0074]

The first set of vertical gate voltage switching transistors 234 are switchably electrically coupled to the global bit line landing pads 232 and the write and read voltage line landing pads 236. When the first set of vertical gate voltage switching transistors 234 are turned on, the first set of vertical gate voltage switching transistors 234 electrically couples the global bit line falling pads 232 to the write and read voltage lines. Pad 236; when the first set of vertical gate voltage switching transistors 234 are turned off, the first set of vertical gate voltage switching transistors 234 will drop the global bit line pad 232 and the write and read voltage lines to the pad 236 electrical separation. The read voltage line drop pad 236 is electrically coupled to the write and read voltage lines 132 for carrying write and read voltages.

[0075]

The second set of vertical gate voltage switching transistors 238 are switchably electrically coupled to the global bit line landing pad 232 and the erase/precharge/mask voltage line landing pad 240. When the second set of vertical gate voltage switching transistors 238 are turned on, the second set of vertical gate voltage switching transistors 238 electrically couples the global bit line falling pads 232 to the erase/precharge/shadow voltage lines. Falling pad 240; when the second set of vertical gate voltage switching transistors 238 are turned off, the second set of vertical gate voltage switching transistors 238 will drop the global bit line pad 232 and erase/precharge/mask voltage The wire falls off the pad 240 electrically separated. The erase/precharge/shadow voltage line landing pad 240 is electrically coupled to an erase/precharge/shadow voltage line 134 that is used to carry the erase/precharge/mask voltage.

[0076]

The first set of vertical gate voltage switching transistors 234 and the second set of vertical gate voltage switching transistors 238 separate the erase/precharge/shadow voltage lines 134 used to carry erase/precharge/mask voltages from other circuits. . Other circuits may be, for example, sense amplifiers connected via write and read voltage lines 132.

[0077]

Fig. 9 is a perspective view showing the structure of an embodiment of the integrated circuit of Fig. 8.

[0078]

The stacked blocks in Fig. 9 are respectively shown as simplified perspective views of Figs. 10 to 14. The stereo NAND memory array (not shown) is coupled to the global bit line landing pad 232 by the global bit line 120. The global bit line landing pad 232 is electrically coupled to one of the source/deuterium extremes in both the first set of vertical gate voltage switching transistors 234 and the second set of vertical gate voltage switching transistors 238. The first set of vertical gate voltage switching transistors 234 are switchably electrically coupled to the global bit line landing pads 232 and the write and read voltage line landing pads 236. The write and read voltage line drop pads 236 are electrically coupled to the write and read voltage lines 242 for carrying write and read voltages. The second set of vertical gate voltage switching transistors 238 are switchably electrically coupled to the global bit line landing pad 232 and the erase/precharge/mask voltage line landing pad 240. The erase/precharge/shadow voltage line pad 240 is electrically coupled to the erase/precharge/shadow voltage line 265 used to carry the erase/precharge/mask voltage.

[0079]

In the structure of different blocks, for example in a semiconductor strip stack structure, the insulating layer may be the same as or different from the other layers. Representative insulating materials that may be employed include tantalum oxide, tantalum nitride, niobium oxynitride, niobate or other materials. A low dielectric constant (low-k) material having a dielectric constant less than that of cerium oxide, such as SiCHO _x , can be used. It is also possible to use a high dielectric constant material having a dielectric constant higher than that of cerium oxide, such as hafnium oxide (HfO _x ), hafnium oxynitride (HfON), aluminum oxide (AlO _x ), antimony oxide (RuO _x ). Or titanium oxide (TiO _x ).

[0080]

In the structure of different blocks, for example, the semiconductor layer in the semiconductor strip stack structure may be the same as or different from the other layers. Representative materials that can be included in the semiconductor include doped or undoped polysilicon (useable dopants such as arsenic (As), phosphorus (P), boron (B)), combinations of semiconductor structures, metals Silicides, including titanium telluride (TiSi), cobalt telluride (CoSi), semiconductor oxides, including indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), and combinations of semiconductors and metal tellurides.

[0081]

In the structure of different blocks, for example in the bit line and the conductive plug, the conductor layer may be a metal, a conductive compound or a combination of the following materials, including aluminum (Al), copper (Cu), tungsten (W), Titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride (TiN), tantalum nitride (TaN), tantalum aluminum oxynitride (TaAlN) or other materials. The conductor layer may be a semiconductor layer which is electrically conductive after doping and has no semiconductor characteristics.

[0082]

The number of landing pads, semiconductor strips, and voltage lines can be adjusted based on the capacity of the stereo NAND memory array.

[0083]

Fig. 10 is a perspective view showing the structure of the bit line and the bit line landing pad in the integrated circuit of Fig. 9.

[0084]

The stereo NAND memory array (not shown) is coupled to the global bit line landing pad 232 by a plurality of global bit lines 120. The global bit lines 120 are electrically coupled to a global bit line drop pad 232 by a set of conductive plugs, respectively. For example, each of the bit lines BL1-BL8 is electrically coupled to one of the semiconductor strips P1-P8 located in the global bit line landing pad 232, respectively. Adjacent semiconductor strips P1-P8 in the global bit line landing pads 232 are electrically insulated from one another by intermediate insulating strips.

[0085]

Figure 11 is a perspective view showing the structure of a first group of vertical gate voltage switching transistors in the integrated circuit of Figure 9.

[0086]

The first set of vertical gate voltage switching transistors 234 are switchably electrically coupled to the global bit line landing pads 232 and the write and read voltage line landing pads 236. The first set of vertical gate voltage switching transistors 234 includes semiconductor strips P1-P8 that are electrically insulated from one another by intermediate insulating strips. The first set of vertical gate voltage switching transistors 234 may cover the oxide to isolate the semiconductor strips P1-P8 used as the channel layer from the upper conductive gate material. The oxide may be a multilayer structure such as tantalum oxide / tantalum nitride / tantalum oxide (ONO), tantalum oxide / low high dielectric constant dielectric layer / germanium oxide (O / high-k / O), It can provide high dielectric constant and reduce the doubt of capacitor leakage.

[0087]

Fig. 12 is a perspective view showing the structure of the write and read voltage lines and the write and read voltage line drop pads of the integrated circuit in Fig. 9.

[0088]

The write and read voltage lines 242 are electrically coupled to one of the write and read voltage line drop pads 236 by a set of conductive plugs, respectively. Adjacent semiconductor strips P1-P8 located in the write and read voltage line landing pads 236 are electrically insulated from one another by intermediate insulating strips.

[0089]

When the first set of vertical gate voltage switching transistors 234 receives an open gate voltage, the semiconductor strips P1-P8 located in the global bit line falling pads 232 are electrically coupled to be written and read. The voltage lines fall across the semiconductor strips P1-P8 in pad 236. For example, the semiconductor strip P1 located in the global bit line landing pad 232 is electrically coupled to the semiconductor strip P1 located in the write and read voltage line landing pad 236. The other planar layers of the semiconductor strip are also electrically coupled in this manner.

[0090]

When the first set of vertical gate voltage switching transistors 234 receives a turn-off gate voltage, the semiconductor strips P1-P8 located in the global bit line drop pad 232 and the write and read voltage lines are dropped. The semiconductor strips P1-P8 in pad 236 are electrically separated. For example, the semiconductor strip P located in the global bit line landing pad 232 and the semiconductor strip P1 located in the write and read voltage line landing pad 236 are electrically separated. The other planar layers of the semiconductor strip are also electrically separated in this manner.

[0091]

Figure 13 is a perspective view showing the structure of a second group of vertical gate voltage switching transistors in the integrated circuit of Figure 9.

[0092]

The second set of vertical gate voltage switching transistors 238 are switchably electrically coupled to the global bit line landing pad 232 and the erase/precharge/mask voltage line landing pad 240. In addition, the structure of the second set of vertical gate voltage switching transistors 238 and the first set of vertical gate voltage switching transistors 234 can be similar.

[0093]

Fig. 14 is a perspective view showing the structure of the erase/precharge/shielding voltage line and the erase/precharge/shielding voltage line landing pad of the integrated circuit in Fig. 9.

[0094]

The erase/precharge/shadow voltage line 265 is electrically coupled to one of the erase/precharge/shield voltage line drop pads 240 by a set of conductive plugs, respectively. Adjacent semiconductor strips P1-P8 located in the erase/precharge/shield voltage line landing pad 240 are electrically insulated from one another by intermediate insulating strips.

[0095]

When the second set of vertical gate voltage switching transistors 238 receives an open gate voltage, the semiconductor strips P1-P8 located in the global bit line falling pads 232 are electrically coupled to the erase/precharge. The /shielding voltage line falls on the semiconductor strips P1-P8 in the pad 240. For example, the semiconductor strip P1 located in the global bit line landing pad 232 is electrically coupled to the semiconductor strip P1 located in the erase/precharge/shield voltage line landing pad 240. The other planar layers of the semiconductor strip are also electrically coupled in this manner.

[0096]

When the second set of vertical gate voltage switching transistors 238 receives a turn-off gate voltage, the semiconductor strips P1-P8 located in the global bit line drop pad 232 and the erase/precharge/shadow voltage lines are located. The semiconductor strips P1-P8 in the landing pad 240 are electrically separated. For example, the semiconductor strip P1 located in the global bit line landing pad 232 and the semiconductor strip P1 located in the erase/precharge/shield voltage line landing pad 240 are electrically separated. The other planar layers of the semiconductor strip are also electrically separated in this manner.

[0097]

Figure 15 is a block diagram showing another detailed block diagram of the integrated circuit of Figure 6, showing that it is accessed by odd or even bit lines instead of all bit lines as shown in Figure 8. Access.

[0098]

The stereo NAND memory array 100 is coupled to the global bit line landing pad 232 by a global bit line 120. The global bit line pad 232 is electrically coupled to one of the source/drain electrodes of the four groups of transistors described below. The four sets of transistors are: a first odd array vertical gate voltage switching transistor 244, a first even array vertical gate voltage switching transistor 245, a second odd array vertical gate voltage switching transistor 248 and a second even array Vertical gate voltage switching transistor 249.

[0099]

The first odd array vertical gate voltage switching transistor 244 is switchably electrically coupled to the global bit line landing pad 232 and the odd write and read voltage line landing pads 246. When the first odd array vertical gate voltage switching transistor 244 is turned on, the first odd array vertical gate voltage switching transistor 244 electrically couples the global bit line falling pad 232 to the odd write and read voltages. The line falls on the pad 246. When the first odd array vertical gate voltage switching transistor 244 is turned off, the first odd array vertical gate voltage switching transistor 244 will drop the global bit line pad 232 and write and read the voltage line odd number pad 246 electrical separation. The odd write and read voltage line drop pads 246 are electrically coupled to odd write and read voltage lines 252 for carrying write and read voltages.

【0100】

The first even array vertical gate voltage switching transistor 245 is switchably electrically coupled to the global bit line landing pad 232 and the even number of write and read voltage line even pads 247. When the first even array vertical gate voltage switching transistor 245 is turned on, the first even array vertical gate voltage switching transistor 245 electrically couples the global bit line pad 232 to the even write and read voltages. The even number of lines falls on pad 247. When the first even array vertical gate voltage switching transistor 245 is turned off, the first even array vertical gate voltage switching transistor 245 will drop the global bit line pad 232 and the even number of write and read voltage lines evenly Pad 247 is electrically separated. The even write and read voltage line even pads 247 are electrically coupled to the even write and read voltage lines 253 for carrying the write and read voltages.

【0101】

The second odd array vertical gate voltage switching transistor 248 is switchably electrically coupled to the global bit line landing pad 232 and the odd erase/precharge/mask voltage line pad 250. When the second odd-array vertical gate voltage switching transistor 248 is turned on, the second odd-array vertical gate voltage switching transistor 248 electrically couples the global bit line pad 232 to the odd erase/pre-charge/ The masking voltage line falls on the pad 250. When the second odd array vertical gate voltage switching transistor 248 is turned off, the second odd array vertical gate voltage switching transistor 248 will drop the global bit line pad 232 and the odd erase/precharge/mask voltage line The pad 250 is electrically separated. The odd erase/precharge/shadow voltage line pad 250 is electrically coupled to an odd erase/precharge/shadow voltage line 254 for carrying the erase/precharge/mask voltage.

【0102】

The second even array vertical gate voltage switching transistor 249 is switchably electrically coupled to the global bit line landing pad 232 and the erase/precharge/mask voltage line landing pad 251. When the second even array vertical gate voltage switching transistor 249 is turned on, the second even array vertical gate voltage switching transistor 249 electrically couples the global bit line pad 232 to the even erase/precharge/ The masking voltage line falls on the pad 251. When the second even array vertical gate voltage switching transistor 249 is turned off, the second even array vertical gate voltage switching transistor 249 will drop the global bit line pad 232 and the even erase/precharge/mask voltage line The pad 251 is electrically separated. The even erase/precharge/mask voltage line drop pads 251 are electrically coupled to the even erase/precharge/mask voltage lines 255 used to carry the erase/precharge/mask voltage.

【0103】

First odd array vertical gate voltage switching transistor 244, first even array vertical gate voltage switching transistor 245, second odd array vertical gate voltage switching transistor 248 and second even array vertical gate voltage switching transistor 249 may be identical to the first set of vertical gate voltage switching transistors 234 illustrated in FIG. 11 and the second set of vertical gate voltage switching transistors 238 illustrated in FIG. In addition, since only even or odd semiconductor strips are required, each of the other semiconductor strips can be replaced with other materials.

[0104]

First odd array vertical gate voltage switching transistor 244, first even array vertical gate voltage switching transistor 245, second odd array vertical gate voltage switching transistor 248 and second even array vertical gate voltage switching transistor 249 separates the erase/precharge/mask voltage on the odd erase/precharge/mask voltage lines 254 and 255 from other circuits, such as sense amplifiers connected via write and read voltage lines 252 and 253.

【0105】

Figure 16 is a perspective view showing the structure of the write and read voltage lines and the write and read voltage line drop pads of the integrated circuit in Fig. 15, which are accessed by even bit lines. Instead of accessing through all bit lines as shown in Figure 12.

【0106】

The even write and read voltage lines 253 are electrically coupled to one of the even write and read voltage line drop pads 247 by a set of conductive plugs, respectively. The even write and read voltage line drop pads 247 include semiconductor strips P2, P4, P6, and P8.

【0107】

In addition to this, the even write and read voltage lines 253 are similar to the write and read voltage lines 242. The even write and read voltage line drop pads 247 can be similar to the write and read voltage line drop pads 236 shown in FIG. In addition, the semiconductor strips P2, P4, P6, and P8 may be replaced with other materials.

【0108】

Figure 17 is a perspective view showing the structure of the write and read voltage lines and the writing and reading voltage line landing pads of the integrated circuit in Fig. 15, which are accessed by odd bit lines. Instead of accessing through all bit lines as shown in Figure 12.

【0109】

The odd write and read voltage lines 252 are electrically coupled to one of the odd write and read voltage line drop pads 246 by a set of conductive plugs, respectively. The odd write and read voltage line drop pads 246 include semiconductor strips P1, P3, P5, and P7.

[0110]

In addition to this, the odd write and read voltage lines 252 are similar to the write and read voltage lines 242. The odd write and read voltage line drop pads 246 can be similar to the write and read voltage line drop pads 236 shown in FIG. In addition, the semiconductor strips P1, P3, P5, and P7 may be replaced with other materials.

[0111]

Figure 18 is a perspective view showing the structure of the erase/precharge/shielding voltage line and the erase/precharge/shielding voltage line landing pad of the integrated circuit in Fig. 15, which is passed through the even bit line. Access is made instead of accessing through all bit lines as shown in Figure 14.

[0112]

The even erase/precharge/shadow voltage lines 255 are electrically coupled to one of the even erase/precharge/shield voltage line landing pads 251 by a set of conductive plugs, respectively. The even erase/precharge/mask voltage line drop pads 251 include semiconductor strips P2, P4, P6, and P8.

[0113]

In addition to this, the even erase/precharge/mask voltage line 255 is similar to the odd erase/precharge/mask voltage line 254 of the erase/precharge/mask voltage. The even erase/precharge/shadow voltage line landing pad 251 can be similar to the erase/precharge/shield voltage line landing pad 240 shown in FIG. In addition, the semiconductor strips P2, P4, P6, and P8 may be replaced with other materials.

【0114】

Figure 19 is a perspective view showing the erase voltage line of the integrated circuit in Fig. 15 and the structure of the erase voltage line drop pad, which are accessed by odd bit lines instead of the 14th The figure shows access through all bit lines.

[0115]

The odd erase/precharge/shadow voltage lines 254 are electrically coupled to one of the odd erase/precharge/shield voltage line landing pads 250 by a set of conductive plugs, respectively. The odd erase/precharge/mask voltage line drop pads 250 include semiconductor strips P1, P3, P5, and P7.

[0116]

In addition to this, the odd erase/precharge/shadow voltage line 254 is similar to the erase/precharge/mask voltage wipe/precharge/mask voltage line 265. The odd erase/precharge/shadow voltage line landing pad 250 can be similar to the erase/precharge/shield voltage line landing pad 240 shown in FIG. In addition, the semiconductor strips P1, P3, P5, and P7 may be replaced with other materials.

【0117】

Figure 20 is a perspective view showing the structure of the even-numbered landing pads of the integrated circuit in Figure 15 in place of the even-numbered landing pads shown in Figures 16 and 18.

【0118】

Unlike the 16th and 18th drawings, the even landing pads P2, P4, P6, and P8 are arranged in a straight line, and the even landing pads P2, P4, P6, and P8 shown in FIG. 20 are arranged in a line. Checkerboard pattern. In addition to this, the even landing pads P2, P4, P6 and P8 are similar to the even landing pads 247 and 251 depicted in Figures 16 and 18. In addition, the even landing pads P2, P4, P6 and P8 may be replaced by other materials.

【0119】

Fig. 21 is a perspective view showing the structure of the odd-numbered landing pads of the integrated circuit in Fig. 15 for replacing the odd-numbered landing pads shown in Figs. 17 and 19.

[0120]

Unlike the 16th and 18th drawings, the even landing pads P2, P4, P6, and P8 are arranged in a straight line, and the even landing pads P1, P3, P5, and P7 shown in FIG. 20 are arranged in a line. Checkerboard pattern. In addition, the even landing pads P1, P3, P5 and P7 are similar to the odd landing pads 246 and 250 depicted in Figures 16 and 18. In addition, the even landing pads P1, P3, P5 and P7 may be replaced by other materials.

【0121】

Fig. 22 is a block diagram showing the wiring on one of the wiring layers of the integrated circuit accessed in all the bit lines in Fig. 8.

【0122】

FIG. 22 illustrates a plurality of parallel bit lines BL1-BL8 120 on the metal layer ML2 coupled to the global bit line 232.

【0123】

Figure 23 is a block diagram showing the wiring on another wiring layer in the integrated circuit accessed in all the bit lines in Figure 8.

[0124]

FIG. 23 illustrates that a plurality of parallel write and read voltage lines BLi1-BLi8 242 located on the metal layer ML1 are coupled to the write and read voltage line landing pads 236. Although located on different metal layers, the write and read voltage lines BLi1-BLi8 242 are oriented in the same direction as the bit lines BL1-BL8 120. The BL_BIAS line 265 is an erase/precharge/shadow voltage line coupled to the erase/precharge/shadow voltage line landing pad 240. BIAS_SEL 262 carries a gate voltage that is used to control whether the second set of vertical gate voltage switching transistors 238 are turned "on" or "off". The BIAS_SEL line 264 carries a gate voltage that is used to control whether the first set of vertical gate voltage switching transistors 234 are turned "on" or "off". The BL_BIAS line 265, the BIAS_SEL line 262, and the BIAS_SEL line 264 are all arranged in parallel on the metal layer ML1. The routing directions of the BL_BIAS line 265, the BIAS_SEL line 262, and the BIAS_SEL line 264 are orthogonal to the bit lines BL1-BL8 120 and the write and read voltage lines BLi1-BLi8 242.

【0125】

In another embodiment, the locations of the metal layers ML1 and ML2 may vary. For example, either or both of them may be placed on the metal layer ML3 or higher. In another embodiment, the direction of the wire described above can be rotated by an angle.

【0126】

Fig. 24 is a block diagram showing the wiring on one of the wiring layers of the integrated circuit accessed by the even and odd bit lines in Fig. 15.

【0127】

FIG. 24 illustrates a plurality of parallel bit lines BL1-BL8 120 on the metal layer ML2 coupled to the global bit line 232.

【0128】

Figure 25 is a block diagram showing the wiring on another wiring layer of the integrated circuit accessed by the even and odd bit lines in Fig. 15.

【0129】

Figure 25 illustrates a plurality of parallel odd-numbered write and read voltage lines BLi1, BLi3, BLi5, and BLi7 252 on the metal layer ML1 coupled to the odd write and read voltage line landing pads 246, and A plurality of parallel even-numbered write and read voltage lines BLi2, BLi4, BLi6, and BLi8 252 located on the metal layer ML1 are coupled to the write and read voltage line coupling pads 247. Unlike the illustration of Figure 23, the write and read voltage lines here are divided into odd and even groups. Although located on different metal layers, odd-numbered write and read voltage lines BLi1, BLi3, BLi5, and BLi7 252 have even-numbered write and read voltage lines BLi2, BLi4, BLi6, and BLi8 252 trace direction and bit elements Lines BL1-BL8 120 are identical.

【0130】

The BL_BIAS line 254 is an odd erase/precharge/shadow voltage line coupled to the odd drop erase/precharge/shadow voltage line pad 250. The BIAS_SEL line 255 is an even erase/precharge/shadow voltage line coupled to the even drop erase/precharge/shield voltage line pad 251. Unlike the Figure 23, these erase/precharge/shadow voltage lines are divided into odd and even groups.

【0131】

The BIAS_SEL line 262 carries a gate voltage that is used to control whether the second odd-array vertical gate voltage switching transistor 248 is turned "on" or "off". The BIAS_SEL line 273 carries a gate voltage that is used to control whether the second even array vertical gate voltage switching transistor 249 is turned "on" or "off". Unlike the BIAS_SEL line 262 depicted in Figure 23, these BIAS_SEL lines are divided into odd and even groups.

【0132】

The BIAS_SEL line 274 carries a gate voltage that is used to control whether the first odd array vertical gate voltage switching transistor 244 is turned "on" or "off". The BIAS_SEL line 275 carries a gate voltage that is used to control whether the first even array vertical gate voltage switching transistor 245 is turned "on" or "off". Unlike the BIAS_SEL line 264 depicted in Figure 23, these BIAS_SEL lines are divided into odd and even groups.

【0133】

The BL_BIAS line 254, the BIAS_SEL line 255, the BIAS_SEL line 272, the BIAS_SEL line 273, the BIAS_SEL line 274, and the BIAS_SEL line 275 are all arranged in parallel on the metal layer ML1. BL_BIAS line 254, BIAS_SEL line 255, BIAS_SEL line 272, BIAS_SEL line 273, BIAS_SEL line 274 and BIAS_SEL line 275 are routed with bit lines BL1-BL8 120 and odd write and read voltage lines BLi1, BLi3, BLi5 and The BLi7 252 even write and read voltage lines BLi2, BLi4, BLi6 and BLi8 are orthogonal.

【0134】

In another embodiment, the locations of the metal layers ML1 and ML2 may vary. For example, either or both of them may be placed on the metal layer ML3 or higher. In another embodiment, the direction of the wire described above can be rotated by an angle.

【0135】

Figure 26 is a simplified circuit diagram of a pair of vertical gate switch transistors that can be used for write or read operations.

【0136】

The first transistor 312 is turned on by the gate voltage BL_SEL 310, so that the bit lines 300 and 330 electrically coupled to the sense amplifier 350 are electrically coupled to each other. The second transistor 322 is turned on by the gate voltage BL_SEL 320 to be electrically coupled from the BL_BIAS 340 to the bit line 300. When used for a write operation, a write voltage having a value of 0V or Vdd is transferred to the bit line 300 through the first transistor 312. When used for a read operation, a read voltage having a value of about ~1V is passed through the first transistor 312 to the sense amplifier 350.

【0137】

Figure 27 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for writing or reading operations in an integrated circuit that is accessed in all bit lines in Figure 8.

【0138】

The circuit illustrated in Fig. 27 is substantially similar to that of Fig. 26, with the difference that the number of switching transistors and sense amplifiers increases as the number of bit lines increases. In order to control the bit line 301, a first transistor 314, a second transistor 324, a bit line 331 and a sense amplifier 351 are added. The bit line 301, the first transistor 314, the second transistor 324, the bit line 331, and the sense amplifier 351 function as a bit line 300, a first transistor 312, a second transistor 322, and a bit line, respectively. 330 is similar to sense amplifier 350.

【0139】

Figure 28 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for write or read operations in an integrated circuit accessed in even and odd bit lines in Figure 15.

【0140】

The circuit shown in Fig. 28 is substantially similar to that of Fig. 27, except that one bit line is required for access, so only even bit lines or odd bit lines can be accessed. In the present embodiment, when a write operation is performed, a write voltage having a value of 0 V or Vdd is transmitted to the bit line BL 300 through the first transistor 312; or when a read operation is performed, the value is approximately ~ A 1V read voltage is passed through the first transistor 312 to the sense amplifier 350. At the same time, when a write operation or a read operation is being performed by the bit line 300, no operation is performed by the bit line 301. The first transistor 312 is turned on, the second transistor 324 is turned off, the bit line 301 is coupled to 0V to shield it, or precharged, thereby placing the bit line 301 and the adjacent bit line 300. The write or read operation is isolated.

【0141】

Figure 29 is a simplified circuit diagram showing a pair of vertical gate switching transistors that can be used for erase operations.

【0142】

The first transistor 312 is turned on by the gate voltage BL_SEL 310, so that the bit lines 300 and 330 electrically coupled to the sense amplifier 350 are electrically separated from each other. The second transistor 322 is turned on by the gate voltage BL_SEL line 320 to electrically couple the bit line 300 to the BL_BIAS line 340. When used for the erase operation, a high intensity erase voltage is transmitted to the bit line BL 300 through the second transistor 322.

【0143】

Figure 30 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for erase operations in an integrated circuit that is accessed in all bit lines in Figure 8.

【0144】

The circuit illustrated in Fig. 30 is substantially similar to that of Fig. 29, with the difference that the number of switching transistors and sense amplifiers increases as the number of bit lines increases. In order to control the bit line 301, a first transistor 314, a second transistor 324, a bit line 331 and a sense amplifier 351 are added. The bit line 301, the first transistor 314, the second transistor 324, the bit line 331, and the sense amplifier 351 function as a bit line 300, a first transistor 312, a second transistor 322, and a bit line, respectively. BLi 330 is similar to sense amplifier 350.

【0145】

Figure 31 is a simplified circuit diagram of a plurality of pairs of vertical gate switching transistors that can be used for erase operations in an integrated circuit accessed in even and odd bit lines in Figure 15.

【0146】

The circuit illustrated in Fig. 31 is substantially similar to that of Fig. 28, with the difference that only the erase operation, not the write or read operation, must be performed in an integrated circuit having even or single bit lines. Unlike the erase operation illustrated in FIG. 31, the even and singular bit lines apply similar bias voltages as illustrated in FIG. Therefore, both the bit lines BL 300 and BLi 330 are applied with a high-intensity erase bias.

【0147】

Figure 32 is a simplified circuit diagram showing an integrated circuit having a vertical gate switching transistor.

【0148】

The integrated circuit 475 includes the stereo NAND flash memory array 460 of the above embodiment, which is placed over a semiconductor substrate having a conductor stack structure and has a capacitor formed of a conductor stack structure. Row decoder 461 is coupled to a plurality of word lines 462 arranged along a row of memory arrays 460. The column decoder in block 466 is coupled to the plurality of string select lines 464 arranged along the columns of the stacked structures in the corresponding memory array 460 for reading or writing data from the memory cells of the memory array 460. . The planar decoder 458 is coupled to a plurality of planar layers of the memory array 460 via a plurality of bit lines 459. The address is provided by bus 465 to row decoder 461, column decoder and plane decoder 458. The page buffer 463 is coupled to the column decoder and memory array 460 in block 466. The page buffer 463 includes the stereo high voltage switch transistor described in the above embodiment. The page buffer 463 multiplexes the bit lines directed to the memory array 460 and the bit lines directed to the sense amplifier or voltage lines used to carry the erase bias. This multiplex can be divided into odd and even lines. The page buffer 463 can include a sense amplifier for performing read and verify operations. The page buffer 463 may include other circuitry, such as fail detection circuitry, to detect whether a pass/retry/fail is performed after the verify operation, and a read write operation is read/ The data cache and the cache decoding/output buffer of the data are written. Data is supplied to the data input structure in block 466 via data input line 471 from an input/output port on integrated circuit 475, or from other sources internal or external to integrated circuit 475. In this embodiment, other circuits 474, such as a general purpose processor or a special purpose application circuitry, are supported by a NAND flash memory array and provide a system-on-a system. The module combination of -chip) is also included in this integrated circuit. The data is provided via data output line 472 from the data output structure in block 466 on integrated circuit 475 to the input/output port on integrated circuit 475, or to other data endpoints internal or external to integrated circuit 475.

【0149】

In the present embodiment, the controller of the biasing arrangement state machine 469 is used to control the application of bias voltages generated or provided by the voltage source or power supply 468, such as read, write, erase, erase verify And write verification; and control is used to control the gate voltages of the first and second sets of vertical gate voltage switching transistors. This controller can be implemented using conventional special purpose logic circuitry. In another embodiment, the controller includes a general purpose processor implemented in the same integrated circuit for performing an operational program to control the operation of the component. In yet another embodiment, a controller can be implemented using a combination of special purpose logic circuitry and a general purpose processor.

【0150】

In some embodiments, the position of the planar decoder, the column decoder, and the row decoder can be changed by changes in routing and decoding, respectively.

[0151]

The adjectives used above, such as above, below, top, bottom, over or under, are used only for descriptive descriptions to aid understanding, not for use. To limit the scope of the invention.

[0152]

Figure 33 is a cross-sectional view showing the structure of different mask combinations that can produce landing zones of different depths. In order to form the landing zone structure described herein,

[0153]

A stacked structure 20 in which the dielectric layer 22 and the conductive layer 24 are staggered is formed on the dielectric substrate 26. In this embodiment, eight sets of dielectric layers 22 and conductive layers 24 are included, labeled 22.0 to 22.7, and 24.0 to 24.7, respectively. A hard mask 30, an etch stop layer 28, and a first dielectric layer 22 overlie the stacked structure 20. The combination of the closed mask region 40 and the open etch region 38 by using the first photoresist mask 52, the second photoresist mask 54 and the second photoresist mask 56 is etched differently. The depth of the contact opening is 32.0 to 32.7.

【0154】

The first photoresist mask 52 has an open etched region 38 covering half of the contact openings 32 (e.g., four, in this embodiment) and a hard mask 30 between the open etched regions 38 and the contact openings 32. The first photoresist mask 52 also has a closed mask region 40 covering the other contact openings 32 and a hard mask 30 between the closure mask region 40 and the contact opening 32. The second photoresist mask 54 has two open etched regions 38 and two closed mask regions 40 interleaved with one another, covering one quarter of the contact openings 32 (eg, two, in this embodiment) and at the openings The etched region 38 and the hard mask 30 between the closed mask region 40 and the contact opening 32. The third photoresist mask 56 has four open etched regions 38 and four closed mask regions 40 interleaved with one another, covering one-eighth of the contact openings 32 (eg, one, in this embodiment) and at the openings The etched region 38 and the hard mask 30 between the closed mask region 40 and the contact opening 32.

【0155】

Reactive ion etching can be used, for example, including tetrafluoromethane/nitrogen/difluoromethane/hydrobromic acid/niobium-oxygen/helium (CF ₄ /N ₂ /CH ₂ F ₂ /HBr/He-O ₂ /He) The chemical etchant stops at the top of a suitable conductive layer 24.0 to 24.7.

【0156】

In the present embodiment, the landing pads are arranged in a straight line corresponding to the closed mask region 40 and the open etched region 38 which are arranged in a line in the mask. In still other embodiments of the invention, the enclosure mask region 40 and the open etch region 38 are arranged in a checkerboard pattern that abuts each other to create odd or even landing pads having a checkerboard pattern that abut each other.

【0157】

Further information on methods and techniques for forming a connecting conductor to a landing pad is disclosed in U.S. Patent Application Serial No. U.S. Patent Application Serial No. Serial No. FOR IC DEVICE WITH STACKED CONTACT LEVELS" and US Patent Application No. US 13/114,931, filed on May 24, 2011, entitled "MULTILAYER CONNECTION STRUCTURE AND MAKING METHOD", wherein the contents of the applications will pass The entire disclosure of this patent is incorporated herein by reference. These applications have a co-inventor with this case.

【0158】

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. The process steps and structures described herein do not encompass the complete fabrication process for making a full volume circuit. The present invention can be implemented in conjunction with a number of different integrated circuit fabrication techniques currently known or developed in the future. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

140, 146, 148‧‧‧ conductive plugs

142‧‧‧First transistor gate

144‧‧‧Second transistor gate

150, 152, 154‧‧‧ source/bungee

Claims (20)

[Item 1] An integrated circuit comprising:
a stereo NAND memory array comprising a plurality of memory transistors;
a plurality of bit lines, the plurality of bit lines of the plurality of bit lines being coupled to a plurality of different portions of the stereo NAND memory array; and a plurality of transistor pairs having a semiconductor stack (stack) Of semiconductor layers, the plurality of different layers in the plurality of transistor pairs, the plurality of different pairs of transistor pairs; each of the plurality of transistor pairs comprising a first a transistor and a second transistor, and the first transistor and the second transistor have a first source/汲 terminal, a second source/汲 terminal, and a third source/汲 terminal point;
Wherein the first transistor has the first source/tb extreme point and the third source/tb extreme point; and the second transistor has the second source/tb extreme point and the third source And the first source/deuterium pole is electrically coupled to an erase voltage line; the second source/turner pole is electrically coupled to the plurality of write/read voltage lines Corresponding to one;
The third source/deuterium pole is electrically coupled to a corresponding one of the plurality of bit lines.
[Item 2] The integrated circuit of claim 1, further comprising a first gate for controlling all of the first transistors of the plurality of transistor pairs; and a second gate for To control all of the second transistors in the plurality of transistor pairs.
[Item 3] The integrated circuit of claim 2, wherein the first gate controls whether the plurality of bit lines are coupled to the first source/汲 terminals of the plurality of transistor pairs And the second gate controls whether the plurality of bit lines are coupled to the two source/drain extreme points of the plurality of transistor pairs.
[Item 4] The integrated circuit of claim 1, wherein the stereo NAND memory array comprises a plurality of stacks of semiconductor strips arranged to be different in the stereo NAND memory array. a plurality of transistor channels of the memory transistor;
And the semiconductor stack includes:
a first semiconductor strip stack structure configured to be the plurality of transistor pairs of the plurality of transistor pairs; and a second semiconductor strip stack structure configured to The plurality of transistor pairs are different from the plurality of transistor channels of the second transistors.
[Item 5] The integrated circuit of claim 4, wherein the plurality of semiconductor strips in the first semiconductor strip stack structure, the plurality of semiconductor strips in the second semiconductor strip stack structure, and A plurality of strips of semiconductor strips located in the plurality of conductor strip stack structures share a plurality of plane positions.
[Item 6] The integrated circuit of claim 1, further comprising a circuit for generating a first set of voltages for the erase voltage line and a second set for the write/read voltage lines Voltage.
[Item 7] The integrated circuit of claim 4, wherein the semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the plurality of bit lines and the semiconductor strips Adjacent to these bit lines.
[Item 8] The integrated circuit of claim 4, wherein the semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the plurality of bit lines and are not associated with the semiconductor strips The bit lines are adjacent to each other.
[Item 9] The integrated circuit as described in claim 2, further comprising a circuit,
Used to perform the following actions:
Opening a plurality of the first transistors; and turning off the plurality of second transistors; and turning on the plurality of the second transistors; and turning off the plurality of the first transistors.
[Item 10] A method for operating a plurality of bit lines, the bit lines being electrically coupled to a stereo NAND memory array having a plurality of memory transistors, wherein different bit lines are electrically coupled to the three-dimensional NAND memory Different parts of the NAND memory array, this method includes:
Switching the bit lines electrically to one of:
(i) a first set of voltages coupled by a first plurality of transistors of at least one first memory operating pattern of the stereo NAND memory array, wherein the first plurality of transistors Having a first semiconductor strip stack structure;
(ii) a second set of voltages coupled by a second plurality of transistors of the at least one second memory operating pattern of the stereo NAND memory array, wherein the second plurality of transistors There is a second semiconductor strip stack structure; and the second memory operation type is different from the first memory operation type.
[Item 11] The method of claim 10, wherein the plurality of semiconductor strips in the first semiconductor strip stack structure are disposed as different ones of the first plurality of transistors a plurality of transistor channels; a plurality of semiconductor strips disposed in the second semiconductor strip stack structure are disposed as a plurality of transistor channels of the plurality of transistors of the second plurality of transistors; The stereo NAND memory array includes a plurality of semiconductor strip stack structures disposed as a plurality of transistor channels of the plurality of memory transistors in the stereo NAND memory array.
[Item 12] The method of claim 11, the plurality of semiconductor strips in the first semiconductor strip stack, the plurality of semiconductor strips in the second semiconductor strip stack structure, and the plurality of semiconductor strips The plurality of semiconductor strips in the semiconductor strip stack structure share a plurality of planar positions; wherein the plurality of planar positions are different for the different transistor channels.
[Item 13] The method of claim 10, wherein the first memory operation type comprises erasing; and the second memory operation type comprises at least one of writing and reading.
[Item 14] The method of claim 10, wherein the first memory operation type comprises erasing, pre-charging, and masking; and the second memory operation type includes writing and reading.
[Item 15] The method of claim 12, wherein the different bit lines of the plurality of bit lines are coupled to the different planar positions in the stereo NAND memory array.
[Item 16] For example, the method described in claim 10 of the patent scope further includes:
Generating the first set of voltages suitable for the first memory operating mode; and generating the second set of voltages suitable for the second memory operating mode.
[Item 17] The method of claim 10, wherein the semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the plurality of bit lines and adjacent to the semiconductor strips. The bit lines.
[Item 18] The method of claim 10, wherein the semiconductor strips in the first semiconductor strip stack structure are electrically coupled to the plurality of bit lines and are not associated with the semiconductor strips. Adjacent to these bit lines.
[Item 19] For example, the method described in claim 10 of the patent scope further includes:
(i) opening the first plurality of transistors; and turning off the second plurality of transistors, thereby coupling the first set of voltages to the plurality of bit lines to perform at least the first memory operation Type;
(ii) opening the second plurality of transistors; and turning off the first plurality of transistors, thereby coupling the second set of voltages to the plurality of bit lines to perform at least the second memory operation Type.
[Item 20] A method for manufacturing an integrated circuit, comprising:
Providing a stereo NAND memory array to include a plurality of memory transistors;
Providing a plurality of bit lines, wherein the plurality of bit lines of the plurality of bit lines are coupled to a plurality of different portions of the stereo NAND memory array; and providing a plurality of transistor pairs to have one a semiconductor stack in which a plurality of different layers in the plurality of transistor pairs comprise a plurality of different pairs of the plurality of transistors; each of the plurality of pairs of transistors includes a first a transistor and a second transistor, and the first transistor and the second transistor have a first source/汲 terminal, a second source/汲 terminal, and a third source/汲 terminal point;
Wherein the first transistor includes the first source/tb extreme point and the third source/tb extreme point; the second transistor includes the second source/tb extreme point and a third source/汲 extreme point;
The first source/deuterium pole is electrically coupled to an erase voltage line; the second source/turn pole is electrically coupled to one of a plurality of write/read voltage lines;
The third source/deuterium pole is electrically coupled to a corresponding one of the plurality of bit lines.