TWI538179B - Backside illumination (bsi) cmos image sensor process - Google Patents

Description

Back-illuminated complementary metal oxide semiconductor transistor image sensing process

The present invention relates to a back-illuminated complementary metal oxide semiconductor transistor image sensing process, and in particular to a back-illuminated metal oxide semiconductor transistor image sensing method for forming a curved mirror on an active surface of a substrate Measuring process.

Back Side Illumination (BSI) image sensor is a common image sensing device, and because the back-illuminated image sensor can be integrated into traditional semiconductor manufacturing, it has lower manufacturing cost and component size. Small and the advantage of higher integration. In addition, the backside illuminated image sensor has the advantages of low operating voltage, low power consumption, high quantum efficiency, low read-out noise, and random access as needed. It has been widely used in electronic products such as PC cameras and digital cameras.

A typical back-illuminated image sensor can be divided into a light sensing area and a peripheral circuit area according to its function. The light sensing area is usually provided with a plurality of photodiodes arranged in an array, and respectively matched with Resetting a MOS transistor such as a reset transistor, a current source follower, and a row selector to receive external light The intensity of the illumination is sensed, and the peripheral circuit area is used to connect the internal metal interconnections and the external connection lines. The principle of sensitization of the back-illuminated image sensor is to distinguish the incident light into a combination of light of different wavelengths, and then receive them by a plurality of photosensitive elements on the semiconductor substrate, and convert them into digital signals of different strengths and weaknesses. For example, the incident light is divided into a combination of three colors of red, blue, and green, and then received by the corresponding photodiode, and then converted into a digital signal.

The invention provides a back-illuminated complementary metal oxide semiconductor transistor image sensing process, which forms at least one curved mirror on the active surface of the substrate, so that incident light penetrating through the photosensitive region of the substrate can be reflected back Photosensitive area to increase the photoelectric conversion efficiency of the photosensitive area.

The present invention provides a back-illuminated complementary metal oxide semiconductor transistor image sensing process comprising the following steps. First, a substrate is provided having an active surface. Next, a curved surface process is performed to planarize the active surface. Then, a reflective layer is formed on the active surface, thereby forming at least one curved mirror on the active surface.

Based on the above, the present invention provides a back-illuminated complementary metal oxide semiconductor transistor image sensing process that forms at least one curved mirror on the active surface of the substrate to pass incident light through the photosensitive region in the substrate. Reflected back into the photosensitive region, thereby increasing the photoelectric conversion efficiency of the photosensitive region.

1-8 are schematic cross-sectional views showing a back-illuminated complementary metal oxide semiconductor transistor image sensing process according to an embodiment of the invention. As shown in FIG. 1, a substrate 110 is provided having a front surface S1 and a back surface S2, wherein the substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, and a tri-five-layer germanium substrate (eg, GaN-on-silicon). A semiconductor substrate such as a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. In the present embodiment, the front surface S1 of the substrate 110 is an active surface.

Next, please continue to refer to FIG. 1-2 to perform a surface forming process (as shown in FIG. 1-2) to form a plurality of curved surfaces S3 by arcuating the front surface S1 of the portion of the substrate 110. Specifically, as shown in FIG. 1, an etching process P1 may be performed to etch the substrate 110 from the front surface S1 of the substrate 110 to form a plurality of grooves R in the substrate 110. Next, as shown in FIG. 2, an annealing process P2 is performed to planarize the substrate 110 between the grooves R. In detail, the annealing process P2 is started by the edge of the opening of the groove R, and the parameters of the annealing process P2, such as time, temperature and pressure, are adjusted to control the degree of arc angle, and the grooves are matched. The size of the substrate 110 between R, in turn, achieves an overall curved surface effect. In the present embodiment, the annealing process P2 is a hydrogen-containing annealing process, but the invention is not limited thereto. In a preferred embodiment, the process temperature of the hydrogen-containing annealing process is greater than 1000 ° C, such that the front side S1 of the substrate 110 is curved. In a more preferred embodiment, the process temperature of the hydrogen-containing annealing process is 1000 ° C, the process pressure is 500 torr, and the process time is 3 minutes to achieve the desired arc surface, and subsequent processes are performed. Form the desired curved mirror in the middle.

It is noted that the arcing process of the embodiment is: forming a groove R in the substrate 110; performing a hydrogen-containing annealing process to vaguely face the front surface S1 of the substrate 110 between the grooves R. However, in other embodiments, the front side S1 of the substrate 110 may be directly curved in other processes without first forming the groove R. Furthermore, if an oxide layer (not shown) is located on the front surface S1 of the substrate 110, the substrate 110 will not be curved, so that when only a portion of the substrate 110 has to be curved, it is not necessary The curved portion of the substrate 110 forms an oxide layer (not shown) thereon, thereby preventing the surface from being curved, thereby achieving the effect of selectively planarizing the portion of the substrate 110. A plurality of arc mirrors are locally formed on the substrate 110 in the subsequent process.

Next, as shown in FIG. 3, an insulating material 10 is filled in each of the grooves R, wherein the step of filling the insulating material 10 may include: first filling an insulating material (not shown) in the groove R, and then The insulating material (not shown) is planarized and etched back to form the insulating material 10 to be lower than the curved surface S3 of the substrate 110. In this embodiment, the insulating material 10 is a shallow trench insulating material, such as hafnium oxide or tantalum nitride, to form a shallow trench isolation (STI) structure or a deep trench isolation in each recess R. (deep trench isolation, DTI) structure, the depth of the shallow trench isolation structure is, for example, about 2500 to 4000 angstroms, and the depth of the deep trench isolation structure is, for example, about 25,000 to 36,000 angstroms, but the present invention does not limit. In other words, the arcuation process of the present invention can be effectively integrated into the existing shallow trench isolation process or deep trench isolation process, that is, masked (not shown) on the front side of the substrate 110 by a patterned tantalum nitride or the like. After S1 forms a plurality of grooves R, the masks are removed, and then the arc finishing process is completed. Then, the insulating material is filled in the grooves and planarized to form a shallow trench isolation (STI) structure, so that the substrate between the shallow trench insulations becomes an active area having a curved surface S3 structure. . In addition, in the planarization process of chemical mechanical polishing or the like, it is preferred to over-polishing the insulating material in the recess R or in combination with an etch-back process so that the curved surface S3 is more prominent than shallow. Ditch insulation surface.

As shown in FIG. 4, the photosensitive region 120 is formed in the substrate 110, and the photosensitive region 120 can be, for example, a photodiode (not shown), but the invention is not limited thereto, wherein the photosensitive diode ( The formation method of the unillustrated is well known in the art and will not be described again. Generally, the photosensitive region 120 will include a P-N junction C where the incident light to be measured is absorbed and converted into an electron/hole pair to generate a sensing current. When the photosensitive region 120 is a source or a drain region of a MOS transistor (not shown) of the CMOS image sensor, the sensing current is transmitted to other components by the MOS transistor (not shown), for example, A MOS transistor such as a reset transistor, a current source follower, and a row selector is used to convert the sensed light into a digital signal or in a peripheral circuit area. The logic MOS transistor and the like in the present embodiment are not exemplified in this embodiment.

Then, a reflective layer 20 is formed on each of the curved faces S3 of the substrate 110, thereby forming at least one curved mirror 22 on the curved surface S3. The reflective layer 20 may be, for example, a plurality of mirrors composed of a reflective material such as metal, or may be a film layer of a plurality of different materials (which utilize different refractive indices to achieve total reflection), such as cerium oxide and nitridation. Combination of cockroaches A plurality of mirrors are formed to reflect light incident from the back surface S2 of the substrate 110 back into the photosensitive region 120. Since the face of the curved mirror 22 facing the substrate 110 is a concave mirror, the curved mirror 22 can reflect the light incident from the back surface S2 of the substrate 110. In a preferred embodiment, the focus of each of the curved mirrors 22 should be disposed on the PN junction surface C, so that the light passing through the PN junction surface C can be reflected by the respective curved mirrors 22 and then concentrated on the PN junction surface. In C, the light is converted into an electron/hole pair, thereby increasing the photoelectric conversion efficiency of the photosensitive region 120.

In this embodiment, since the sensing region 120 is the source or the drain region of each MOS transistor, a self-aligned metal salicide process P3 can be directly performed to form a metal germanide as a separate The reflective layer 20 of the invention is on the source or drain regions of the MOS transistors, such that metal tantalum can be self-aligned on each of the arcuate faces S3. The metal halide is generally nickel/telluride. In order to make the metal halide effectively reflect light, in the present embodiment, the thickness of the metal halide is preferably greater than 200 angstroms, but the invention is not limited thereto. Furthermore, in the present embodiment, the self-aligned metal telluride process can be performed in conjunction with the MOS transistor process in the logic circuit region, for example, after forming the insulating material 10, the gate forming process is performed first, and the source/drain formation is performed. The self-aligned metal telluride process is performed after the process. Therefore, the sensing region 120 is masked in the logic circuit region process until the region where the metal halide is to be formed is exposed until the self-aligned metal germanide process is performed.

Next, after the metal germanide is formed, an interlayer dielectric layer may be formed to cover the metal germanide and fill the recess R on the insulating material 10. For example, as shown in FIG. 5, a desired contact plug (not shown) and an interconnect structure 130 are formed on the front surface S1 of the substrate 110. The interconnect structure 130 includes a plurality of interlayer dielectric layers and an interlayer metal dielectric A dielectric layer 132 such as an intermetal dielectric (IMD) and a plurality of metal layers 134. The dielectric layer 132 is, for example, an oxide layer, and the metal layer 134 is composed of, for example, aluminum or copper, but the invention is not limited thereto. Specifically, the interconnect structure 130 is formed by forming the respective dielectric layers 132; etching the dielectric layers 132 to form recesses (not shown) in the respective dielectric layers 132; and filling the metal (for example, aluminum or A structure in which a copper is formed in a groove (not shown) in a cyclic process of forming a metal layer 134 or the like.

Then, as shown in FIG. 6, the substrate 110 is inverted, and then the substrate 110 is thinned from the back surface S2 of the substrate 110, preferably to expose the insulating material 10, to electrically insulate the MOS transistors corresponding to the photosensitive regions 120, thereby avoiding the substrate 110. Leakage current. The process of thinning the substrate 110 can be, for example, a planarization process such as a chemical mechanical polishing (CMP) process, but the invention is not limited thereto.

As shown in FIG. 7, a doped layer or/and an oxide layer (not shown) may be selectively formed on the back surface S2, and then an anti-reflective layer 140 may be formed on the substrate 110 (or doped). Layer, oxide layer). The anti-reflection layer 140 may be, for example, a tantalum nitride layer, a hafnium oxynitride layer, a carbon-doped tantalum nitride layer, a carbon-doped niobium oxynitride layer, or the like. Then, at least one color filter 150 is formed on the anti-reflection layer 140. In this embodiment, a patterned blue filter 152, a patterned green filter 154, and a patterned red filter 156 are respectively formed on the anti-reflection layer 140, but the present invention does not To this end, in other embodiments, color filters of other color systems may be formed, depending on actual needs. It is noted that each photosensitive region 120 of the present invention is located between the corresponding color filter 150 and the curved mirror 22, and each curved mirror 22 is disposed through the color The color filter 150 has a light path on the light. In this way, the curved mirror 22 can receive the light filtered from the color filter 150, and the light passing through each photosensitive region 120 is reflected by the curved mirrors 22 to the corresponding photosensitive region 120. More preferably, the light is reflected to the PN junction surface to effectively increase the photoelectric conversion efficiency of the photosensitive region 120, thereby increasing the formed back-illuminated complementary metal oxide semiconductor transistor image sensing device. Sensing sensitivity. The present invention is suitable for use in a back-illuminated complementary metal oxide semiconductor transistor image sensing device, but the present invention is also applicable to other substrates 110 that are required to reflect light, depending on actual needs.

As shown in FIG. 8, a flat layer (not shown) may be selectively formed on each of the color filters 150. Then, a microlens 162, 164, 166 is formed on each color filter 150 or a flat layer (not shown) to concentrate the light into each of the color filters 150. Thereafter, a passivation layer (not shown) may be selectively formed on each of the microlenses 162, 164, and 166, and then the subsequent back-illuminated complementary metal oxide semiconductor transistor image sensing process or external power Connection process, etc.

In summary, the present invention provides a back-illuminated complementary metal oxide semiconductor transistor image sensing process that forms at least one curved mirror on the active surface of the substrate to pass through the photosensitive region in the substrate. The light is again reflected back into the photosensitive region, thereby increasing the photoelectric conversion efficiency of the photosensitive region. In detail, the method of forming the curved mirror first performs a surface forming process to arcuate the active surface, and then forms a reflective layer on the active surface to form at least one curved mirror on the active surface. In an embodiment, the method for performing the surface forming process may include: first etching the substrate from the active surface to form a plurality of grooves in the substrate; The annealing process is to arc-form the active surface between the grooves, wherein the annealing process may be a hydrogen-containing annealing process, but the invention is not limited thereto.

Furthermore, in the embodiment, the photosensitive region is a germanium-containing material such as a source or a drain region of each MOS transistor, so that a metal germanium process can be directly performed to form a curved mirror on each source or drain. However, the invention is not limited thereto, and a metal or a plurality of films having different refractive indexes may be formed to form each curved mirror.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Insulation materials

20‧‧‧reflective layer

22‧‧‧Arc mirror

110‧‧‧Base

120‧‧‧Photosensitive area

130‧‧‧Inline structure

132‧‧‧ dielectric layer

134‧‧‧metal layer

140‧‧‧Anti-reflective layer

150‧‧‧Color filters

152‧‧‧ patterned blue filter

154‧‧‧ patterned green filter

156‧‧‧ patterned red filter

162, 164, 166‧‧‧ microlenses

C‧‧‧P-N junction

P1‧‧‧ etching process

P2‧‧‧ Annealing Process

P3‧‧‧Self-aligned metal telluride process

R‧‧‧ groove

S1‧‧ positive

S2‧‧‧Back

S3‧‧‧ curved surface

1-8 are schematic cross-sectional views showing a back-illuminated complementary metal oxide semiconductor transistor image sensing process according to an embodiment of the invention.

10‧‧‧Insulation materials

20‧‧‧reflective layer

22‧‧‧Arc mirror

110‧‧‧Base

120‧‧‧Photosensitive area

C‧‧‧P-N junction

P3‧‧‧Self-aligned metal telluride process

S2‧‧‧Back

S3‧‧‧ curved surface

Claims (19)

A Backside Illumination (BSI) complementary metal oxide semiconductor transistor image sensing process includes: providing a substrate having an active surface; performing a curved surface process to planarize the active surface, The step of performing the arc finishing process includes: etching the substrate from the active surface to form a plurality of grooves in the substrate; and performing an annealing process to arcuate the active surface between the grooves After performing the annealing process, an insulating material is filled in each of the grooves; and a reflective layer is formed on the active surface, thereby forming at least one curved mirror on the active surface. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 1, wherein the face of the curved mirror facing the substrate is a concave mirror. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 1, wherein the step of the arc finishing process comprises: etching the substrate from the active surface to form a plurality of concaves. The groove is in the substrate; and an annealing process is performed to arcuate the active surface between the grooves. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 3, wherein the annealing process comprises a hydrogen-containing annealing process. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 4, wherein the process temperature of the hydrogen-containing annealing process is greater than 1000 ° C. The back-illuminated complementary metal oxide semiconductor transistor image sensing process according to claim 5, wherein the hydrogen-containing annealing process has a process temperature of 1000 ° C, a process pressure of 500 torr, and a process The time is 3 minutes. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 3, wherein after the annealing process, the method further comprises: filling an insulating material in each of the grooves. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 7, wherein the insulating material comprises a shallow trench insulating material for forming a shallow trench isolation (STI) )structure. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 1, wherein before the performing the surface forming process, the method further comprises: forming an oxide layer on the active surface To prevent part of the active surface from being curved. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 1, wherein the method of forming the reflective layer comprises performing a self-aligned metal telluride process to form a metal germanium On the active surface. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 10, wherein the back-illuminated metal oxide semiconductor transistor image sensing is performed after the metal telluride process The process further includes forming at least one interconnect structure on the active surface. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 10, wherein the metal telluride has a thickness greater than 200 angstroms. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 1, further comprising the step of forming a photosensitive region on the substrate after the arc finishing process. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 13, wherein the focus of the curved mirror is located in the photosensitive region. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 13, wherein the photosensitive region comprises a P-N junction, and the focus of the curved mirror is located on the P-N junction. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 13, wherein the active surface is located on a front side of the substrate, and after forming the reflective layer, the back-illuminated Complementary metal oxide semiconductor transistor The image sensing process further includes: forming an interconnect structure on the active surface; thinning the substrate from a back surface of the substrate; and forming at least one color filter on the back surface. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 16, wherein the arc mirror is disposed on a light path of the light passing through the color filter, and The photosensitive region is located between the color filter and the curved mirror. The back-illuminated complementary metal oxide semiconductor transistor image sensing process of claim 16, wherein before forming the color filter, the method further comprises: forming an anti-reflcctive layer. On the back. The back-illuminated metal oxide semiconductor transistor image sensing process of claim 16, wherein after the color filter is formed, the method further comprises: forming a microlens in each of the color filters. on.