TWI536541B - Semiconductor device layout structure - Google Patents

Description

Semiconductor device layout structure

The present invention relates to a semiconductor device layout structure, and more particularly to a device layout structure having a vertical diffusion super junction structure.

The conventional vertical diffusion gold-oxygen half field effect transistor (VDMOSFET) is mainly formed by an N-type epitaxy drift doped region and a PN junction with a P-type base doped region above it. The surface resistance of the semiconductor element is mainly the PN junction. When the operating voltage of the semiconductor element is increased, the dopant concentration of the N-type epitaxial drift doping region must be lowered and the thickness thereof increased. In contrast, the above-mentioned method of increasing the withstand voltage of the P-N junction also increases the on-resistance (Ron) of the device, and the on-resistance is also limited by the dopant concentration and thickness of the N-type epitaxial drift doping region. The vertical diffusion gold-oxygen half-field effect transistor with super-junction structure can improve the dopant concentration of the N-type epitaxial drift doping region, thereby improving the on-resistance (Ron) of the device.

Technology using conventional epitaxial multilayer ^{(multi-epi technology, COOLMOS TM} ) technology to form a super junction (Super-junction) structure, the multilayer epitaxial techniques require multiple epitaxial comprising, implanting P type dopant, Process cycle for high temperature diffusion. Therefore, the above-mentioned multi-layer epitaxial technology has disadvantages such as many process steps and high cost. Moreover, the size of the conventional vertical diffusion MOS field-effect transistor is difficult to shrink.

Therefore, there is a need in the art for a semiconductor device layout structure having a super junction structure to improve the above disadvantages.

One embodiment of the present invention provides a semiconductor device layout structure. The semiconductor device layout structure includes an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region provides a plurality of semiconductor elements formed thereon; and a first super junction layout unit , in the active region, including a first trench; a first doped region having the first conductivity type, the first doped region surrounding the first trench; and a second trench surrounding the first a doped region; a second doped region having a second conductivity type, the second doped region surrounding the second trench, wherein in a top view, the first trench is doped by the first doping The region and the second doped region are laterally spaced from the second trench.

Another embodiment of the present invention provides a semiconductor device layout structure. The semiconductor device layout structure includes an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region provides a plurality of semiconductor elements formed thereon; a first super junction layout The unit, located in the active area, includes a first trench having a first sidewall and a second sidewall adjacent to the first sidewall; a first doped region having the first conductivity type, a first doped region surrounding the first trench; a second trench adjacent to the first sidewall of the first trench; a second doped region having a second conductivity type, the second doped region Surrounding the second trench, wherein in a top view, the first trench is formed by the first doping region and the first The second doped region is laterally spaced apart from the second trench; a third trench adjacent to the second sidewall of the first trench; a third doped region having the second conductivity type, the third doping The inter-cell surrounds the second trench, wherein in the top view, the first trench is laterally separated from the third trench by the first doped region and the third doped region.

Yet another embodiment of the present invention provides a semiconductor device layout structure. The semiconductor device layout structure includes an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region provides a plurality of semiconductor elements formed thereon; a super junction layout unit is located The active region includes a first trench; a first doped region having the first conductivity type, the first doped region surrounding the first trench; and a second trench adjacent to the first trench a second doped region having a second conductivity type, the second doped region surrounding the second trench, wherein in a top view, the first trench is formed by the first doped region and The second doped region is laterally spaced apart from the second trench, and wherein the first sidewall of the first trench is parallel to a second trench of the first sidewall adjacent to the first trench Two side walls.

200‧‧‧Semiconductor substrate

201h1, 204h1, 204j1‧‧‧ first side wall

201h2, 204h2, 218j1‧‧‧ second side wall

202‧‧‧ epitaxial layer

300‧‧‧active area

302‧‧‧ Terminal Area

500‧‧‧Semiconductor device

204, 204a204f, 204h, 204j, 204k, 2041, 204m‧‧‧ first trench

206‧‧‧First insulating liner

207, 221‧‧‧ side wall

205, 219‧‧‧ bottom

210, 210a~210f, 210h, 210j, 220k, 220m‧‧‧ first doped area

218, 218a~218f, 218h1, 218j, 218k, 2181, 21811~21816, 218m‧‧‧ second trench

218a2‧‧‧Internal sidewall section

218a1‧‧‧External side wall section

218h2‧‧‧ third trench

220‧‧‧Second insulation liner

222, 222a~222f, 222h1, 222j, 222k, 2221, 22211~22216, 222m‧‧‧ second doped area

222h2‧‧‧ third doping zone

224‧‧ ‧ gate oxide layer

226‧‧ ‧ gate layer

228‧‧ ‧ gate structure

230‧‧‧Second insulation

232‧‧‧First Well Area

234‧‧‧ source area

236‧‧‧Interlayer dielectric layer

238‧‧‧Contact hole opening

242‧‧‧Contact hole plug

244a~244g‧‧‧rounded ends

250‧‧‧Super junction structure

400, 402‧‧‧ directions

600a~600h‧‧‧Semiconductor device layout structure

610, 610a~610g, 620a~620e‧‧‧ super junction layout unit

D1, D2‧‧‧ distance

W1, W2‧‧‧ width

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a semiconductor device in accordance with some embodiments of the present invention.

2A and 2B are top plan views of N-type trenches and P-type trenches of a semiconductor device layout structure according to some embodiments of the present invention.

3 is a view showing a layout structure of a semiconductor device according to some other embodiments of the present invention. A top view of a trench and a P-channel.

4A-4E are top plan views of an N-type trench and a P-type trench of a semiconductor device layout structure according to some embodiments of the present invention, wherein the N-type trench and the P-type trench are arranged in an array.

In order to make the objects, features, and advantages of the present invention more comprehensible, the detailed description of the embodiments and the accompanying drawings. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. The overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description and are not intended to be related to the different embodiments.

Embodiments of the present invention provide a semiconductor device layout structure. The above semiconductor device layout structure includes a layout of a metal oxide semi-transistor transistor (MOSFET) having a super junction structure, such as a layout of a super-contact vertical diffusion metal oxide half field effect transistor (VDMOSFET).

1 shows a schematic cross-sectional view of a semiconductor device 500 in accordance with some embodiments of the present invention. In some embodiments of the present invention, the semiconductor device 500 includes a MOS thin film transistor (MOSFET) having a super junction structure, such as a super-connected vertical diffusion MOS field-effect transistor (VDMOSFET). . As shown in FIG. 1, in some embodiments of the present invention, the semiconductor device 500 includes a semiconductor substrate 200 having a first conductivity type. An epitaxial layer 202 having the above first conductivity type is formed on the semiconductor substrate 200. In some embodiments of the present invention, the epitaxial layer 202 may include an active region 300 and a termination region 302 surrounding the active region 300. In an embodiment of the invention The active region 300 is provided with semiconductor elements formed thereon, and the termination region 302 serves as insulation between different semiconductor devices. A first trench 204 is formed in the epitaxial layer 202. A first insulating spacer layer 206 is formed on a sidewall 207 and a bottom surface 205 of the first trench 204. A first insulating material 212 is filled in the first trench 204. A first doped region 210 is formed in the partial epitaxial layer 202 from the sidewall 207 and the bottom surface 205 of the first trench 204. The first doped region 210 described above substantially surrounds the first trench 204. In some embodiments of the invention, the first doped region 210 has the first conductivity type described above. A first insulating material 212 is filled in the first trench 204. A second trench 218 is formed in the epitaxial layer 202. A second insulating spacer layer 220 is formed on a sidewall 221 and a bottom surface 219 of the second trench 218. A second insulating material 230 is filled in the second trench 218. A second doped region 222 is formed in the range from the sidewall 221 and the bottom surface 219 of the second trench 218 to the portion of the epitaxial layer 202. The second doped region 222 substantially surrounds the second trench 218. In some embodiments of the invention, the second doped region 222 has a second conductivity type different from the first conductivity type described above. In some embodiments of the invention, the first doped region 210 is adjacent to the second doped region 222 along a first direction 400, as shown in FIG. In some embodiments of the invention, the first conductivity type is N-type, and the second conductivity type is P-type. Accordingly, a super junction structure 250 of some embodiments of the present invention is formed, the super junction structure 250 having a first doped region 210 surrounding the first trench 204 and a second doping surrounding the second trench 218 Area 222. The first doping region 210 and the second doping region 222 of the super junction structure 250 are adjacent to each other. Therefore, an interface between the first doping region 210 of the super junction structure 250 and the second doping region 222 adjacent to the first doping region 210 forms a PN junction. Some in the present invention In the embodiment, the first trench 204 for forming the N-type first doping region 210 can be regarded as an N-type trench 204. Moreover, the second trench 218 for forming the P-type second doping region 222 can be regarded as a P-type trench 218. In some embodiments of the present invention, the N-type trench 204, the P-type trench 218, the N-type first doped region 210 surrounding the N-type trench 204, and the P-type trench 218 surrounding the P-type trench 218 are adjacent to The P-type second doping region 222 of the N-type first doping region 210 constitutes a super junction layout unit 610.

As shown in FIG. 1, in some embodiments of the present invention, the semiconductor device 500 further includes a gate structure 228, and the gate structure 228 includes a gate oxide layer 224 and a gate layer 226. The gate structure 228 covers the first trench 204 and covers a portion of the epitaxial layer 202 of the adjacent first trench 204. The second trench 218 is exposed from the gate structure 228. A first well region 232 is formed in the epitaxial layer 202 that is not covered by the gate structure 228, and the first well region 232 has a second conductivity type. A source region 234 is formed in the first well region 232, and the source region 234 has the first conductivity type described above. The source region 234 is adjacent to the gate structure 228. In some embodiments of the invention, an interlevel dielectric layer (ILD) 236 is formed to cover the epitaxial layer 202 and the gate structure 228. A contact hole opening 238 is formed through the interlayer dielectric layer 236 described above. The second trench 218 and a portion of the epitaxial layer 202 adjacent to the second trench 218 are exposed from the contact hole opening 238. A wiring region 240 is formed in a portion of the epitaxial layer 202 exposed from the contact hole opening 238, and the wiring region 240 has the second conductivity type described above. A contact hole plug 242 is filled in the contact hole opening 238.

2A and 2B are top plan views of N-type trenches and P-type trenches of semiconductor device layout structures 600a, 600b of some embodiments of the present invention. In the present invention In some embodiments, one or more super junction layout units may be disposed in the active region 300, and the super junction layout unit includes an N-type trench, a P-type trench, and a surrounding of the N-type trench. An N-type first doped region and a P-type second doped region surrounding the P-type trench 218 and adjacent to the N-type first doped region. As shown in FIG. 2A, the semiconductor device layout structure 600a includes super-junction layout units 610a-610f arranged side by side in the direction 400. The super junction layout unit 610a includes a first trench 204a. A first doped region 210a has a first conductivity type, and the first doped region 210a surrounds the first trench 204a. A second trench 218a surrounds the first doped region 210a. A second doped region 222a has a second conductivity type, and the second doping 222a region surrounds the second trench 218a. In some embodiments of the present invention, in a top view as shown in FIG. 2A, the first trench 204a is lateral to the second trench 218a by the first doped region 210a and the second doped region 222a. Separated (in direction 400).

In some embodiments of the invention, the first conductivity type is N-type, and the second conductivity type is P-type. In some embodiments of the present invention, the first trench 204a for forming the N-type first doping region 210a may be regarded as an N-type trench 204a of the super junction layout unit 610a. Moreover, the second trench 218a for forming the P-type second doping region 222a can be regarded as a P-type trench 218a of the super-junction layout unit 610a.

In some embodiments of the present invention, a top view shape of the first trench 204a includes a strip shape, and the strip shape extends in a direction 402 as shown in FIG. 2A. A top view shape of the second groove 218a includes an annular shape, and the annular shape extends in the direction 402. In some embodiments of the present invention, the second trench 218a is compliant to surround a sidewall of the first trench 204a. (boundary). In the super junction layout unit 610a, the sidewalls of the first trench 204a and the sidewalls of the second trench 218a adjacent to the sidewall of the first trench 204a are parallel to each other. Moreover, the second trench 218a is separated from the first trench 204a by a fixed distance D1.

In some embodiments of the present invention, a first dopant having a first conductivity type is doped with a portion of the epitaxial layer 202 along two opposite sidewalls 207 of the first trench 204, respectively, by performing a doping process. The first doped region 210a of the above-described super junction layout unit 610a is formed as shown in FIG. Therefore, in some embodiments of the present invention, the first doping region 210a of the superjunction layout unit 610a is adjacent to a sidewall (boundary) of the first trench 204a, as shown in FIG. 2A. Similarly, a second dopant having a second conductivity type opposite to the first conductivity type is respectively doped with a portion of the opposite sidewalls 221 of the second trench 218 by performing another doping process. Layer 202 is formed to form a second doped region 222a of the superjunction layout unit 610a. Therefore, in some embodiments of the present invention, the second doping region 222a of the superjunction layout unit 610a is adjacent to the sidewall (boundary) of the second trench 218, as shown in FIG. 2A.

In some embodiments of the present invention, the sidewall of the second trench 218 of the superjunction layout unit 610a has an inner sidewall portion 218a2 proximate to the first trench 204a and away from the first trench 204a. An outer sidewall portion 218a1 is shown in Figure 2A. In some embodiments of the present invention, the second doped region 222a of the inner sidewall portion 218a2 adjacent to the sidewall of the second trench 218 is simultaneously adjacent to the first doped region 210a of the superjunction layout unit 610a. .

In some embodiments of the present invention, the super junction layout unit The first trench 204a of 610a has a round-shaped end 244a as shown in FIG. 2A. Since the second trench 218a is compliantly disposed around a sidewall (boundary) of the first trench 204a, the outer sidewall portion 218a1 of the second trench 218 is adjacent to the rounded end 244a of the first trench 204a. Can be configured as a rounded shape.

In some embodiments of the present invention, the semiconductor device layout structure 600a includes super-junction layout units 610b-610f disposed alongside the super-junction layout unit 610a. The above-described super junction layout units 610b to 610f are layout configurations having a super junction layout unit 610a similar to the above-described semiconductor device layout structure 600a as shown in FIG. 2A. For example, the super-junction layout unit 610b/610c/610d/610e/610f includes a first trench 204b/204c/204d/204e/204f. a first doped region 210b/210c/210d/210e/210f having a first conductivity type, the first doped region 210b/210c/210d/210e/210f surrounding the first trench 204b/204c/204d/204e/ 204f. A second trench 218b/218c/218d/218e/218f surrounds the first doped region 210b/210c/210d/210e/210f. a second doped region 222b/222c/222d/222e/222f having a second conductivity type, the second doping 222b/222c/222d/222e/222f region surrounding the second trench 218b/218c/218d/218e/ 218f. In some embodiments of the present invention, in a top view as shown in FIG. 2A, the first trenches 204b/204c/204d/204e/204f are formed by the first doping region 210b/210c/210d/210e/ The 210f and second doped regions 222b/222c/222d/222e/222f are laterally spaced (in the direction 400) from the second trenches 218b/218c/218d/218e/218f.

In some embodiments of the present invention, a top view shape of the first trenches 204a 204f of the superjunction layout units 610a-610f includes a strip And the elongated strip extends in the direction 402. The first trenches 204a to 204f of the above-described super junction layout units 610a to 610f are parallel to each other. In some embodiments of the present invention, the outer sidewall portions 218b1 to 218e1 of the second trenches 218b to 218e adjacent to the rounded ends 244b to 244e of the first trenches 204b to 204e may be respectively configured in a rounded shape.

In some embodiments of the present invention, the super-junction layout units 610a-610f are arranged side by side. As shown in FIG. 2A, the second trench 218b of the super junction layout unit 610b overlaps with the second trench 218a of the super junction layout unit 610a. Similarly, the second trench 218c of the superjunction layout unit 610c overlaps with the second trench 218b of the superjunction layout unit 610b. The second trench 218d of the super junction layout unit 610d overlaps with the second trench 218c of the super junction layout unit 610c. The second trench 218e of the super junction layout unit 610e overlaps with the second trench 218d of the super junction layout unit 610d. The second trench 218f of the super junction layout unit 610f overlaps with the second trench 218e of the super junction layout unit 610e.

As shown in FIG. 2A, in some embodiments of the present invention, one of the differences between the super-junction layout units 610a-610f is the first trenches 204a-204f of the super-junction layout units 610a-610f. There are different lengths in direction 402. For example, a length of the first trench 204b of the super junction layout unit 610b is greater than the first trench 204a of the super junction layout unit 610a. In some embodiments of the invention, the lengths of the first trenches 204a-204f are gradually increased.

As shown in FIG. 2A, in some embodiments of the present invention, the semiconductor device layout structure 600a has three super junction layout units 610f arranged side by side in the direction 400. Therefore, the first trench 204f of the super junction layout unit 610f Have the same length. The outer side wall portions 218f1 of the second grooves 218f of the above three super junction layout units 610f are collectively formed in a rectangular shape.

2B is a top plan view of an N-type trench and a P-type trench of a semiconductor device layout structure 600b of some embodiments of the present invention. In some embodiments of the present invention, one of the differences between the semiconductor device layout structure 600a and the semiconductor device layout structure 600b is that the semiconductor device layout structure 600b as shown in FIG. 2B includes three super junction layout units. 610g, in place of the three super junction layout units 610f shown in FIG. 2A. In some embodiments of the present invention, the outer sidewall portions 218g1 of the second trench 218g of the three ultra-super junction layout units 610g that are close to the rounded ends 244g of the first trench 204g are respectively configured in a rounded shape.

3 is a top plan view of an N-type trench and a P-type trench formed in the active region 300 of the semiconductor device layout structure 600c of some other embodiments of the present invention. In some embodiments of the invention, a plurality of spaced apart P-type trenches may be disposed substantially along different sidewalls of the N-type trench. As shown in FIG. 3, in some embodiments of the present invention, the semiconductor device layout structure 600c may include a plurality of super-junction layout units 610h arranged side by side in the direction 400. In some embodiments of the present invention, the super junction layout unit 610h includes a first trench 204h. The first trench 204h has two opposite first sidewalls 201h1 and two opposite second sidewalls 201h2, and the second sidewall 201h2 is adjacent to the first sidewall 201h1. In some embodiments of the invention, the two opposing first side walls 201h1 extend generally along the direction 402, while the two opposing second side walls 201h2 extend generally along the direction 400. A first doped region 210h has a first conductivity type, and the first doped region 210h surrounds the first trench 204h. Two mutually opposite second grooves 218h1 are respectively close to the first two opposite to each other of the first groove 204h Side wall 204h1. A second doped region 222h1 has a second conductivity type, and the second doped region 222h1 surrounds the second trench 218h1. In a top view as shown in FIG. 3, the first trench 204h in the super junction layout unit 610h is lateral to the second trench 218h1 by the first doping region 210h and the second doping region 222h1. Separated (in direction 400). The super junction layout unit 610h further includes two third trenches 218h2 opposite to each other, respectively adjacent to the two second sidewalls 204h2 opposite to each other of the first trench 204h. A third doped region 222h2 has a second conductivity type, and the third doped region 222h2 surrounds the third trench 218h2. In a top view as shown in FIG. 3, the first trench 204h in the super junction layout unit 610h is lateral to the third trench 218h2 by the first doping region 210h and the third doping region 222h2. Separated (in direction 402).

In some embodiments of the invention, the first conductivity type is N-type, and the second conductivity type is P-type. In some embodiments of the present invention, the first trench 204h for forming the N-type first doping region 210h may be regarded as the N-type trench 204h of the super junction layout unit 610h. Also, the second trench 218h1 for forming the P-type second doping region 222h1 can be regarded as the P-type trench 218h1 of the super junction layout unit 610h. Further, the above-described third trench 218h2 for forming the P-type third doping region 222h2 can be regarded as the P-type trench 218h2 of the super junction layout unit 610h.

In some embodiments of the present invention, the first doping region 210h as shown in FIG. 3 forms a first sidewall 204h1 and a second sidewall 204h2 adjacent to the first trench 204h. In some embodiments of the present invention, as shown in FIG. 3, the second doping region 222h1 is formed adjacent to a sidewall of the second trench 218h1, and the third doping region 222h2 is formed adjacent to the third trench. One side wall of 218h2.

In some embodiments of the present invention, the super junction layout unit A top view shape of the first groove 204h of 610h includes an elongated shape, and the elongated shape extends in the direction 402 as shown in FIG. Moreover, a top view shape of the second groove 218a includes an elongated shape, and the elongated shape extends in the direction 402. In the above-described super junction layout unit 610h, the first sidewall 204h1 of the first trench 204h and the sidewall of the second trench 218h1 of the first sidewall 204h1 close to the first trench 204h are parallel to each other. Moreover, the second trench 218h1 is separated from the first trench 204h by a fixed distance D1, as shown in FIG.

In some embodiments of the present invention, a top view shape of the third trench 218h2 of the super junction layout unit 610h includes a rectangle. In the super junction layout unit 610h, the third trench 218h2 is separated from the first trench 204h by a fixed distance D2, as shown in FIG.

In some embodiments of the invention, the third trench 218h2 is aligned in the direction 400 to the second trench 218h1. A width W2 of the third trench 218h2 in the direction 400 is equal to a width W1 of the first trench 204h in the direction 400. In some embodiments of the present invention, one of the two opposing second trenches 218h1 of the superjunction layout unit 610h is associated with two opposite second trenches of another adjacent superjunction layout unit 610h. One of the grooves 218h1 overlaps each other as shown in FIG. Moreover, the second trench 218h1 of the two adjacent super junction layout units 610h overlapping each other is separated from the two adjacent super junction layout units 610h by a fixed distance D2.

4A-4E are top plan views of N-type trenches and P-type trenches of semiconductor device layout structures 600d-600h according to some embodiments of the present invention. In some embodiments of the invention, the N-type trenches and the P-type trenches are arranged in an array. As shown in FIG. 4A, in some embodiments of the present invention, the above semiconductor device layout structure 600d includes a plurality of superjunction layout units 620a arranged in an array. Each of the super junction layout units 620a includes a first trench 204j and a second trench 218j adjacent to the first trench 204j. A first doped region 210j has a first conductivity type, and the first doped region 210j surrounds the first trench 204j. A second doped region 222j has a second conductivity type, and the second doped region 222j surrounds the second trench 218j. In a top view as shown in FIG. 4A, the first trench 204j in the super junction layout unit 620a is lateral to the second trench 218j by the first doping region 210j and the second doping region 222j. Separated (in direction 400). In the super junction layout unit 610a, the first sidewall 204j1 of the first trench 204j and a second sidewall 218j1 of the second trench 218j adjacent to the first sidewall 204j1 are parallel to each other.

In some embodiments of the invention, the first conductivity type is N-type, and the second conductivity type is P-type. In some embodiments of the present invention, the first trench 204j for forming the N-type first doping region 210j may be regarded as the N-type trench 204j of the super junction layout unit 620a. Also, the second trench 218j for forming the P-type second doping region 222j can be regarded as the P-type trench 218j of the super junction layout unit 620a. In the above-described semiconductor device layout structure 600d, a plurality of first trenches 204j and second trenches 218j of the super-junction layout unit 620a arranged in an array are staggered.

In some embodiments of the invention, the first doped region 210j as shown in FIG. 4A is formed adjacent to the sidewall of the first trench 204j. In some embodiments of the invention, as shown in FIG. 4A, the second doped region 222j is formed adjacent to the sidewall of the second trench 218j. In some embodiments of the present invention, the top view shape of the first trench 204j and the second trench 218j of each super junction layout unit 620a are opposite to each other. with. For example, the top view 204j and the second groove 218j of each super junction layout unit 620a have a triangular shape in a top view.

4B-4E are top plan views of N-type trenches and P-type trenches of semiconductor device layout structures 600e-600h according to some embodiments of the present invention. As shown in FIGS. 4B-4E, in some embodiments of the present invention, the semiconductor device layout structures 600e-600h include a plurality of super-junction layout units 620b-620e arranged in an array. The configuration of the above-described super junction layout units 620b to 620e is similar to the super junction layout unit 620a of the above-described semiconductor device layout structure 600d as shown in FIG. 4A. One of the differences between the super junction layout unit 620a and the super junction layout units 620b to 620e is: the first trenches 204k~204m and the first trenches of the super junction layout units 620b to 620e (Fig. 4B to 4E) The top view shape of the two trenches 218k to 218m is different from the top view shape of the first trench 204j and the second trench 218j of the super junction layout unit 620a. In some embodiments of the invention, the top view shape of the first trench and the second trench of each superjunction layout unit includes a circle, a triangle, a rectangle, a hexagon, or a polygon.

As shown in FIG. 4B, in some embodiments of the present invention, the top surface 204k and the second trench 218k of the super-junction layout unit 620b of the semiconductor device layout structure 600e have a star shape (star-like). Shape). In some embodiments of the present invention, the super junction layout unit 620b of the semiconductor device layout structure 600e is composed of a first trench 204k and a second trench 218k. In some embodiments of the present invention, the first trench 204k for forming the N-type first doping region 220k may be regarded as the N-type trench 204k of the super junction layout unit 620b. Also, the above-described second trench 218k for forming the P-type second doping region 222k can be regarded as the P-type trench 218k of the super junction layout unit 620b.

As shown in FIG. 4C to FIG. 4D, in some embodiments of the present invention, the first trenches 2041 and the second trenches 2181, 21811 to 21816 of the super-junction layout units 620c-620d of the semiconductor device layout structure 600f-600g The top view shape is a hexagonal shape. In some embodiments of the invention, the superjunction layout units 620c-620d have different configurations. As shown in FIG. 4C, in some embodiments of the present invention, the super junction layout unit 620c of the semiconductor device layout structure 600f is composed of a first trench 2041 and a second trench 2181. In some embodiments of the present invention, the first trench 2041 for forming the N-type first doping region 2201 may be regarded as the N-type trench 2041 of the super junction layout unit 620c. Further, the second trench 2181 for forming the P-type second doping region 2221 can be regarded as the P-type trench 2181 of the super junction layout unit 620c of the semiconductor device layout structure 600f. As shown in FIG. 4D, in some embodiments of the present invention, the super-junction layout unit 620d of the semiconductor device layout structure 600g is composed of a first trench 2041 and six second trenches 21811~21816. The six second trenches 21811~21816 are respectively adjacent to the six different sidewalls 20411~20416 of the first trench 2041. In some embodiments of the present invention, the first trench 2041 for forming the N-type first doping region 2201 may be regarded as the N-type trench 2041 of the super junction layout unit 620d. Moreover, the second trenches 21811~21816 for forming the P-type second doping regions 22211~22216 can be regarded as the P-type trenches 21811~21816 of the super-junction layout unit 620d of the semiconductor device layout structure 600g, as described in The 4D picture shows.

As shown in FIG. 4E, in some embodiments of the present invention, the top view 204m and the second trench 218m of the super-junction layout unit 620e of the semiconductor device layout structure 600h have a rectangular shape. In some embodiments of the present invention, the above semiconductor device layout structure 600h The super junction layout unit 620e is composed of a first trench 204m and a second trench 218m. In some embodiments of the present invention, the first trench 204m for forming the N-type first doping region 220m may be regarded as the N-type trench 204m of the super junction layout unit 620b. Also, the second trench 218m for forming the P-type second doping region 222m can be regarded as the P-type trench 218m of the super junction layout unit 620h as shown in FIG. 4E.

Embodiments of the present invention provide a semiconductor device layout structure. The above semiconductor device layout structure includes a super junction layout unit or a plurality of side-by-side super junction layout units. The super junction layout unit includes an N-type trench, a P-type trench, an N-type first doped region surrounding the N-type trench, and a surrounding P-type trench adjacent to the N-type first a P-type second doped region of the doped region, and the super-junction layout unit is disposed in an active region of the epitaxial layer on the semiconductor substrate. In some embodiments of the invention, in a top view, the P-type trench is configured to conform to a boundary of the N-type trench. A top view shape of the N-shaped trench can be designed with a round-shaped end to reduce electric field concentration. In some embodiments of the present invention, a sidewall portion of the P-type trench of the super junction layout unit (610f) remote from and surrounding the boundary of the N-type trench may have a linear boundary extending in one direction (direction 400) ( As shown in Figure 2A). In some embodiments of the invention, a plurality of P-type trenches may be designed to surround an N-type trench. The plurality of P-type trenches are respectively adjacent to different sidewalls of the N-type trench. In some embodiments of the invention, the semiconductor device layout structure includes a plurality of super junction layout units arranged in an array. A plurality of first trenches and second trenches of the superjunction layout cells arranged in an array are staggered. The semiconductor device layout structure of the embodiment of the present invention provides a consideration of charge balance A layout design of charge-balance concept to provide a power semiconductor device with fast switching time while maintaining the same breakdown voltage.

While the present invention has been described by way of example only, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

300‧‧‧active area

204a~204f‧‧‧first trench

210a~210f‧‧‧first doped area

218a~218f‧‧‧second trench

218a2‧‧‧Internal sidewall section

218a1‧‧‧External side wall section

222a~222f‧‧‧Second doped area

244a~244F‧‧‧rounded ends

400, 402‧‧‧ directions

600a‧‧‧Semiconductor device layout structure

610a~610F‧‧‧Super Junction Layout Unit

D1‧‧‧ distance

Claims (40)

A semiconductor device layout structure comprising: an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region is provided with a plurality of semiconductor elements formed thereon; and a first super-connection The surface layout unit is located in the active region and includes: a first trench; a first doped region having the first conductivity type, the first doped region surrounding the first trench; and a second trench Surrounding the first doped region; and a second doped region having a second conductivity type, the second doped region surrounding the second trench, wherein in a top view, the first trench is The first doped region and the second doped region are laterally spaced from the second trench. The semiconductor device layout structure of claim 1, wherein a top view shape of the first trench comprises an elongated shape, wherein the elongated strip extends in a first direction. The semiconductor device layout structure of claim 2, wherein a top view shape of the second trench comprises a ring shape, wherein the second trench extends in the first direction. The semiconductor device layout structure of claim 1, wherein the first doped region is adjacent to a sidewall of the first trench. The semiconductor device layout structure of claim 4, wherein the second doped region is adjacent to a sidewall of the second trench. The semiconductor device layout structure according to claim 5, wherein the The sidewall of the second trench has an inner sidewall portion proximate the first trench and an outer sidewall portion remote from the first trench. The semiconductor device layout structure of claim 6, wherein the second doped region of the inner sidewall portion of the sidewall adjacent to the second trench is adjacent to the first doped region. The semiconductor device layout structure of claim 5, wherein the sidewall of the first trench is parallel to the sidewall of the second trench, and the sidewall of the second trench is adjacent to the first trench The side wall of the slot. The semiconductor device layout structure of claim 6, wherein the first trench has a rounded end. The semiconductor device layout structure of claim 9, wherein the outer sidewall portion of the second trench adjacent to the rounded end of the first trench is rounded. The semiconductor device layout structure of claim 8, wherein the outer sidewall portion of the second trench is rectangular. The semiconductor device layout structure of claim 1, wherein the active region is formed in an epitaxial layer on the semiconductor substrate, and the first trench and the second trench are formed on the Lei In the crystal layer. The semiconductor device layout structure of claim 12, wherein the epitaxial layer further comprises a termination region surrounding the active region. The semiconductor device layout structure of claim 1, wherein at least one PN junction exists at an interface between the first doped region and the second doped region. For example, the layout structure of the semiconductor device described in claim 1 is further included. The second super-junction layout unit includes: a third trench; a third doped region having the first conductivity type, the first super-junction layout unit a third doped region surrounding the third trench; a fourth trench surrounding the third doped region; and a fourth doped region having the second conductivity type, the fourth doped region surrounding the fourth a trench, wherein in the top view, the third trench is laterally spaced from the fourth trench by the third doped region and the fourth doped region. The semiconductor device layout structure of claim 15, wherein the fourth trench of the second super-junction layout unit overlaps the second trench of the first super-junction layout unit. The semiconductor device layout structure of claim 16, wherein a top view shape of the first and third trenches comprises a strip shape, wherein the strip shape extends in a first direction. The semiconductor device layout structure of claim 17, wherein the first and third trenches are parallel to each other. The semiconductor device layout structure of claim 17, wherein a portion of the fourth trench of the second superjunction layout unit and a portion of the second trench of the first superjunction layout unit Overlap each other and extend in the first direction. The semiconductor device layout structure of claim 17, wherein the first trench has a first length extending along the first direction, and wherein The third groove has a third length extending along the first direction. The semiconductor device layout structure of claim 20, wherein the third length is different from the first length. The semiconductor device layout structure of claim 20, wherein the third length is equal to the first length. The semiconductor device layout structure of claim 17, wherein the third trench is spaced apart from the fourth trench in a second direction, and the second direction is different from the first direction. A semiconductor device layout structure comprising: an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region is provided with a plurality of semiconductor elements formed thereon; and a first super-connection The surface layout unit is located in the active area, and includes: a first trench having a first sidewall and a second sidewall adjacent to the first sidewall; a first doped region having the first conductive a first doped region surrounding the first trench; a second trench adjacent to the first sidewall of the first trench; a second doped region having a second conductivity type, the second a doped region surrounding the second trench, wherein in a top view, the first trench is laterally separated from the second trench by the first doped region and the second doped region; a third trench a trench adjacent to the second sidewall of the first trench; and a third doped region having the second conductivity type, the third doped region surrounding the second trench, wherein in the top view, the first a groove by the first The doped region and the third doped region are laterally spaced from the third trench. The semiconductor device layout structure of claim 24, wherein a first distance between the first trench and the second trench is equal to one between the first trench and the third trench The second distance. The semiconductor device layout structure of claim 24, wherein a top view shape of the first and second trenches comprises a strip shape, wherein the strip shape extends in a first direction. The semiconductor device layout structure of claim 26, wherein the first sidewall of the first trench extends along the first direction, and the second sidewall of the first trench extends along a second direction. And the second direction is different from the first direction. The semiconductor device layout structure of claim 27, wherein the third trench is aligned with the second trench along the second direction. The semiconductor device layout structure of claim 24, wherein the first doped region is adjacent to the first and second sidewalls of the first trench, and the second doped region is adjacent to the first a sidewall of the trench, and the third doped region is adjacent to a sidewall of the third trench. The semiconductor device layout structure of claim 27, wherein the first doped region is adjacent to the second doped region along the second direction. The semiconductor device layout structure of claim 27, wherein the third doped region is adjacent to the first doped region along the first direction. The semiconductor device layout structure of claim 27, wherein a width of the third trench along the second direction is equal to a width of the first trench along the second direction. The semiconductor device layout structure of claim 24, wherein the active region is formed in an epitaxial layer on the semiconductor substrate, and the first trench, the second trench, and the third trench A trench is formed in the epitaxial layer. The semiconductor device layout structure of claim 33, wherein the epitaxial layer further comprises a termination region surrounding the active region. A semiconductor device layout structure comprising: an active region having a first conductivity type, the active region being located above a semiconductor substrate, wherein the active region provides a plurality of semiconductor elements formed thereon; and a super junction layout a unit, located in the active region, comprising: a first trench; a first doped region having the first conductivity type, the first doped region surrounding the first trench; and a second trench close to The first trench; and a second doped region having a second conductivity type, the second doped region surrounding the second trench, wherein in a top view, the first trench is by the first The doped region and the second doped region are laterally spaced from the second trench, and wherein the first sidewall of the first trench is parallel to the second sidewall of the first sidewall adjacent to the first trench a second side wall of the trench. The semiconductor device layout structure of claim 35, further comprising a plurality of the super junction layout units arranged in an array, wherein the first and second trenches of the super junction layout units are staggered . The semiconductor device layout structure of claim 35, wherein a top view shape of the first and second trenches of the super junction layout unit This is the same. The semiconductor device layout structure of claim 35, wherein a top view shape of the first and second trenches comprises a circle, a triangle, a rectangle, a hexagon or a polygon. The semiconductor device layout structure of claim 35, wherein the active region is formed in an epitaxial layer on the semiconductor substrate, and the first trench and the second trench are formed on the Lei In the crystal layer. The semiconductor device layout structure of claim 39, wherein the epitaxial layer further comprises a termination region surrounding the active region.