TWI534948B - Method of forming isolation structure - Google Patents

Description

Method of forming an isolation structure

This invention relates to a method of forming an isolation structure, and more particularly to a method of forming an isolation structure having stress.

In the modern information society, micro-processing systems composed of integrated circuits (ICs) have long been widely used in all aspects of life, such as automatic control of household appliances, mobile communication devices, personal computers, etc. The use of the circuit. With the increasing advancement of technology and the imagination of human society for electronic products, various electronic products with integrated circuits have also developed in the direction of more yuan, more precision and smaller.

In the current semiconductor process, localized oxidation isolation (LOCOS) or shallow trench isolation (STI) is generally used to isolate electronic components to avoid mutual interference between electronic components. phenomenon. However, as the design and manufacturing line width of semiconductor wafers become finer, the pits, crystal defects, and bird's beak lengths generated in the LOCOS process are too long. The characteristics of the semiconductor wafer will be greatly affected, and the field oxide layer produced by the LOCOS method occupies a large volume and affects the integration of the entire semiconductor wafer. Therefore, in a submicron semiconductor process, the size is small, and the accumulation of semiconductor wafers can be improved. 遂 has become a widely used isolation technology.

Typical shallow trench isolation is fabricated by making a recess between the electronic components on the surface of the wafer and filling the dielectric material to create an electrical isolation effect. However, as the size of semiconductor components is shrinking to near physical limits, different sizes of shallow trench isolation structures and active regions have severely affected the electrical performance and process quality of electronic components.

Therefore, a shallow trench isolation with good quality and capable of improving the electrical performance of electronic components has become a target of research.

The present invention thus provides a method of forming an isolation structure that can form an isolation structure with stress to enhance the electrical performance of the electronic component.

The present invention provides a method of forming an isolation structure. First, a substrate is provided, then a trench is formed in the substrate, and a semiconductor layer is formed on the surface of the trench. The semiconductor layer is then subjected to a nitridation process to form a nitride layer in the semiconductor layer. Finally, an insulating layer is filled in the trench.

The invention mainly forms a semiconductor layer in the trench and forms a nitride layer in the semiconductor layer. By adjusting appropriate parameters, the nitride layer can have appropriate stress, and the electrical component of the electronic component surrounded by the isolation structure can be effectively enhanced. Sex.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1 to FIG. 10 , which are schematic diagrams showing the steps of forming an isolation structure according to the present invention. As shown in FIG. 1, a substrate 300 is preferably provided, preferably a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, carbonization. A silicon carbide substrate or a silicon-on-insulator substrate (SOI substrate). A patterned mask layer 302 is then formed over the substrate 300, wherein the patterned mask layer 302 has at least one opening 304 to expose the underlying substrate 300. In one embodiment of the present invention, the patterned mask layer 302 is, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), or Applied Materials. An advanced pattern film (APF), or any combination of the above, or any combination of the above and other materials. In another embodiment of the present invention, a liner layer (not shown) may be selectively formed between the substrate 300 and the patterned mask layer 302, such as a germanium dioxide layer.

As shown in FIG. 2, a mask 306 is formed in the substrate 300 by using the patterned mask layer 302 as a mask. The method of forming the trench 306 can be an anisotropic etch process, such as a dry etch process. Alternatively, the method of forming the trench 306 is also a non- The isotropic etching process plus an isotropic etching process, such as a dry etching process plus a wet etching process. The depth of the trench 306 formed can be adjusted depending on product requirements. If the trench 306 is followed by shallow trench isolation, the trench 306 may have a depth of 3000 Å to 4000 angstroms, but is not limited thereto.

As shown in FIG. 3, depending on the design and process of the different products, after the trench 306 is formed, the patterned mask layer 302 (and the underlying liner layer) can be selectively subjected to a pull back process. To enlarge the opening 304 of the patterned mask layer 302 such that the opening 304 becomes the opening 305, exposing the surface of the substrate 300 other than the trench 306 (as in Figure 3, area A).

As shown in FIG. 4, a semiconductor layer 308 is formed on the substrate 300. In one embodiment of the present invention, the semiconductor layer 308 is formed by an epitaxial process such as selective epitaxial growth (SEG), so that the formed position is on the surface of the exposed substrate 300, That is, on the substrate 300 on the surface of the trench 306 and on the substrate 300 (i.e., region A) that is not covered by the patterned mask layer 302 outside the trench 306. In one embodiment of the present invention, the material of the semiconductor layer 308 is, for example, germanium, germanium, carbon, or a combination thereof, and the thickness thereof is generally between 20 angstroms and 80 angstroms, preferably. It is 50 angstroms. In addition, before performing the epitaxial process, it is preferable to perform a cleaning step on the surface of the substrate 300 to remove oxides such as cerium oxide on the surface of the substrate 300 in the trench 306 to improve the quality of the subsequent epitaxial process. It should be noted that, in another embodiment, as shown in FIG. 5, if the mask layer 302 is patterned before the semiconductor layer 308 is formed, the semiconductor layer is not subjected to the retracting process. The 308 layer does not extend over the surface of the substrate 300 outside of the trench 306, but only in the trench 306.

As shown in FIG. 6, in another embodiment of the present invention, the semiconductor layer 308 can also be formed by a deposition process, such as an Atomic Layer Deposition (ALD) process. At this time, the semiconductor layer 308 is conformally formed along the patterned mask layer 302, the surface of the substrate 300 not covered by the patterned mask layer 302, and the surface of the trench 308, and formed near the region A of the opening 305. A step structure. In this embodiment, the semiconductor layer 308 may be poly-silicon or amorphous silicon. In another embodiment of the present invention, as shown in FIG. 7, if the mask layer 302 is patterned before the semiconductor layer 308 is formed and the recess process is not performed, the semiconductor layer 308 layer formed by the deposition process is not A ladder structure is formed at the opening 304.

After the semiconductor layer 308 is formed in the various manners described above, a semiconductor process 308 is followed by a nitridation process 310 as shown in FIG. In one embodiment of the invention, a portion of the semiconductor layer 308 near the surface is nitrided to form a nitride layer 312, such as a tantalum nitride (SiN) layer. In another embodiment of the invention, all of the semiconductor layer 308 is nitrided to form the nitride layer 312. The nitridation process 310 includes various steps of implanting nitrogen atoms. In one embodiment of the invention, the nitridation process comprises a decoupled plasma nitridation (DPN) and an annealing step. For example, the plasma nitriding treatment comprises introducing nitrogen gas in a plasma environment, performing at normal temperature for 10 seconds to 60 seconds, and subsequent annealing steps continuously introducing nitrogen gas. And it is carried out in 800 degrees Celsius to 1100 degrees Celsius. After the nitridation treatment, the formed nitride layer 312 will have a stress such as tensile stress or compressive stress. In one embodiment of the invention, if the semiconductor layer 308 is germanium, the nitride layer 312 after the nitridation process 310 will have tensile stress.

As shown in FIG. 9, an insulating layer 314, such as a layer of germanium dioxide, is then formed over the substrate 300 to completely fill the trenches 308. In one embodiment of the present invention, the method of forming the insulating layer 314 is, for example, a chemical vapor deposition (CVD) process, and the insulating layer 314 may be a single layer or a multilayer structure of an insulating material layer. After the insulating layer 314 is formed, a dense densification step may be selectively performed, for example, in an environment of 1000 degrees Celsius or more, the insulating layer 314 is densely filled in the trench 306.

As shown in FIG. 10, a planarization process, such as one or more chemical mechanical polish (CMP) processes, one or more etching processes, or a combination of the above, is performed to polish the insulating layer 314. To the patterned mask layer 302. The patterned mask layer 302 is then removed. As a result, the insulating layer 314, the nitride layer 312, and the semiconductor layer 308 together form an isolation structure 316.

The isolation structure 316 of the present invention can be used, for example, as a shallow trench isolation (STI), and since the nitride layer 312 can provide stress, it can be combined with other stress-bearing elements to form a selective strain system (selective strain system). Scheme, SSS). For example, in the foregoing embodiment, the semiconductor layer 308 is 矽 The nitride layer 312 can provide tensile stress, thereby enhancing the electrical performance of the N-type metal oxide semiconductor (MOS) surrounded by the isolation structure 316.

Another feature of the present invention is that the oxide liner layer is formed in an oxidized manner on the surface of the trench 306 as compared with the prior art, which generally consumes the material in the substrate 300 to affect the electrical properties of the device. The semiconductor layer 308 is formed on the surface of the trench 306 as a sacrificial layer, and then the sacrificial layer is nitrided into a pad of appropriate stress, so that the semiconductor material in the substrate 300 is not consumed. In addition, a cleaning step is performed to remove oxides on the surface of the trench 308 prior to forming the semiconductor layer 308. Therefore, the isolation structure 316 of the present invention preferably has no oxide between the semiconductor layer 308 and the substrate 300. The nitride layer 312 (or the nitride layer 312 plus the semiconductor layer 308) is fully relied upon as a spacer for the isolation structure and provides appropriate stress. In addition, as shown in the embodiments of FIGS. 4 and 6, the semiconductor layer 308 and the nitride layer 312 formed further extend to the substrate 300 other than the trench 306 in conjunction with the post-rolling process of the patterned mask layer 302. This helps to increase the stress of the nitride layer 312.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300‧‧‧Base

302‧‧‧ patterned mask layer

304‧‧‧ openings

305‧‧‧ openings

306‧‧‧ Ditch

308‧‧‧Semiconductor layer

310‧‧‧nitriding treatment

312‧‧‧ nitride layer

314‧‧‧Insulation

316‧‧‧Isolation structure

1 to 10 are schematic views showing the steps of forming an isolation structure of the present invention.

300‧‧‧Base

302‧‧‧ patterned mask layer

306‧‧‧ Ditch

308‧‧‧Semiconductor layer

310‧‧‧nitriding treatment

312‧‧‧ nitride layer

Claims (20)

A method of forming an isolation structure includes: providing a substrate; forming a trench in the substrate; forming a semiconductor layer on a surface of the trench; performing a nitridation process on the semiconductor layer to form a semiconductor layer in the semiconductor layer a nitride layer, the nitride layer formed directly contacts the semiconductor layer; and the trench is filled with an insulating layer. The method of forming an isolation structure according to claim 1, wherein the semiconductor layer comprises ruthenium, osmium or carbon. The method of forming an isolation structure according to claim 1, wherein the step of forming the semiconductor layer comprises an epitaxial process. The method of forming an isolation structure according to claim 1, wherein the step of forming the semiconductor layer comprises a deposition process. The method of forming an isolation structure according to claim 1, wherein the forming the trench comprises: forming a patterned mask layer on the substrate; and masking the patterned mask layer to The trench is formed in the substrate. The method of forming an isolation structure according to claim 5, wherein the semiconductor layer is formed only on one surface of the trench. The method of forming an isolation structure according to claim 5, wherein the semiconductor layer is formed on the patterned mask layer and on a surface of the trench. The method for forming an isolation structure according to claim 5, further comprising performing a retracting process on the patterned mask layer before forming the semiconductor layer. The method of forming an isolation structure according to claim 8 wherein the semiconductor layer is formed only on one surface of the trench and on the substrate outside the trench and not covered by the patterned mask layer. The method of forming an isolation structure according to claim 8, wherein the semiconductor layer is formed on the patterned mask layer, on a surface of the trench, and outside the trench and is not patterned by the mask layer. Covered on the substrate. The method of forming an isolation structure according to claim 1, wherein the semiconductor layer has a thickness of 20 angstroms to 80 angstroms. The method of forming an isolation structure according to claim 1, wherein the nitridation process comprises a plasma nitridation process and an annealing process. The method of forming an isolation structure according to claim 12, wherein the plasma nitriding treatment process is performed at room temperature for 10 seconds to 60 seconds. The method of forming an isolation structure according to claim 12, wherein the annealing process comprises introducing nitrogen gas in an environment of 800 degrees Celsius to 1100 degrees Celsius. The method of forming an isolation structure according to claim 1, wherein all of the semiconductor layers become the nitride layer after the nitridation process. A method of forming an isolation structure as described in claim 1, wherein after the nitridation process, a portion of the semiconductor layer becomes the nitride layer and the semiconductor layer adjacent to the substrate remains. The method of forming an isolation structure according to claim 1, wherein the nitride layer has a stress. A method of forming an isolation structure as described in claim 17 of the patent application, wherein the stress is a tensile stress. The method of forming an isolation structure according to claim 18, wherein the isolation structure is isolated as a shallow trench, and the shallow trench isolation surrounds an N-type MOS transistor. The method of forming an isolation structure according to claim 1, wherein before the forming the semiconductor layer, the substrate is further subjected to a cleaning step to remove oxides on the surface of the substrate.