TWI533377B - Stress film forming method and stress film structure - Google Patents

Description

Stress film forming method and stress film structure

The present invention relates to a stress film forming method and a stress film structure, and more particularly to a stress film forming method and a stress film structure applied in a semiconductor process.

As the gate length shrinks to encounter bottlenecks and new materials have not yet been discovered and validated, mobility adjustment engineering has become an important contributor to improving the performance of integrated circuits. For example, the channel lattice strain of MOS transistors has been commonly used to enhance mobility, where the lattice strain enthalpy can provide a hole mobility and electron mobility of approximately no lattice strain. The 矽 is 4 times and 1.8 times.

Therefore, the designer can modify the structure of the transistor to apply tensile stress to the channel of the N-channel MOS transistor, or apply compressive stress to the channel of the P-channel MOS transistor. ). Because the stretching channel can improve the mobility of electrons, the compression channel can improve the mobility of the hole. It is usually covered with a layer of tantalum nitride (SiN) film after the fabrication of the metal oxide semi-transistor element, and the high stress characteristic of the tantalum nitride film itself is used to control the stress in the electron channel.

Under different deposition conditions, the tantalum nitride film can be controlled into a tensile stress film or a compressive stress film. For example, a compressive stress film for enhancing the hole mobility of the P channel can be transparent chemical vapor deposition. The method (CVD) is used, but the tensile stress film for enhancing the electron mobility of the N channel needs to be completed after a plurality of deposition-curing process cycles. Therefore, how to integrate stress films with different characteristics into a complementary metal oxide semi-transistor (CMOS) process is the main purpose of the development of this case.

It is an object of the present invention to provide a stress film forming method for use in a semiconductor process, the method comprising the steps of: providing a substrate having a first electrical channel MOS transistor and a second electrical property over the substrate Channel gold oxide semi-transistor; performing at least one deposition-hardening process on the first electrical channel MOS semi-transistor and the second electrical channel MOS semi-transistor to form a hardened stress film; and above the hardened stress film Another deposition process is performed to form an uncured stress film, and the hardened stress film and the uncured stress film are formed into an unexposed slit stress film.

In a preferred embodiment of the present invention, the substrate is a germanium substrate, the first electrical channel MOS transistor is an N-channel MOS transistor, and the second electrical channel MOS transistor is A P-channel MOS transistor, the material of the hardened stress film and the uncured stress film is tantalum nitride.

In a preferred embodiment of the invention, the deposition-hardening process comprises the steps of: performing a deposition process over the first electrical channel MOS semi-transistor and the second electrical channel MOS semi-transistor Forming a stress film; performing a hardening process to convert the stress film into a hardened stress film; repeating the above two steps at least once.

In a preferred embodiment of the present invention, the deposition process in the deposition-hardening process and the other deposition process are chemical vapor deposition processes, and the hardening process in the deposition-hardening process is an ultraviolet curing process.

In a preferred embodiment of the present invention, before the performing the deposition-hardening process, the method further comprises the step of depositing an etch barrier layer over the substrate to form the hardened stress film on the surface of the etch barrier layer.

In a preferred embodiment of the present invention, the stress film forming method further comprises the step of forming a niobium oxide cap layer on the surface of the non-exposed slit stress film.

Another object of the present invention is to provide a stress film forming method for use in a semiconductor process, the method comprising the steps of: providing a substrate having a first electrical channel MOS transistor and a second electrical property above the substrate Channel gold oxide semi-transistor; performing at least one deposition-hardening process on the first electrical channel MOS semi-transistor and the second electrical channel MOS semi-transistor to form a hardened stress film; Another deposition process forms an uncured stress film; and the uncured stress film is subjected to a half-hardening process, and the processing time of the semi-hardening process is shorter than the processing time of one of the deposition-hardening processes to make the uncured stress The film is transformed into a semi-hardened stress film, and the semi-hardened stress film and the hardened stress film constitute an unexposed slit stress film.

A further object of the present invention is to provide a stress film structure for applying a substrate having a first electrical channel MOS semi-transistor and a second electrical channel MOS transistor, wherein the stress film structure comprises: at least A hardened stress film is completed over the first electrical channel MOS semi-electrode; and an uncured stress film is formed on the surface of the hardened stress film for forming an unexposed slit stress film with the hardened stress film.

Another object of the present invention is to provide a stress film structure for applying a substrate having a first electrical channel MOS transistor and a second electrical channel MOS transistor, wherein the stress film structure comprises: at least A hardened stress film is completed over the first electrical channel MOS semi-electrode; and a semi-hardened stress film is formed on the surface of the hardened stress film for forming an unexposed slit stress film with the hardened stress film.

Referring to FIG. 1A to FIG. 1E, the applicant develops a partial flow chart of a method for forming a stress film in a complementary metal oxide semiconductor (CMOS) process. First, FIG. 1A shows a schematic view of a structure in which an N-channel MOS transistor 11 and a P-channel MOS transistor 12 are respectively formed on the ruthenium substrate 1, in which a shallow trench isolation structure is completed in the ruthenium substrate 1 (Shallow Trench) Isolation (STI) 19 is used to isolate adjacent components. Next, a layer of yttrium oxide is deposited over the ruthenium substrate 1 on which the N-channel MOS transistor 11 and the P-channel MOS transistor 12 have been completed as the etch stop layer 100, and then deposited on the surface of the etch barrier layer 100. The first stress film 101.

In order to apply tensile stress to the channel of the N-channel MOS transistor, the first stress film (for example, tantalum nitride film) 101 is cured to make the first stress. The volume of the film 101 is contracted by about 10% to be converted into a first hardened stress film 1011, and its cross-sectional view is as shown in Fig. 1B. In order to increase the tensile stress, a plurality of deposition-curing process cycles can be used to complete the four-layer hardened stress film to superimpose the desired multilayer tensile stress film 10, for example, with four depositions ( The deposition)-curing cycle is performed to complete the tensile stress film 10 shown in FIG. 1C, and then a silicon oxide cap layer 13 is formed on the surface of the tensile stress film 10. However, as is apparent from Fig. 1C, since the above-described hardening process causes the tensile stress film 10 to contract, a seam 109 as shown in the drawing is produced. The above four deposition-curing cycles are just one example. In order to achieve greater stress requirements or to reduce the spacing between components, it is of course possible to use more than four cycles or at least one cycle to complete the process. The stress film 10 is stretched.

Next, as shown in FIG. 1D, after coating a photoresist layer 14 on the surface of the yttrium oxide cap layer 13, the photoresist layer 14 above the P-channel MOS transistor 12 is removed by a photomask lithography process to leave an N-channel. The photoresist layer 14 above the gold oxide semiconductor 11 is filled with the photoresist material when the photoresist layer 14 is formed, and the photoresist material in the slit 109 is not easily removed and overflows. The photoresist layer 14 above the P-channel MOS transistor 12 cannot be removed.

Therefore, when the above phenomenon causes the subsequent process to remove the multilayer tensile stress film 10 above the P-channel MOS transistor 12, the multilayer tensile stress film 10 cannot be removed, thereby forming a residue as shown in FIG. 1E. The object 108 causes troubles in subsequent coverage of the compressive stress film to provide the compressive stress required for the P-channel MOS transistor 12.

Thus, the Applicant has proposed another embodiment to ameliorate this problem. The main concept of this embodiment is to avoid the last hardening process in the above four deposition-hardening process cycles. The cross-sectional view after the completion of the third deposition-hardening process is as shown in FIG. 2A, wherein the multi-layer hardening stress film 203 is a three-layer hardening stress film (for example, a tensile stress film) which is separately formed after three deposition-hardening processes. The finished product that is superimposed. Then, a fourth deposition process is performed on the surface of the multilayer hardening stress film 203 to form an uncured stress film 204 to form a tensile stress-free exposed slit stress film 20, and then directly on the non-exposed slit stress film 20 A ruthenium oxide cap layer 23 is formed on the surface to thereby produce a structure as shown in FIG. 2B. Since the uncured stress film 204 is not subjected to the final hardening process, it does not shrink again, so the slit 209 is deposited by the last deposition process. The uncured stress film 204 is covered without being exposed, so that the ruthenium oxide cap layer 23 covering the same does not form a slit. The above three deposition-curing cycles are just one example, and the present invention can of course use more than three cycles or at least one cycle in order to achieve greater stress requirements or to accommodate increasingly smaller spacing between components. Match at least one process with no deposition and no hardening.

Next, as shown in FIG. 2C, after the photoresist layer 24 is coated on the surface of the yttrium oxide cap layer 23, the photoresist layer 24 above the P-channel MOS transistor 22 is removed by a photomask lithography process to leave the N-channel gold. The photoresist layer 24 above the oxygen semiconductor 21, but since the photoresist material has been unable to fill the slit 209, the photoresist layer 24 above the P-channel MOS transistor 22 can be completely removed.

After the non-exposed slit stress film 20 is etched by the photoresist layer 24 remaining over the N-channel MOS transistor 21 and stopped in the etch barrier layer 200, a structural diagram as shown in FIG. 2D is formed. The non-exposed slit stress film 20 above the P-channel MOS transistor 22 can be completely removed due to no longer being affected by the residue, so that the subsequent covering of the compressive stress film (not shown in this figure) will not be affected. The compressive stress required for the P-channel MOS transistor 22 is then successfully provided.

In addition, the stress film forming method of the present invention can also be changed. For example, after the uncured stress film 204 is formed on the surface of the multilayer hard stress film 203 in the manner of FIGS. 2A and 2B, the uncured stress film 204 may be subjected to a half-hardening process as shown in FIG. The time is shorter than the processing time of one of the hardening processes in the deposition-hardening process, and the unhardened stress film is converted into the semi-hardening stress film 205, that is, the shrinkage degree of the semi-hardened stress film 205 is not so large that the slit is exposed. The semi-hardened stress film 205 and the multi-layer hardened stress film 203 may still form an unexposed slit stress film 30.

In the above embodiments, the deposition process in the deposition-hardening process may be a chemical vapor deposition process, and the hardening process in the deposition-hardening process is an ultraviolet curing process.

In summary, after the technology of the present invention is improved, the problem of the conventional means can be effectively improved. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1. . .矽 substrate

19. . . Shallow trench isolation structure

11. . . N-channel MOS semi-transistor

12. . . P-channel MOS semi-transistor

100. . . Etch barrier

101. . . First stress film

1011. . . First hardening stress film

10. . . Multilayer tensile stress film

13. . . Cerium oxide cap

109. . . Slit

14. . . Photoresist layer

108. . . the remains

2. . .矽 substrate

203. . . Multilayer hardening stress film

204. . . Unhardened stress film

209. . . Slit

20. . . No exposed slit stress film

200. . . Etch barrier

twenty three. . . Cerium oxide cap

twenty four. . . Photoresist layer

30. . . No exposed slit stress film

205. . . Semi-hardened stress film

1A-1E are partial schematic diagrams of the applicant's development of a stress film formation method for use in a complementary metal oxide semiconductor (CMOS) process.

2A-2D are partial flow diagrams of the applicant's development of another method of forming a stress film for use in a complementary metal oxide semiconductor (CMOS) process.

Figure 3: A schematic representation of the stress film structure developed by the applicant for another stress film formation process applied in a complementary metal oxide semi-transistor (CMOS) process.

2. . .矽 substrate

203. . . Multilayer hardening stress film

204. . . Unhardened stress film

209. . . Slit

20. . . No exposed slit stress film

twenty three. . . Cerium oxide cap

200. . . Etch barrier

Claims (12)

A stress film forming method is applied to a semiconductor process, the method comprising the steps of: providing a substrate having a first electrical channel MOS transistor and a second electrical channel MOS transistor; Forming a hardening stress film by performing at least one deposition-hardening process on the first electrical channel MOS transistor and the second electrical channel MOS transistor; and performing another curing over the hardening stress film The deposition process forms an uncured stress film, and the hardened stress film and the uncured stress film form an unexposed slit stress film. The method for forming a stress film according to claim 1, wherein the substrate is a germanium substrate, and the first electrical channel MOS transistor is an N-channel MOS transistor, and the second electrical channel The gold-oxide semi-transistor is a P-channel MOS semi-electrode, and the material of the hardened stress film and the uncured stress film is tantalum nitride. The stress film forming method of claim 1, wherein the deposition-hardening process comprises the steps of: performing a deposition process on the first electrical channel MOS semi-transistor and the second electrical channel A stress film is formed on the gold oxide semi-electric crystal; the stress film is converted into a hardening stress film by a hardening process; and the above two steps are repeated at least once. The method for forming a stress film according to claim 1, wherein the deposition process in the deposition-hardening process and the another deposition process are chemical vapor deposition processes, and the hardening in the deposition-hardening process The process is an ultraviolet curing process. The method for forming a stress film according to claim 1, wherein the depositing and hardening process further comprises the steps of: depositing an etch barrier layer over the substrate to form the hardened stress film on the etch barrier layer; On the surface. The method for forming a stress film according to claim 1, further comprising the step of forming a niobium oxide cap layer on the surface of the non-exposed slit stress film. A stress film forming method is applied to a semiconductor process, the method comprising the steps of: providing a substrate having a first electrical channel MOS transistor and a second electrical channel MOS transistor; Forming a hardening stress film by performing at least one deposition-hardening process on the first electrical channel MOS transistor and the second electrical channel MOS transistor; performing another deposition over the hardening stress film Forming an uncured stress film; and performing a half-hardening process on the uncured stress film, the processing time of the semi-hardening process being shorter than the processing time of one of the hardening processes in the deposition-hardening process, so that the uncured stress The film is converted into a semi-hardened stress film, and the semi-hardened stress film and the hardened stress film constitute an unexposed slit stress film. The method for forming a stress film according to claim 7, wherein the substrate is a germanium substrate, and the first electrical channel MOS transistor is an N-channel MOS transistor, and the second electrical channel The gold-oxygen semi-transistor is a P-channel MOS transistor, and the hardened stress film, the uncured stress film and the material of the semi-hardened stress film are all tantalum nitride. The stress film forming method of claim 7, wherein the deposition-hardening process comprises the steps of: performing a deposition process on the first electrical channel MOS semi-transistor and the second electrical channel A stress film is formed on the gold oxide semi-electric crystal; the stress film is converted into a hardening stress film by a hardening process; and the above two steps are repeated at least once. The method for forming a stress film according to claim 7, wherein the deposition process in the deposition-hardening process and the another deposition process are chemical vapor deposition processes, and the hardening in the deposition-hardening process The process is an ultraviolet curing process. The stress film forming method of claim 7, wherein the depositing and hardening process further comprises the steps of: depositing an etch barrier layer over the substrate to form the hardened stress film on the etch stop layer; On the surface. The stress film forming method of claim 7, further comprising the step of forming a niobium oxide cap layer on the surface of the non-exposed slit stress film.