TWI530957B - Flash memory, management method and management program of bad block - Google Patents

Description

Flash memory, management method and management program for bad blocks

The present invention relates to a (Not AND, NAND) type flash memory, and more particularly to a method of managing a bad block.

Defective elements produced during the manufacturing phase of the flash memory are saved by replacing the memory elements of the redundant area with a redundancy scheme. On the other hand, even a memory element that is determined to be normal at the time of shipment may become a defective element due to repeated programming or erasing. That is, a memory element is generated such that even if a fixed number of stylized pulses are applied, the threshold value of the memory element cannot be converged within a desired distribution range, and even if a fixed number of erase pulses are applied, The threshold of the memory element cannot be converged within the desired distribution range. The so-called bad block management is adopted in the flash memory, that is, the block including such a bad memory element is identified as a bad block, and the bad block is replaced with another normal block by the block unit. (Patent Document 1).

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2013-145545

The operation flow of the existing bad block management is shown in FIG. When page programming is performed in the flash memory, a stylized pulse is applied to the word line of the selected page, and then a threshold is determined for determining the threshold of the memory cell. If the stylization is insufficient, the previous application is performed. Only stylized pulses of high ΔVpgm. Further, when erasing of the selected block is performed, an erase pulse is applied to the well or the substrate, and verification is performed next, and if the erasing is insufficient, an erase pulse (S10) which is higher than the previous only ΔVers is applied. This stylization is known as the Incremental Step Pulse Program (ISPP) method, which is used as an Incremental Step Pulse Erase (ISPE) method. know.

In the flash memory, the status at the time of stylization or erasing is maintained in the management memory (S12). In the state, for example, it is determined that the verification of the selected page is determined to be unacceptable by applying a predetermined number of stylized pulses, or that the verification of the selected block is judged to be unqualified or verified by applying a predetermined number of erase pulses. The final result is unqualified.

The state stored in the management memory is used to determine whether or not there is a bad block (S14). The determination of whether or not there is a bad block is performed, for example, by an external controller transmitting a command to the flash memory, or by a program loaded in the flash memory itself. If it is determined that there is a bad block, the bad block management unit performs address conversion in such a manner that the access to the bad block becomes access to the normal spare block (S16).

2(A) to 2(B) are diagrams for explaining details of the conventional bad block management. The flash memory includes: a bad block management unit 10 that performs management of bad blocks; a look-up table 20 that stores addresses for converting the address of the bad block into a normal spare block. Address conversion information; word line selection circuit 30, selecting a block based on row address information and page selection; and a memory array 40 comprising a plurality of blocks. M1 of the memory array 40 is a memory area allocated for use by a user, and SB is a spare area prepared to replace a bad block.

The bad block management unit 10 determines the presence or absence of the bad block described in step S14 of FIG. 1 based on an external command or a program loaded on itself. For example, as shown in FIG. 2(B), the stylization (writing) of the page Pi of the block 5 is performed, but the final verification is unacceptable. The stylized state of the page Pi is stored in the management memory (not shown).

When the bad block management unit 10 refers to the management memory and determines that the block 5 is a bad block because the defective page Pi is included, the block 5 is allocated to the block in the blank area in the spare area SB, for example, the block 1004. At this time, the bad block management unit 10 writes the address conversion information to the lookup table 20 for converting the address of the access to the bad block 5 to the access to the spare block 1004. Address. FIG. 3 is a diagram showing an example of a lookup table. In the lookup table, the address of the spare block 1004 in which the address of the bad block 5 is replaced and the address of the bad block 5 is replaced is established. Typically, the flash memory is provided with a logical address from an external controller, so the logical address of the bad block 5 and the spare block 1004 is stored in the lookup table.

When reading, programming (writing) or erasing, the word line selection circuit 30 refers to the lookup table to determine whether the input row address is consistent with the address of the bad block, and if it is consistent, the input is entered. The row address is converted to the address of the spare block and converted into a physical address, and the block select signal BSEL for selecting the block 1004 is output. Further, as long as a read or program (write) operation is performed, the page within the selected block 1004 is selected.

However, the following problems exist in the management method of the existing bad block. As shown in FIG. 2(B), if the defect of the page Pi (for example, in the verification of the stylized operation is unsatisfactory), it is determined that the block 5 is a bad block, and the access to the block 5 is converted into a direction. When the block 1004 is accessed, the data of the page P0 to the page Pi-1 and the page Pi+1 to the page Pn that have been written to the block 5 cannot be used. If you want to use this data, you must execute a file management system (system) that is different from the bad block management method, and copy the page P0~page Pi-1 and page Pi+1~page Pn of block 5 ( Copy) to block 1004, which necessitates complex processing.

It is an object of the present invention to provide a flash memory, a management method and a management program for a bad block that solve the problems of the conventional bad block management method.

The bad block management method of the inverse type flash memory of the present invention comprises the steps of: determining whether there is a bad block in the memory array; and determining whether there is a bad block, determining whether a part of the bad block is There is a bad page; and when it is determined that there is a bad page in a part of the bad block, it is set to convert the bad block and the bad block. Address translation information for the page.

Preferably, the step of setting is to set address conversion information for converting a first page including a bad page into a corresponding page in the spare block, and the second page not containing the bad page is in the bad block. The way of access sets the address translation information. Preferably, the step of setting is to divide the bad block into two page groups by using a bad page as a boundary, and setting an address conversion for converting a page group including the bad page into a corresponding page of the spare block. News. Preferably, the step of setting is to store the address translation information in a rewritable non-volatile memory. Preferably, the bad block management method further comprises the step of integrating the bad block and the spare block into one block. Preferably, the step of integrating is performed in response to erasing bad blocks. Preferably, the step of integrating is performed by executing a command.

The bad block management program of the present invention is a program executed by the reverse flash memory, and includes the following steps: determining whether there is a bad block in the memory array; determining that there is a bad block, determining that the bad area is present Whether there is a bad page in a part of the block; and when it is determined that there is a bad page in a part of the bad block, the address conversion information for converting the page in the bad block and the bad block is set.

The inverse type flash memory of the present invention includes: a memory array including a plurality of blocks; a storage unit storing a state when the memory array is programmed and erased; and a first determining unit based on the a state of determining whether there is a bad block in the memory array; and when determining that there is a bad block, the second determining means determines whether a part of the bad block has a bad page based on the state; and setting a component, When it is determined that there is a bad page in a part of the bad block, it is set to convert the bad block. Translate information with the address of the page within the bad block.

Preferably, the flash memory further comprises: an input component, input address information; a third determining component, determining whether the address information from the input component is consistent with the bad block; and converting the component, determining that the bad zone is When the blocks are consistent, the address information is converted according to the address conversion information. Preferably, the flash memory further includes a fourth determining component that determines whether the address information from the input component matches the bad page, and when the determination is consistent with the bad page, the converting component converts the information according to the address. And converting the address information. Preferably, when the conversion component determines that the address information does not match the bad page by the fourth determining component, the converting component does not perform address translation on the address information according to the address conversion information.

According to the present invention, in the case where it is determined that a part of the bad block is a bad page, the address conversion information for converting the page in the bad block is set, so that it is possible to continue to use the non-bad page in the bad block. Information on the page.

10‧‧‧Bad Block Management Department

20, 152‧‧‧ lookup table

30‧‧‧Word line selection circuit

40‧‧‧ memory array

100‧‧‧flash memory

110‧‧‧Memory array

120‧‧‧Input and output buffers

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

154‧‧‧Manage memory

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧ column selection circuit

190‧‧‧Internal voltage generation circuit

Ax‧‧‧ address information

Ay‧‧‧Listing address information

BLK (0), BLK (1), ..., BLK (m) ‧ ‧ blocks

BSEL‧‧‧ block selection signal

C1, C2, C3‧‧‧ control signals

GBL‧‧‧ bit line

M1‧‧‧ memory area

MC0~MC31‧‧‧ memory unit

NU‧‧‧string unit

P0~Pi-1, Pi~Pn‧‧‧ page

SB‧‧ ‧ spare area

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

TD, TS‧‧‧ select transistor

Vers‧‧‧ erase voltage

Vpass‧‧‧ turn-on voltage

Vprog‧‧‧ stylized voltage

Vread‧‧‧ reading voltage

WL‧‧‧ word line

FIG. 1 is a view showing an operational flow of bad block management of a conventional flash memory.

2(A) to 2(B) are diagrams for explaining the conventional bad block management.

FIG. 3 is a diagram showing an example of a lookup table used for conventional bad block management.

4 is a block diagram showing a configuration example of a flash memory according to an embodiment of the present invention.

Fig. 5 is a circuit diagram showing a configuration of a reverse side of a memory cell array according to an embodiment of the present invention.

Fig. 6 is a view showing an example of a voltage applied to each portion in the stylization of the flash memory of the embodiment.

Fig. 7 is a flow chart showing the operation of establishing a look-up table (LUT) in the bad block management of the flash memory of the embodiment.

8(A) to 8(B) are diagrams showing an example of a lookup table of the present embodiment.

Fig. 9 is a flow chart for explaining the operation of the flash memory of the embodiment.

Figure 10 is a flow chart illustrating the operation of the defragmentation of the present embodiment.

11(A) to 11(B) are diagrams for explaining an example of updating of the reorganization and lookup table of the present embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In a preferred embodiment of the invention, a reverse flash memory is exemplified. In addition, the drawing emphasizes the display of each part for easy understanding, and it should be noted that the scale of the actual device is different.

[Examples]

Fig. 4 is a block diagram showing the configuration of a flash memory according to an embodiment of the present invention. However, the configuration of the flash memory shown here is an example, and the present invention is not necessarily limited to such a configuration.

The flash memory 100 of the present embodiment is configured to include a memory array 110 that forms a plurality of memory cells arranged in a matrix, and an input/output buffer 120 connected to the external input/output terminal I/O and held Input and output data; an address register 130, receiving address data from the input and output buffer 120; a data register 140 holding input and output data; and a controller 150 based on the input/output buffer 120 Command data and external control signals (chip enable or address latch enable, etc.), and supply control signals C1, control signals C2, and control signals C3 A lookup table (LUT) 152 stores address information necessary to replace bad blocks with normal spare blocks; management memory 154 stores memory for staging (writing) and erasing The state of the cell, etc.; the word line selection circuit 160 decodes the address information of the row address information Ax from the address register 130 or the address of the lookup table, and performs a region based on the decoding result. Block Selecting a word line or the like; a page buffer/sense circuit 170 holding data read from a page selected by the word line selection circuit 160 or holding data written to the selected page; The selection circuit 180 decodes the column address information Ay from the address register 130, and selects the column data in the page buffer 170 based on the decoding result; and the internal voltage generating circuit 190 generates data for performing data. Voltages necessary for reading, programming, and erasing (programmed voltage Vprog, pass voltage Vpass, read voltage Vread, erase voltage Vers, etc.).

The controller 150 has a function for managing bad blocks as described below, and responds Management of bad blocks is performed in response to commands from an external controller or in response to a control sequence or control program carried on itself. The controller 150 writes the state to the management memory 154 when performing a program (write) or erase operation, and further converts the address conversion information for converting the pages in the bad block and/or the bad block. Write to lookup table 152. In a preferred embodiment, lookup table 152 and management memory 154 include rewritable non-volatile memory or non-volatile registers.

The memory array 110 includes a plurality of blocks BLK(0), BLK(1), ..., BLK(m) arranged in the column direction. A page buffer/sense circuit 170 is disposed at one end of the block. However, the page buffer/sense circuit 170 can also be disposed at the other end or both ends of the block. Furthermore, the memory array 110 can also be disposed on both sides of the word line selection circuit 160.

As shown in FIG. 5, a plurality of anti-serial units NU are formed in one memory block, and the anti-serial unit NU is formed by connecting a plurality of memory cells in series, in a memory block, along a There are n+1 string units NU arranged in the row direction. The string unit NU includes: a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series; a transistor TD is selected, connected to the drain side of the memory cell MC31 as one end; and selection of electricity The crystal TS is connected to the source side of the memory cell MC0 as the other end portion; and the drain of the selected transistor TD is connected to a corresponding bit line GBL, and the source of the selected transistor TS is connected The shared source line SL.

The control gate of the memory cell MCi is connected to the word line WLi, and the gate of the selection transistor TD and the selection transistor TS is connected to the selection gate line SGD and the selection gate line SGS which are parallel to the word line WL. Word line selection circuit 160 is based on row address Ax When the block is selected by the converted address, the selection transistor TD and the selection transistor TS are selectively driven via the selected gate signal of the block. In addition, FIG. 5 shows the configuration of a typical string unit, but the string unit may also include one or more dummy cells in the reverse string.

Typically, the memory cell has a Metal-Oxide-Semiconductor (MOS) structure including: a source/drain as an N-type diffusion region formed in the P-well; a tunnel oxide film is formed on the channel between the source and the drain; a floating gate (charge accumulation layer) is formed on the tunnel oxide film; and the gate is controlled, and the gate is separated An electric film is formed on the floating gate. When the charge is not accumulated in the floating gate, that is, when the data "1" is written, the threshold is in a negative state, and the memory cell is normally on. When electrons are accumulated in the floating gate, that is, when the data "0" is written, the threshold shift is positive, and the memory cell is normally off.

FIG. 6 is a table showing an example of a bias voltage applied during each operation of the flash memory. In the read operation, a positive voltage is applied to the bit line, a certain voltage (for example, 0 V) is applied to the selected word line, and a turn-on voltage Vpass (for example, 4.5 V) is applied to the unselected word line, and the gate line SGD is selected. The gate line SGS is selected to apply a positive voltage (for example, 4.5 V), the bit line selection transistor TD and the source line selection transistor TS are turned on, and 0 V is applied to the common source line. In the stylized (write) operation, a high voltage stylized voltage Vprog (15V~20V) is applied to the selected word line, and an intermediate potential (for example, 10V) is applied to the unselected word line, so that the bit line selects the transistor. TD is turned on (on), causing the source line selection transistor TS to be turned off, and will be "0" or "1" The potential corresponding to the data is supplied to the bit line GBL. In the erase operation, 0V is applied to the selected word line in the block, and a high voltage (for example, 20V) is applied to the P well, and the data is erased by the block unit by extracting the electrons of the floating gate to the substrate. .

Next, the operation of establishing the lookup table in the bad block management method of the present embodiment will be described with reference to the flowchart of FIG. The controller 150 starts management of the bad block in response to a command from the external controller or in response to a control sequence or a control program carried on itself (S100).

If the management of the bad block is performed, the controller 150 reads the status from the management memory 154 and checks the verification result of the stylized or erased. As described above, when the stylization (writing) or erasing is performed by the incremental step pulse patterning method or the incremental step pulse erasing method, verification is performed, and the verification result or the like is stored in the management memory 154. For example, it is determined that the verification of the selected page is unqualified or qualified by the application of the predetermined number of stylized pulses, and the verification of the selected block is judged to be unqualified or qualified, or verified by the application of the erase pulse of a predetermined number of times. The final result is stored as a failure or the like as a state.

It is determined whether or not there is a bad block based on the result of the state check (S104). The determination of whether or not there is a bad block may also be performed by the controller 150, or may also provide a check result of the state to the external controller in response to a command from the external controller, and receive the result of the determination there. Therefore, an algorithm for determining whether or not there is a bad block is prepared in advance in the controller 150 or an external controller. The criterion for determining which block is a bad block can be arbitrarily determined. For example, if the final verification result is unqualified, or if the final verification result is acceptable, When a stylized pulse or a erase pulse is added more than a fixed number of times, the block can be set as a bad block.

If it is determined that there is a bad block (S104), it is further determined whether a part of the bad block is a bad page (S106). A part of the bad block is a bad page, which means that the bad block memory is on the bad page and the normal page. Whether or not the determination of the bad page is determined as to whether or not the bad page is determined may be performed by the controller 150 or by an external controller. The criterion for determining which page becomes a bad page can be arbitrarily determined. For example, when the stylized final verification result is unqualified or exceeds the expected number of stylized pulses, the page can be set to a bad page or a bad page. For example, as shown in FIG. 2(B), the page Pi of the determination block 5 is a bad page.

In the case where it is determined that there is a bad block and a bad page is included, the controller 150 writes the address conversion information for converting the bad block and the page within the bad block to the lookup table 152 (S108). On the other hand, in a case where it is determined that there is a bad block but there is no bad page, the controller 150 writes the address conversion information for converting the bad block to the lookup table 152 (S110).

8(A) to 8(B) are diagrams for explaining address conversion information of the lookup table 152. In FIG. 8(A), it is assumed that the determination page Pi is a bad page (bad page) and the block 5 is a bad block. In this case, the page other than the page Pi of the block 5 is normal, and it is desirable to continue to use the material written to the page other than the page Pi. In one embodiment, the access to page P0~page Pi-1 is still valid, that is, access to block 5 is continued, and access to page Pi~page Pn is converted to correspondence to spare block 1004. Page Pi~ page Pn access.

Fig. 8(B) shows an example of address conversion information of the lookup table. The lookup table contains a block conversion table in which address information useful for converting the bad block 5 into the spare block 1004 is specified. Further, flag information as additional information is specified in the block conversion table. Flag information is information that identifies whether a bad block contains bad pages and normal pages. If it is assumed that the bad block contains a bad page and a normal page, the flag is set to "1" to establish a page conversion table. When all the pages of the bad block are bad pages, or when it is not determined that the bad block contains bad pages, the flag is set to "0". In the example of FIG. 8(A), the bad block 5 includes the bad page Pi and other normal pages, so the flag is set to "1", and the page conversion table is further added to the bad block 5.

The page conversion table specifies address conversion information for converting pages containing bad pages in bad blocks, and address conversion information for converting pages that do not contain bad pages. In the example of FIG. 8(A), the block 5 is divided into the page group A of the normal page P0 to the page Pi-1 and the page group B of the page Pi~page Pn including the bad page by the bad page Pi as a boundary. Moreover, it is assumed that the access to the page group A is directly accessed in the block 5, that is, the address to the page group A is not converted. On the other hand, access to page group B specifies address translation information in a manner that is accessed on the corresponding page of block 1004.

How to divide the block 5 containing bad pages and not including bad pages is arbitrary. For example, it is also possible to set only the page Pi of the defective page Pi to be converted into the block 1004, and the normal pages P0 to P1 and the pages Pi+1 to Pn of the other pages continue to be accessed in the block 5. However, as in the example of FIG. 8(B), converting a page including a defective page Pi into a spare block may cause access to the same block. The rate is increased, which is advantageous in terms of shortening the access time.

Next, the reading, stylization, and erasing operations after the execution of the bad block management will be described with reference to the flowchart of FIG. If a command to read, program (write), erase, etc. is sent from the external controller to the flash memory 100, the controller 150 decodes the received command and discriminates its operation (S200). When the controller 150 reads and programs, it determines whether the block address of the input row address matches the bad block address (S202). This determination is a reference lookup table 152.

When coincident with the bad block, the controller 150 determines whether a part of the bad block contains a bad page (S204). In this determination, the flag of the lookup table refers to "1". When it is determined that a part of the bad page is included, the controller 150 refers to the page conversion table of the bad block to perform conversion of the input page address (S206). For example, if it is the example of FIG. 8(A) to FIG. 8(B), if the input page address matches the P0~Pi-1 of the block 5, it is in the block 5 according to the page conversion table. The page group A accesses the mode conversion address. If it matches the page Pi~ page Pn, the address is translated in the manner of accessing the page group B of the block 1004.

When it is determined that the bad block does not contain a bad page, that is, if the flag is "0", the input block address is converted into the address of the spare block according to the block conversion table (S208). . In the case where the input block address does not coincide with the bad block address (S202), the input block address is not converted and is directly used (S210). The input address or the converted address is supplied to the word line selection circuit 160, and the word line selection circuit 160 selects the block and the page (S220). Thereby, it is possible to continue to utilize the data of the normal page stored in the bad block.

On the other hand, when performing the erase operation (S200), the controller 150 determines whether the input block address and the bad block address match (S212), and if it matches the bad block address, according to The block conversion table converts the block address to the address of the spare block (S214). In the example of FIGS. 8(A) to 8(B), if the input block address is block 5, it is converted to the address of the block 1004.

If the input block address does not match the bad block address (S212), the input block address is directly used. Moreover, the word line selection circuit 160 selects a block in accordance with the input block address or the converted block address (S220). When the input block address matches the bad block, at least the spare block is erased, but the bad block can also be erased at the same time.

Next, the reorganization of the present embodiment and the update of the lookup table will be described with reference to the flowchart of FIG. If the reorganized command is discriminated (S300) in response to a command transmitted from the external controller or a control sequence or a control program mounted thereon, the controller 150 performs reorganization (S302). As shown in FIGS. 8(A) to 8(B), when a bad page and a normal page are included in the bad block, there are two blocks including the page group A and the block 100 including the page group B. Block. The reorganization causes the page data fragmented into the two blocks to be integrated or aggregated into one block.

As shown in FIG. 11(A), the controller 150 integrates the page group A of the block 5 with the page group B of the block 1004 into an idle spare block, such as the block 1006. The data of the page group A of the block 5 is programmed in the corresponding pages of the block 1006, and the data of the page group B of the block 1004 is programmed in the corresponding pages of the block 1006. Thus, the two blocks 5 and blocks 1004 are integrated into one block 1006. Preferably, Block 1004 is erased after the reorganization is performed, leaving block 1004 in an idle state.

Then, the controller 150 updates the contents of the lookup table 152 (S308). That is, the controller 150 updates the address translation information of the lookup table in a manner reflecting the result of the reorganization. Specifically, as shown in FIG. 11(B), the address conversion information is rewritten in such a manner that the address of the bad block 5 is converted into the address of the spare block 1006, and the flag is set to "0". Along with this, the page conversion table of the bad block 5 is erased.

Further, the controller 150 determines when the erase operation has been performed (S304) Whether the selected block is a bad block (S306). The erasing of bad blocks refers to the fact that there is no need to store the normal pages of bad blocks. For example, the page group A of the block 5 and the page group B of the block 1004 shown in FIG. 8(A) are not required, and the page group A and the page group B do not need to be stored in the page reading or page staging. take. Therefore, when the flag 150 is set to the bad block 5, the controller 150 updates the lookup table 152 by rewriting the flag to "0" and erasing the page conversion table of the block 5 (S308). ).

By performing reorganization in this manner, access across blocks can be reduced, thereby increasing access speed. Furthermore, by increasing the number of blank blocks in the spare memory area, the efficiency of bad block management can be improved.

In the embodiment, the flash memory for storing the binary data in the memory unit is exemplified, but the present invention is also applicable to the flash memory in which the memory unit stores the multi-bit data. Further, in the above embodiment, an example in which the controller 150 performs management of bad blocks is shown, but management of bad blocks may be performed by the word line selection circuit 160, and bad blocks may be provided separately from the controller 150. Management. Further, the lookup table 152 or the management memory 154 can also utilize a portion of the memory region of the memory array 110. The domain 150 can also include a lookup table and management memory therein.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the invention as described in the appended claims.

100‧‧‧flash memory

110‧‧‧Memory array

120‧‧‧Input and output buffers

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

152‧‧‧ lookup table

154‧‧‧Manage memory

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧ column selection circuit

190‧‧‧Internal voltage generation circuit

Ax‧‧‧ address information

Ay‧‧‧Listing address information

BLK (0), BLK (1), ..., BLK (m) ‧ ‧ blocks

C1, C2, C3‧‧‧ control signals

Vers‧‧‧ erase voltage

Vpass‧‧‧ turn-on voltage

Vprog‧‧‧ stylized voltage

Vread‧‧‧ reading voltage

Claims (14)

A bad block management method, which is a bad block management method of a reverse flash memory, and includes the following steps: determining whether there is a bad block in the memory array; when it is determined that the bad block exists Determining whether a portion of the bad block has a bad page; and determining that the bad block and the bad area are converted when a portion of the bad block is present in the bad block Address translation information of a page in the block, wherein the step of setting is to divide the bad block into two page groups by using the bad page as a boundary, and setting the location for including the bad page The page group is converted into the address translation information of the corresponding page of the spare block. The bad block management method according to claim 1, wherein the setting step is to set a page for converting a first page including the bad page into a corresponding page in the spare block. Address translation information is set, and the address translation information is set in a manner that the second page that does not include the bad page is accessed in the bad block. The bad block management method according to claim 1 or 2, wherein the setting step stores the address conversion information in a rewritable non-volatile memory. The bad block management method according to claim 1 or 2, wherein the bad block management method further comprises the step of integrating the bad block and the spare block into one block. A bad block management method as described in claim 4, wherein the method The step of integrating is performed in response to performing the erasure of the bad block. The bad block management method according to claim 4, wherein the step of integrating is performed by executing a command. A bad block management program is a bad block management program executed by the inverse type flash memory, and includes the following steps: determining whether there is a bad block in the memory array; determining that the bad area exists At the time of the block, determining whether a portion of the bad block has a bad page; and determining that the bad block is to be converted in a part of the bad block, The address translation information of the page in the bad block, wherein the step of setting is to divide the bad block into two page groups by using the bad page as a boundary, and set to be used to include the bad page. The page group is converted into the address translation information of a corresponding page of the spare block. A flash memory comprising: a memory array comprising a plurality of blocks; a storage component storing a state when the memory array is programmed and erased; and a first determining component determining based on the state Whether there is a bad block in the memory array; when determining that the bad block exists, the second determining unit determines whether a part of the bad block has a bad page based on the state; and setting a component that determines that the bad page exists in a portion of the bad block And setting address conversion information for converting the bad block and the page in the bad block, wherein the storage component divides the bad block into two pages by using the bad page as a boundary a group, configured to convert the page group including the bad page into the address translation information of a corresponding page of the spare block. The flash memory of claim 8, wherein the setting component is configured to convert the first page including the bad page into the address of a corresponding page in the spare block. Converting the information, and setting the address translation information in a manner that the second page that does not include the bad page is accessed in the bad block. The flash memory of claim 8, wherein the flash memory further comprises: an input component, input address information; and a third determining component, determining the address information from the input component Whether it is consistent with the bad block; and the conversion component converts the address information according to the address conversion information when it is determined to be consistent with the bad block. The flash memory of claim 10, wherein the flash memory further comprises a fourth determining component that determines whether the address information from the input component matches the bad page, When it is determined that the bad page is consistent, the conversion unit converts the address information according to the address conversion information. The flash memory according to claim 11, wherein the conversion unit determines, by the fourth determining unit, the address information and the bad page If there is no match, the conversion component does not perform address translation on the address information according to the address conversion information. The flash memory according to any one of claims 8 to 12, wherein the flash memory further comprises integrating the bad block and the spare block into one block. Integrate parts. The flash memory of claim 13, wherein the integrated component is executed in response to performing erasing of the bad block.