TWI529779B - Method for patterning semiconductor structure - Google Patents

Description

Method of patterning a semiconductor structure

This invention relates to a method of patterning a semiconductor structure, and more particularly to a method of patterning a semiconductor structure using two masks having similar patterns.

In order to form a designed integrated circuit on a semiconductor wafer, a photomask is generally formed, and a layout pattern is formed on the photomask, and the light is processed by a yellow photolithography process. The pattern on the cover is transferred to the photoresist layer on the surface of the semiconductor structure, thereby transferring the layout pattern of the integrated circuit to the semiconductor structure. Therefore, the lithography process can be said to be a very important key step in the semiconductor process.

Since the critical dimension (CD) of the pattern that can be fabricated on the reticle is limited by the resolution limit of the optical exposure tool, the integration is gradually formed. The circuit design is getting smaller and smaller. When the high-density reticle is exposed to the pattern for pattern transfer, the optical proximity effect (OPE) is easily generated, resulting in deviation of the pattern transfer. Or the pattern is deformed to affect the electrical characteristics of the product.

The present invention is directed to a method of patterning a semiconductor structure that can transfer a desired pattern from a reticle into a semiconductor structure.

According to one aspect of the invention, a method of patterning a semiconductor structure is presented. The method includes the following steps. A first photomask is provided. The first reticle defines a first pattern in a first region and is adjacent to a second region of the first region A second pattern is defined. Transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first film structure in the second region. A second film structure is formed on the first film structure. A second photomask is provided. The second reticle defines a third pattern in the first region. At least 50% of the portion of the first pattern defined by the first mask in the first region is the same as the portion of the third pattern defined by the second mask in the first region. The third pattern defined by the second mask is transferred to the second film structure in the first region. The third pattern in the second film structure is transferred to the first film structure.

In accordance with an alternative aspect of the invention, a method of patterning a semiconductor structure is presented. The method includes the following steps. A first photomask is provided. The first reticle defines a first pattern in a first region and defines a second pattern in a second region adjacent to the first region. Transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first film structure in the second region. A second film structure is formed on the first film structure. A second photomask is provided. The second reticle defines a third pattern in the first region. At least 50% of the area projected from the first pattern defined by the first mask to the first film structure is overlaid on the area projected from the third pattern defined by the second mask to the second film structure. The third pattern defined by the second mask is transferred to the second film structure in the first region. The third pattern in the second film structure is transferred into the first film structure.

According to still another aspect of the present invention, a method of patterning a semiconductor structure is presented. The method includes the following steps. A first photomask is provided. The first reticle defines a first pattern in a first region and defines a second pattern in a second region adjacent to the first region. Transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first film structure in the second region. A second film structure is formed on the first film structure. A second photomask is provided. The second reticle defines a third pattern in the first region. At least 50% of the area of the first pattern defined by the first mask is corresponding to the third pattern defined by the second mask. Transferring the third pattern defined by the second mask a second film structure into the first region. The third pattern in the second film structure is transferred into the first film structure.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

102‧‧‧First film structure

104‧‧‧Substrate

106‧‧‧Dielectric layer

108‧‧‧hard mask layer

110‧‧‧ dielectric layer

112‧‧‧hard mask layer

114‧‧‧etch stop layer

116‧‧‧Dielectric layer

118‧‧‧Anti-reflective layer

120‧‧‧ photoresist layer

122‧‧‧First mask

124‧‧‧ first pattern

126‧‧‧ second pattern

128‧‧‧First area

130‧‧‧Second area

132‧‧‧ first pattern

134‧‧‧second pattern

136‧‧‧ first pattern

138‧‧‧ second pattern

140‧‧‧Second film structure

142‧‧‧mask layer

144‧‧‧Anti-reflective layer

146‧‧‧ photoresist layer

148‧‧‧second mask

150‧‧‧ third pattern

152‧‧‧ third pattern

154‧‧‧film pattern

156‧‧‧film pattern

158‧‧‧second pattern

160‧‧‧film pattern

162‧‧‧second pattern

164‧‧‧film pattern

166‧‧‧second pattern

168‧‧‧film pattern

170‧‧‧second pattern

1 through 8 illustrate a method of patterning a semiconductor structure in accordance with an embodiment.

1 through 8 illustrate a method of patterning a semiconductor structure in accordance with an embodiment.

Referring to FIG. 1 , the first thin film structure 102 may include a substrate 104 , a dielectric layer 106 , a hard mask layer 108 , a dielectric layer 110 , a hard mask layer 112 , an etch stop layer 114 , a dielectric layer 116 , and anti-reflection. Layer 118 and photoresist layer 120. For example, substrate 104 can include a germanium substrate or other suitable semiconductor substrate. Dielectric layer 106 can include a pad oxide. The hard mask layer 108 can include a nitride such as tantalum nitride. Dielectric layer 110 can include an oxide such as hafnium oxide. The hard mask layer 112 may comprise an advanced pattern film (APF) (trade name) obtained from US Applied Materials. The etch stop layer 114 may include an oxide such as carbon-containing cerium oxide (SiOC). Dielectric layer 116 can include an oxide such as hafnium oxide. The anti-reflective layer 118 may include a bottom anti-reflective coating (BARC).

A first reticle 122 is provided. The first reticle 122 defines a first pattern 124 in the first region 128 and a second pattern 126 in the second region 130 adjacent the first region 128. In an embodiment, the first region 128 is a region corresponding to a larger component (eg, a non-critical dimension), including a dummy pattern region or a device region, such as a logic device region, and the second region 130 corresponds to Device regions having narrower component characteristics (e.g., having critical dimensions) include, for example, static random access memory (SRAM) device regions. For example, for a 20 nm generation, the component line width of the critical dimension region can be about 40 nm, line space. It can be about 50 nm. Further, the element line width and the line spacing of the non-critical size regions may be greater than about 200 nm.

Referring to FIG. 1 , the first pattern 124 defined by the first mask 122 can be transferred to the first film structure 102 to form the first pattern 132 in the photoresist layer 120 in the first region 128 by using a yellow light lithography process. And transferring the second pattern 126 defined by the first mask 122 to the first film structure 102 to form the second pattern 134 in the photoresist layer 120 in the second region 130.

Referring to FIG. 2, the photoresist layer 120 is used as an etch mask to perform an etching step to transfer the first pattern 132 of the photoresist layer 120 downward to the dielectric layer 116 in the first region 128 to form a first The pattern 136 is patterned and the second pattern 134 of the photoresist layer 120 is transferred down to the dielectric layer 116 in the second region 130 to form a second pattern 138. This etching step can be substantially stopped at the etch stop layer 114. The anti-reflective layer 118 and the photoresist layer 120 can then be removed.

Referring to FIG. 3, a second film structure 140 is formed on the first film structure 102A. The second film structure 140 may include a mask layer 142, an anti-reflection layer 144, and a photoresist layer 146. Mask layer 142 may comprise an I-line photoresist material that is sensitive to light sources having a wavelength of 365 nm. The anti-reflective layer 144 may be a single or multi-layer anti-reflective layer, and the composition may be an organic silicon polymer or a polysilane. The photoresist layer 146 can be an ArF photoresist or a 193 nm photoresist.

Referring to FIG. 3, a second mask 148 is provided. The second mask 148 defines a third pattern 150 in the first region 128. Furthermore, the second mask 148 does not define a pattern in the second region 130. The third pattern 150 defined by the second mask 148 can be transferred to the second film structure 140 to form a third pattern 152 in the photoresist layer 146 in the first region 128 using a yellow lithography process.

Referring to FIG. 4, the third pattern 152 in the photoresist layer 146 is transferred downward into the first thin film structure 102A in the first region 128, and the first pattern 136 and the third pattern are formed in the dielectric layer 116. 152 combines the formed film pattern 154. For example, the method of transferring the third pattern 152 (Fig. 3) includes the following steps. An etching step is performed using the photoresist layer 146 as an etch mask to place the third pattern 152 Transfer to the anti-reflective layer 144, the mask layer 142 can be used as an etch stop layer in this etching step. An etching step can then be performed using an anti-reflective layer 144 having a third pattern (not shown) as an etch mask to transfer a third pattern (not shown) to the mask layer 142, wherein the dielectric layer 116 and the etch stop layer 114 may be used as an etch stop layer in this etch step, and the remaining photoresist layer 146 may be removed by this etching step. The anti-reflective layer 144 can then be removed. An etch step can then be performed using the mask layer 142 having a third pattern (not shown) as an etch mask to transfer a third pattern (not shown) to the dielectric layer 116, which can be stopped at the etch stop layer 114. The mask layer 142 can then be removed to expose the dielectric layer 116 having the thin film pattern 154 and the second pattern 138 in the first region 128 and the second region 130, respectively, as shown in FIG.

In an embodiment, the first reticle 122 (FIG. 1) and the second reticle 148 (FIG. 3) are designed to have a similar pattern in the first region 128, and only the first region in the second region 130. The mask 122 has a pattern (in other words, the second mask 148 does not have a pattern in the second region 130), and uses this design to perform a patterning process, so that the transfer of the mask pattern density to the semiconductor structure can be avoided ( For example, the pattern of the dielectric layer 116) of the first film structure 102A (eg, the thin film pattern 154 and the second pattern 138) is deformed. This design has a more significant effect on the formation of a pattern of elements having a critical dimension (e.g., the second pattern 138) in the second region 130 (SRAM device region). For example, at least 50% of the portion of the first pattern 124 defined by the first mask 122 in the first region 128 is identical (or overlapped) to the third pattern 150 defined by the second mask 148. The portion occupied by the first area 128. Alternatively, at least 50% of the area projected from the first pattern 124 defined by the first mask 122 to the first film structure 102 is overlapped with the third pattern 150 defined from the second mask 148 to be projected onto the second film structure. The area of 140. Alternatively, at least 50% of the area of the first pattern 124 defined by the first mask 122 is corresponding to the third pattern 150 defined by the second mask 148. In the embodiment, when the pattern similarity between the first mask 122 and the second mask 148 in the first region 128 is higher, the problem that the mask pattern density causes deformation of the pattern transferred to the semiconductor structure can be avoided. In other words, the higher the accuracy of the pattern transfer and the better the transfer effect. In some embodiments, for example, first The portion of the first pattern 124 defined by the reticle 122 in the first region 128 is substantially identical to the portion of the third pattern 150 defined by the second reticle 148 in the first region 128. Alternatively, the area projected from the first pattern 124 defined by the first mask 122 onto the first film structure 102 is substantially completely overlapped with the third pattern 150 defined from the second mask 148 and projected onto the second film structure 140. Area. Alternatively, the first pattern 124 defined by the first mask 122 is substantially identical to the third pattern 150 defined by the second mask 148.

In the embodiment, the thin film pattern 154 formed by transferring the first pattern 124 defined by the first mask 122 (Fig. 1) and the third pattern 150 defined by the second mask 148 (Fig. 3) (4th FIG.), which is designed to be disposed in a non-critical first region 128 (including, for example, a dummy pattern region or a logic device region), and thus is capable of accepting an alignment adjustment offset caused by an alignment error ( Alignment shift; AA-shift) In other words, such a size shift does not affect the electrical characteristics of the integrated circuit. For example, for the 20 nm generation, the specification of the alignment adjustment offset is limited to less than about 5 nm.

Referring to FIG. 5, an etching step may be performed to transfer the thin film pattern 154 and the second pattern 138 in the dielectric layer 116 downward to the etch stop layer 114 to form a thin film pattern 156 and a second in the etch stop layer 114. Pattern 158. Dielectric layer 116 is then removed.

Referring to FIG. 6, an etching step may be performed using the etch stop layer 114 as an etch mask to transfer the thin film pattern 156 and the second pattern 158 in the etch stop layer 114 downward to the hard mask layer 112 to be hard. A thin film pattern 160 and a second pattern 162 are formed in the mask layer 112. The etch stop layer 114 can then be removed.

Referring to FIG. 7, an etching step may be performed using the hard mask layer 112 as an etch mask to transfer the thin film pattern 160 and the second pattern 162 in the hard mask layer 112 downward to the hard mask layer 108. A thin film pattern 164 and a second pattern 166 are formed in the hard mask layer 108. The hard mask layer 112 can then be removed.

Referring to FIG. 8, the hard mask layer 108 can be used as an etch mask to perform an etching step to bond the thin film pattern 164 and the second pattern in the hard mask layer 108. The 166 is transferred down to the substrate 104 to form a thin film pattern 168 and a second pattern 170 in the substrate 104. The dielectric layer 110 remaining on the hard mask layer 108 can help the substrate 104, dielectric layer 106, and hard mask layer 108 have a good corner shape after this etching step. After this etching step, the dielectric layer 110 can be removed.

As can be seen from the above description, the embodiments provide a method of patterning a semiconductor structure that can transfer a desired pattern into the semiconductor structure to avoid deformation of the transferred pattern caused by the density of the mask pattern.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

102‧‧‧First film structure

104‧‧‧Substrate

106‧‧‧Dielectric layer

108‧‧‧hard mask layer

110‧‧‧ dielectric layer

112‧‧‧hard mask layer

114‧‧‧etch stop layer

116‧‧‧Dielectric layer

118‧‧‧Anti-reflective layer

120‧‧‧ photoresist layer

122‧‧‧First mask

124‧‧‧ first pattern

126‧‧‧ second pattern

128‧‧‧First area

130‧‧‧Second area

132‧‧‧ first pattern

134‧‧‧second pattern

Claims (18)

A method of patterning a semiconductor structure, comprising: providing a first reticle defining a first pattern in a first region and defining a second region adjacent to the first region a second pattern; transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first pattern The first film structure in the two regions; forming a second film structure on the first film structure; providing a second mask, wherein the second mask defines a third pattern in the first region, wherein At least 50% of the portion of the first pattern defined by the first mask in the first region is the same as the third pattern defined by the second mask in the first region. Portioning the third pattern defined by the second mask to the second film structure in the first region; transferring the third pattern in the second film structure to the first film structure; Will land all at the same level on one of the first film structures The portion of the second patterned simultaneously transferred from the first patterned thin film pattern and the third pattern constituting one down to about the first film structure. The method of claim 1, wherein the portion of the first pattern defined by the first mask in the first region is substantially identical to the second The reticle defines the portion of the third pattern that is occupied in the first region. A method of patterning a semiconductor structure according to claim 1, wherein the second mask does not define a pattern in the second region. The method of claiming the patterned semiconductor structure of claim 1, further comprising removing the second film after transferring the third pattern in the second film structure to the first film structure. structure. A method of patterning a semiconductor structure according to claim 1, wherein the film pattern is in the first region. The method of patterning a semiconductor structure according to claim 1, wherein the first film structure is in the second region after the third pattern in the second film structure is transferred to the first film structure The middle has the second pattern. A method of patterning a semiconductor structure according to claim 1, wherein the first region comprises a logic device region or a dummy pattern region, and the second region comprises a static random access memory (SRAM) device region. A method of patterning a semiconductor structure according to claim 1, wherein the first region is a non-critical region and the second region is a critical region. A method of patterning a semiconductor structure, comprising: providing a first reticle defining a first pattern in a first region and defining a second region adjacent to the first region a second pattern; transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first pattern The first film structure in the two regions; forming a second film structure on the first film structure; providing a second mask, wherein the second mask defines a third pattern in the first region, wherein At least 50% of the area projected from the first mask to the first film structure is overlapped with the third pattern defined by the second mask projected onto the second film structure a region; transferring the third pattern defined by the second mask to the second film structure in the first region; transferring the third pattern in the second film structure into the first film structure; And landing all of the upper portion of the first film structure The second pattern is transferred on the same level simultaneously by the first pattern and the film pattern constituting one of the third pattern down to the first portion about the film structure. The method of patterning a semiconductor structure according to claim 9, wherein the first pattern defined from the first mask is projected to the first film junction The region of the structure is substantially completely overlapping the region of the third pattern defined by the second mask onto the second film structure. A method of patterning a semiconductor structure according to claim 9 wherein the second mask does not define a pattern in the second region. A method of patterning a semiconductor structure according to claim 9 wherein the first region comprises a logic device region or a dummy pattern region, the second region comprising a static random access memory device region. A method of patterning a semiconductor structure according to claim 9 wherein the first region is a non-critical dimension region and the second region is a critical dimension region. A method of patterning a semiconductor structure, comprising: providing a first reticle defining a first pattern in a first region and defining a second region adjacent to the first region a second pattern; transferring the first pattern defined by the first mask to a first film structure in the first region, and transferring the second pattern defined by the first mask to the first pattern The first film structure in the two regions; forming a second film structure on the first film structure; providing a second mask, wherein the second mask defines a third pattern in the first region, wherein The at least 50% of the area defined by the first reticle corresponds to the third pattern defined by the second reticle; and the third pattern defined by the second reticle is transferred to the The second film structure in the first region; transferring the third pattern in the second film structure into the first film structure; and landing all at the same level on a portion of the first film structure The second pattern and the first pattern and the third pattern One pattern is transferred simultaneously to a thin film down to the thin film structure at a first portion. A method of patterning a semiconductor structure according to claim 14, wherein the first pattern defined by the first mask is substantially identical to the third pattern defined by the second mask. A method of patterning a semiconductor structure according to claim 14 wherein the second mask does not define a pattern in the second region. A method of patterning a semiconductor structure according to claim 14, wherein the first region comprises a logic device region or a dummy pattern region, and the second region comprises a static random access memory device region. A method of patterning a semiconductor structure according to claim 14, wherein the first region is a non-critical size region and the second region is a critical dimension region.