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TWI524545B - Method of Making Solar Cell Structure - Google Patents

Method of Making Solar Cell Structure Download PDF

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TWI524545B
TWI524545B TW103125473A TW103125473A TWI524545B TW I524545 B TWI524545 B TW I524545B TW 103125473 A TW103125473 A TW 103125473A TW 103125473 A TW103125473 A TW 103125473A TW I524545 B TWI524545 B TW I524545B
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semiconductor layer
single crystal
type semiconductor
layer
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TW103125473A
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TW201605063A (en
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Hui-Liang Huang
Jian-Yang Lin
cheng-xiang Hu
Chao-Cheng Li
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Hui-Liang Huang
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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Description

太陽電池結構的製作方法 Solar cell structure manufacturing method

本發明係有關於一種太陽電池,特別是有關於一種晶矽太陽電池的製作方法。 The present invention relates to a solar cell, and more particularly to a method of fabricating a wafer solar cell.

單晶矽的組成原子均按照一定的規則,週期性地排列,它的製作方法是把矽金屬(純度為99.999999999%,11個9)熔融於石英坩堝中,然後把晶種插入液面,以每分鐘2~20轉的速率旋轉,同時以每分鐘0.3~10毫米的速度緩慢的往上拉引,如此即可形成一直徑4~8吋單晶矽碇,此製作方法稱為柴氏長晶法(Czochralski method),用單晶矽製成的太陽電池,效率高且性能穩定,目前已被廣泛的應用。 The constituent atoms of the single crystal germanium are periodically arranged according to a certain rule. The method is prepared by melting a base metal (purity of 99.999999999%, 11 9) into a quartz crucible, and then inserting the seed crystal into the liquid surface to Rotate at a rate of 2 to 20 revolutions per minute, and slowly pull up at a speed of 0.3 to 10 mm per minute. Thus, a single crystal of 4 to 8 inches in diameter can be formed. This method is called Chai's length. The Czochralski method, a solar cell made of single crystal germanium, has high efficiency and stable performance and has been widely used.

近年來國際石油價格不斷攀升,且核能安全堪憂。而台灣的能源仰賴進口煤炭與核能發電,火力發電與核能發電佔了台灣發電比例的絕大多數,為了降低對於進口的依賴程度和在台灣核能設施過於老舊使人受到生命威脅的情況下,再生能源對於台灣這塊土地來說,需要受到相當大的重視。 In recent years, international oil prices have been rising and nuclear safety is worrying. While Taiwan's energy relies on imported coal and nuclear power, thermal power and nuclear power account for the vast majority of Taiwan's power generation. In order to reduce dependence on imports and to make Taiwan's nuclear facilities too old and life threatening, Renewable energy needs to receive considerable attention for the land of Taiwan.

在眾多的再生能源中,以太陽電池最為適合普遍地開發,因為台灣地處亞熱帶區,一年來日照豐沛,且台灣在太陽電池製造上有非常大的優勢,如半導體產業技術成熟,在全球太陽電池出貨中佔據要角,因此極具發展半導體太陽電池優勢。 Among the many renewable energy sources, solar cells are most suitable for universal development. Because Taiwan is located in the subtropical zone, it has a strong sunshine in the past year, and Taiwan has great advantages in solar cell manufacturing, such as the maturity of the semiconductor industry and the global sun. Battery shipments occupy a leading role, so it has the advantage of developing semiconductor solar cells.

以現今發展的太陽電池製作步驟,首先以RCA清洗流程清洗基板表面,之後結構化基板表面,並使用酸性溶液清洗結構化表面,再來使用擴散製程製作P型半導體層或是N型半導體層於基板表面上,而擴散P型半 導體層或N型半導體層是取決於基板的型態,目前皆以P型半導體參雜矽當作基板,再高溫擴散N型半導體參雜層,再來使用蝕刻方式蝕刻擴散後基板邊緣,再來也是用蝕刻方式去除基板表面氧化物,接著在基板表面製作抗反射層,最後再製作金屬電極。 In the current solar cell fabrication process, the surface of the substrate is first cleaned by an RCA cleaning process, and then the surface of the substrate is structured, and the structured surface is cleaned using an acidic solution, and then a P-type semiconductor layer or an N-type semiconductor layer is formed using a diffusion process. On the surface of the substrate, while diffusing the P-type half The conductor layer or the N-type semiconductor layer is dependent on the type of the substrate. Currently, the P-type semiconductor doped germanium is used as the substrate, and the N-type semiconductor doping layer is diffused at a high temperature, and then the edge of the diffused substrate is etched by etching. The substrate surface oxide is also removed by etching, and then an anti-reflection layer is formed on the surface of the substrate, and finally a metal electrode is fabricated.

由上列製作流程中,可以得知太陽電池的製作是需要經過多項不同製程所結合起來的。因此如何增加太陽電池的效率值與簡化在製程中所投資的成本是一項非常重要的課題,而其中以抗反射技術最為重要,例如表面以酸性溶液蝕刻或是在表面備製抗反射層皆被廣泛應用,然而表面以酸性溶液蝕刻或是在表面備製抗反射層,皆需要多道製程,而增加製造成本;又在製作抗反射層之後,再製作金屬電極,於製作金屬電極之過程中,會減損抗反射膜之效用,因而會降低抗反射之作用,進而減少進光量,而降低太陽電池效率。 From the above production process, it can be known that the production of solar cells needs to be combined through a number of different processes. Therefore, how to increase the efficiency value of solar cells and simplify the cost invested in the process is a very important issue, and anti-reflection technology is the most important, such as etching the surface with an acidic solution or preparing an anti-reflection layer on the surface. Widely used, however, the surface is etched with an acidic solution or an anti-reflective layer is prepared on the surface, which requires multiple processes and increases manufacturing costs. After the anti-reflection layer is fabricated, a metal electrode is fabricated to produce a metal electrode. In this case, the effect of the anti-reflection film is degraded, thereby reducing the anti-reflection effect, thereby reducing the amount of light entering and reducing the efficiency of the solar cell.

有鑒於此,為了提升晶矽太陽電池效率,本發明將高介電材料二氧化鉿(HfO2)當鈍化層提供高性能的保護效果,同時於製作金屬電極之後,再利用微球結構製備抗反射層,以避免抗反射層的性能減損。 In view of this, in order to improve the efficiency of the solar cell of the wafer, the present invention provides a high-performance protective effect of the high dielectric material cerium oxide (HfO2) as a passivation layer, and at the same time, after the metal electrode is fabricated, the anti-reflection is prepared by using the microsphere structure. Layer to avoid performance degradation of the anti-reflective layer.

本發明結構包括一P型金屬接觸電極、一P型半導體層、一單晶P型基板、一N型半導體層、一N型金屬接觸電極、一表面鈍化層以及一微球狀結構化抗反射層,其中該N型半導體層與該P型半導體層分別位於該單晶P型基板之上側與下側,該P型金屬接觸電極位於該P型半導體層之下側,該表面鈍化層位於該N型半導體層上側,該N型金屬接觸電極具特定的圖案分佈且穿過該表面鈍化層與該N型半導體層連接,而該微球狀結構化抗反射層位於不具該N型金屬接觸電極的該表面鈍化層上側。 The structure of the invention comprises a P-type metal contact electrode, a P-type semiconductor layer, a single crystal P-type substrate, an N-type semiconductor layer, an N-type metal contact electrode, a surface passivation layer and a microspherical structured anti-reflection a layer, wherein the N-type semiconductor layer and the P-type semiconductor layer are respectively located on an upper side and a lower side of the single crystal P-type substrate, and the P-type metal contact electrode is located on a lower side of the P-type semiconductor layer, and the surface passivation layer is located at the bottom side On the upper side of the N-type semiconductor layer, the N-type metal contact electrode has a specific pattern distribution and is connected to the N-type semiconductor layer through the surface passivation layer, and the micro-spherical structured anti-reflection layer is located without the N-type metal contact electrode The surface passivation layer is on the upper side.

又本發明為先製作該表面鈍化層於該N型半導體層上側,再讓該N型金屬接觸電極具特定的圖案分佈於該表面鈍化層上側,且其經烘烤後,該N型金屬接觸電極為穿過該表面鈍化層與該N型半導體層連接,最後才於不具該N型金屬接觸電極的該表面鈍化層上側形成該微球狀結構化抗反射層。 In the present invention, the surface passivation layer is first formed on the upper side of the N-type semiconductor layer, and the N-type metal contact electrode is distributed on the upper side of the surface passivation layer, and after the baking, the N-type metal contact is performed. The electrode is connected to the N-type semiconductor layer through the surface passivation layer, and finally the microspherical structured anti-reflection layer is formed on the upper side of the surface passivation layer not having the N-type metal contact electrode.

據此,該表面鈍化層可以提供高效之保護效果,而該微球狀結構化抗反射層的設置,可以避免太陽光反射,而增加太陽光的通過量,且該微球狀結構化抗反射層為最後製成,因而可以避免該微球狀結構化抗反射層的性能減損,藉以提昇太陽電池效率。 Accordingly, the surface passivation layer can provide an efficient protection effect, and the microspherical structured anti-reflection layer can be arranged to avoid reflection of sunlight, increase the throughput of sunlight, and the micro-spherical structured anti-reflection The layer is finally formed, so that the performance degradation of the microspherical structured anti-reflective layer can be avoided, thereby improving the efficiency of the solar cell.

10‧‧‧P型金屬接觸電極 10‧‧‧P type metal contact electrode

20‧‧‧P型半導體層 20‧‧‧P type semiconductor layer

30‧‧‧單晶P型基板 30‧‧‧Single crystal P-type substrate

40‧‧‧N型半導體層 40‧‧‧N type semiconductor layer

50‧‧‧N型金屬接觸電極 50‧‧‧N type metal contact electrode

60‧‧‧表面鈍化層 60‧‧‧ surface passivation layer

70‧‧‧微球狀結構化抗反射層 70‧‧‧Microspherical structured anti-reflective layer

圖1為本發明較佳實施例之結構示意圖。 1 is a schematic structural view of a preferred embodiment of the present invention.

圖2A為本發明半成品之結構示意圖一。 2A is a schematic structural view of the semi-finished product of the present invention.

圖2B為本發明半成品之結構示意圖二。 2B is a schematic structural view 2 of the semi-finished product of the present invention.

茲有關本發明的詳細內容及技術說明,現以實施例來作進一步說明,但應瞭解的是,該等實施例僅為例示說明之用,而不應被解釋為本發明實施之限制。 The detailed description of the present invention and the technical description of the present invention are further illustrated by the accompanying drawings, but it should be understood that these embodiments are merely illustrative and not to be construed as limiting.

請參閱「圖1」所示,本發明結構包括一P型金屬接觸電極10、一P型半導體層20、一單晶P型基板30、一N型半導體層40、一N型金屬接觸電極50、一表面鈍化層60以及一微球狀結構化抗反射層70,其中該N型半導體層40與該P型半導體層20分別位於該單晶P型基板30之上側與下側,該P型金屬接觸電極10位於該P型半導體層20之下側,該表面鈍化層60位於該N型半導體層40上側,該N型金屬接觸電極50具特定的圖案分佈且穿過該表 面鈍化層60與該N型半導體層40連接,而該微球狀結構化抗反射層70位於不具該N型金屬接觸電極50的該表面鈍化層60上側。 Referring to FIG. 1 , the structure of the present invention includes a P-type metal contact electrode 10 , a P-type semiconductor layer 20 , a single crystal P-type substrate 30 , an N-type semiconductor layer 40 , and an N-type metal contact electrode 50 . a surface passivation layer 60 and a microspherical structured anti-reflective layer 70, wherein the N-type semiconductor layer 40 and the P-type semiconductor layer 20 are respectively located on the upper side and the lower side of the single crystal P-type substrate 30, the P-type The metal contact electrode 10 is located on the lower side of the P-type semiconductor layer 20, and the surface passivation layer 60 is located on the upper side of the N-type semiconductor layer 40. The N-type metal contact electrode 50 has a specific pattern distribution and passes through the table. The surface passivation layer 60 is connected to the N-type semiconductor layer 40, and the micro-spherical structured anti-reflection layer 70 is located on the upper side of the surface passivation layer 60 having the N-type metal contact electrode 50.

又接觸該N型半導體層40的單晶P型基板30的表面,可以為鋸齒狀表面,其可讓該N型半導體層40、該表面鈍化層60與該微球狀結構化抗反射層70皆具有鋸齒狀表面,因而可以增加抗反射之效果,而增加太陽電池結構的電池效率。 The surface of the single crystal P-type substrate 30 that is in contact with the N-type semiconductor layer 40 may be a sawtooth surface that allows the N-type semiconductor layer 40, the surface passivation layer 60, and the microspherical structured anti-reflective layer 70. They all have a serrated surface, which can increase the anti-reflection effect and increase the battery efficiency of the solar cell structure.

而本發明的製造方法,首先為取一單晶P型基板30,將該單晶P型基板30用丙酮清洗10分鐘,乙醇清洗10分鐘,去離子水(DI Water)清洗10分鐘,再以攝氏100度烘乾10分鐘。 In the manufacturing method of the present invention, first, a single crystal P-type substrate 30 is taken, and the single crystal P-type substrate 30 is washed with acetone for 10 minutes, ethanol washed for 10 minutes, and deionized water (DI Water) for 10 minutes, and then Dry at 100 degrees Celsius for 10 minutes.

而該N型半導體層40形成於該單晶P型基板30之方式,為使用一旋轉塗佈機將磷擴散溶液均勻旋塗至該單晶P型基板30上,讓該單晶P型基板30為塗佈有磷,其轉速設定成兩階段,其第一轉轉速為1000rpm,時間為15秒,第二轉轉速為3000rpm,時間為20秒。再將該單晶P型基板30放置通入氮氣的高溫爐管中,並以攝氏200度烘烤,烘烤時間為15分鐘,以烘乾表面擴散源有機物。接著將該單晶P型基板30放置於快速退火爐中,先將其抽真空,待真空抽至100毫托耳(mtorr)以下再通入氮氣,其氮氣維持在4-6托耳(torr),退火溫度為攝氏950度,持續約60秒,即完成該N型半導體層40的製作。 The N-type semiconductor layer 40 is formed on the single crystal P-type substrate 30, and the phosphorus diffusion solution is uniformly spin-coated onto the single crystal P-type substrate 30 using a spin coater to allow the single crystal P-type substrate. 30 is coated with phosphorus, and its rotation speed is set to two stages, the first rotation speed is 1000 rpm, the time is 15 seconds, the second rotation speed is 3000 rpm, and the time is 20 seconds. The single crystal P-type substrate 30 was placed in a high-temperature furnace tube through which nitrogen gas was passed, and baked at 200 ° C for 15 minutes to dry the surface diffusion source organic matter. Then, the single crystal P-type substrate 30 is placed in a rapid annealing furnace, which is first evacuated, and vacuum is drawn to 100 mTorr and then nitrogen gas is introduced, and the nitrogen gas is maintained at 4-6 Torr (torr The annealing temperature is 950 degrees Celsius for about 60 seconds, that is, the fabrication of the N-type semiconductor layer 40 is completed.

且在形成該N型半導體層40於該單晶P型基板30之前,該單晶P型基板30接觸該N型半導體層40的表面,可以藉由蝕刻製程形成鋸齒狀表面,即可讓該N型半導體層40、該表面鈍化層60與該微球狀結構化抗反射層70皆具有鋸齒狀表面。 Before the N-type semiconductor layer 40 is formed on the single crystal P-type substrate 30, the single crystal P-type substrate 30 contacts the surface of the N-type semiconductor layer 40, and the sawtooth surface can be formed by an etching process. The N-type semiconductor layer 40, the surface passivation layer 60, and the microspherical structured anti-reflective layer 70 each have a serrated surface.

而該P型半導體層20形成於該單晶P型基板30下之方式,為使用旋轉塗佈機將硼擴散溶液均勻旋塗至該單晶P型基板30上,讓該單晶P型基板 30為塗佈有硼,其轉速設定成兩階段,其第一轉轉速為2000rpm,時間為10秒,第二轉轉速為3000rpm,時間為20秒。將該單晶P型基板30放置通入氮氣的高溫爐管中,並以攝氏200度烘烤,烘烤時間為15分鐘,以烘乾表面擴散源有機物。接著再將該單晶P型基板30放置快速退火爐中,先將其抽真空,待真空抽至100毫托耳(mtorr)以下在通入氮氣,其氮氣維持在4-6托耳(torr),退火溫度為攝氏950度,持續約60秒,即完成該P型半導體層20的製作。 The P-type semiconductor layer 20 is formed under the single crystal P-type substrate 30, and the boron diffusion solution is uniformly spin-coated onto the single crystal P-type substrate 30 using a spin coater to allow the single crystal P-type substrate. 30 is coated with boron, and its rotation speed is set to two stages, and the first rotation speed is 2000 rpm, the time is 10 seconds, the second rotation speed is 3000 rpm, and the time is 20 seconds. The single crystal P-type substrate 30 was placed in a high-temperature furnace tube through which nitrogen gas was passed, and baked at 200 ° C for 15 minutes to dry the surface diffusion source organic matter. Then, the single crystal P-type substrate 30 is placed in a rapid annealing furnace, and then vacuumed first, and vacuum is drawn to 100 mTorr or less, and nitrogen gas is supplied thereto, and the nitrogen gas is maintained at 4-6 Torr (torr The annealing temperature is 950 degrees Celsius for about 60 seconds, that is, the fabrication of the P-type semiconductor layer 20 is completed.

而該表面鈍化層60的製作方式,為使用一濺鍍機系統沉積二氧化鉿(HfO2)薄膜,射頻(rf)功率控制在100-300瓦(W),並通入95%氬(Ar)氣與5%氧氣,時間為4分鐘,腔體壓力控制在5毫托耳(mtorr),厚度約為80奈米(nm)。 The surface passivation layer 60 is formed by depositing a hafnium oxide (HfO 2 ) film using a sputtering system, controlling the radio frequency (rf) power to 100-300 watts (W), and introducing 95% argon (Ar). Gas and 5% oxygen for 4 minutes, chamber pressure controlled at 5 mTorr, and thickness of approximately 80 nm (nm).

請再一併參閱「圖2A」與「圖2B」,而該N型金屬接觸電極50的製作方式,為以熱蒸鍍機系統蒸鍍鋁於該表面鈍化層60上(如「圖2A」),其厚度約為150奈米(nm),且該N型金屬接觸電極50在形成之後,更經過一烘烤程序,藉由該烘烤程序,讓該N型金屬接觸電極50滲透該表面鈍化層60而進入與該N型半導體層40連結(如「圖2B」)。 Please refer to FIG. 2A and FIG. 2B together. The N-type metal contact electrode 50 is formed by vapor deposition of aluminum on the surface passivation layer 60 by a thermal vapor deposition system (eg, FIG. 2A). And a thickness of about 150 nanometers (nm), and after the formation of the N-type metal contact electrode 50, a baking process is performed, and the N-type metal contact electrode 50 is allowed to penetrate the surface by the baking process. The passivation layer 60 enters the N-type semiconductor layer 40 (as shown in FIG. 2B).

同樣的,該P型金屬接觸電極10的製作方式,為以熱蒸鍍機系統蒸鍍鋁於該P型半導體層20下,其厚度約為300奈米(nm)。 Similarly, the P-type metal contact electrode 10 is formed by vapor-depositing aluminum under the P-type semiconductor layer 20 in a thermal vapor deposition system to a thickness of about 300 nanometers (nm).

最後,該微球狀結構化抗反射層70的製作方式,為使用旋轉塗佈機將該微球狀結構化抗反射層70的材料,二氧化矽(SiO2)顆粒粉末溶液均勻的塗佈在該表面鈍化層60具有該N型金屬接觸電極50的一側上,此階段控制第一轉在1000rpm,旋塗時間10秒,第二轉控制在1000-5000rpm,旋塗時間20-40秒。將旋塗好的結構放置高溫退火爐內,進行攝氏300度、時間10分鐘的處理,目的將二氧化矽(SiO2)顆粒內部結晶更凝聚。 Finally, the microspherical structured anti-reflective layer 70 is formed by uniformly coating the material of the microspherical structured anti-reflective layer 70 and the ceria (SiO2) particle powder solution using a spin coater. The surface passivation layer 60 has one side of the N-type metal contact electrode 50. This stage controls the first rotation at 1000 rpm, the spin coating time is 10 seconds, the second rotation is controlled at 1000-5000 rpm, and the spin coating time is 20-40 seconds. The spin-coated structure was placed in a high-temperature annealing furnace and treated at 300 ° C for 10 minutes for the purpose of crystallizing the interior of the cerium oxide (SiO 2 ) particles.

如上所述,本發明於太陽電池結構之內,形成表面鈍化層與微球狀結構化抗反射層,透過該表面鈍化層可以提供保護效果,而該微球狀結構化抗反射層的設置,可以增加太陽光的通過量,又該微球狀結構化抗反射層的製作為在製作P型金屬接觸電極與N型金屬接觸電極之後,因而可以維持良好的抗反射作用,可藉以提昇太陽電池效率。 As described above, the present invention forms a surface passivation layer and a microspherical structured anti-reflective layer within the structure of the solar cell, through which the protective layer can provide a protective effect, and the microspherical structured anti-reflective layer is disposed, The throughput of the sunlight can be increased, and the microspherical structured anti-reflection layer is fabricated after the P-type metal contact electrode and the N-type metal contact electrode are formed, thereby maintaining a good anti-reflection effect, thereby improving the solar cell. effectiveness.

10‧‧‧P型金屬接觸電極 10‧‧‧P type metal contact electrode

20‧‧‧P型半導體層 20‧‧‧P type semiconductor layer

30‧‧‧單晶P型基板 30‧‧‧Single crystal P-type substrate

40‧‧‧N型半導體層 40‧‧‧N type semiconductor layer

50‧‧‧N型金屬接觸電極 50‧‧‧N type metal contact electrode

60‧‧‧表面鈍化層 60‧‧‧ surface passivation layer

70‧‧‧微球狀結構化抗反射層 70‧‧‧Microspherical structured anti-reflective layer

Claims (6)

一種如申請專利範圍第1項所述之太陽電池結構的製作方法,其中為先製作該表面鈍化層於該N型半導體層上側,再讓該N型金屬接觸電極具特定的圖案分佈於該表面鈍化層上側,且經烘烤後,讓該N型金屬接觸電極穿過該表面鈍化層與該N型半導體層連接,最後才於不具該N型金屬接觸電極的該表面鈍化層上側形成該微球狀結構化抗反射層,且該N型半導體層形成於該單晶P型基板之方式,為使用一旋轉塗佈機將磷擴散溶液均勻旋塗至該單晶P型基板上,其轉速設定成兩階段,其第一轉轉速為1000rpm,時間為15秒,第二轉轉速為3000rpm,時間為20秒,接著再將該單晶P型基板放置通入氮氣的高溫爐管中,並以攝氏200度烘烤,烘烤時間為15分鐘,以烘乾表面擴散源有機物,接著將該單晶P型基板放置快速退火爐中,先將其抽真空,待真空抽至100毫托耳以下在通入氮氣,其氮氣維持在4-6托耳,退火溫度為攝氏950度,持續約60秒,即完成該N型半導體層的製作。 The method for fabricating a solar cell structure according to claim 1, wherein the surface passivation layer is first formed on the upper side of the N-type semiconductor layer, and the N-type metal contact electrode is distributed on the surface in a specific pattern. After the upper side of the passivation layer is baked, the N-type metal contact electrode is connected to the N-type semiconductor layer through the surface passivation layer, and finally the micro-layer is formed on the upper surface of the surface passivation layer without the N-type metal contact electrode. a spherical structured antireflection layer, wherein the N-type semiconductor layer is formed on the single crystal P-type substrate, wherein a spin coating machine is used to uniformly spin-coat a phosphorus diffusion solution onto the single crystal P-type substrate, and the rotation speed thereof Set to two stages, the first rotation speed is 1000 rpm, the time is 15 seconds, the second rotation speed is 3000 rpm, and the time is 20 seconds. Then, the single crystal P type substrate is placed in a high temperature furnace tube of nitrogen gas. And baking at 200 degrees Celsius, baking time is 15 minutes to dry the surface diffusion source organic matter, and then placing the single crystal P-type substrate in a rapid annealing furnace, first evacuating it, and vacuuming to 100 millimeters Below the ear, nitrogen is introduced. The nitrogen gas is maintained at 4-6 Torr, and the annealing temperature is 950 ° C for about 60 seconds to complete the fabrication of the N-type semiconductor layer. 如申請專利範圍第1項所述之太陽電池結構的製作方法,其中在形成該N型半導體層於該單晶P型基板之前,該單晶P型基板接觸該N型半導體層的表面,藉由蝕刻製程形成鋸齒狀表面。 The method for fabricating a solar cell structure according to claim 1, wherein the single crystal P-type substrate contacts the surface of the N-type semiconductor layer before forming the N-type semiconductor layer on the single crystal P-type substrate, A sawtooth surface is formed by the etching process. 如申請專利範圍第1項所述之太陽電池結構的製作方法,其中該P型半導體層形成於該單晶P型基板下之方式,為使用一旋轉塗佈機將硼擴散溶液均勻旋塗至該單晶P型基板上,其轉速設定成兩階段,第一轉轉速為2000rpm,時間為10秒,第二轉轉速為3000rpm,時間為20秒,將該單晶P型基板放置通入氮氣的高溫爐管中,並以攝氏200度烘烤,烘烤時間為15分鐘,以烘乾表面擴散源有機物,接著再將該單晶P型基板放置快速退火爐中,先將其抽真空,待真空抽至100m托 耳以下在通入氮氣,其氮氣維持在4-6托耳,退火溫度為攝氏950度,持續約60秒,即完成該P型半導體層20的製作。 The method for fabricating a solar cell structure according to claim 1, wherein the P-type semiconductor layer is formed under the single crystal P-type substrate, and the boron diffusion solution is uniformly spin-coated by using a spin coater. The rotation speed of the single crystal P-type substrate is set to two stages, the first rotation speed is 2000 rpm, the time is 10 seconds, the second rotation speed is 3000 rpm, and the time is 20 seconds. Into a high temperature furnace tube of nitrogen, and baked at 200 degrees Celsius, baking time is 15 minutes to dry the surface diffusion source organic matter, and then the single crystal P-type substrate is placed in a rapid annealing furnace, first pumping it Vacuum, vacuum pumped to 100m Below the ear, nitrogen gas was introduced, the nitrogen gas was maintained at 4-6 Torr, and the annealing temperature was 950 degrees Celsius for about 60 seconds to complete the fabrication of the P-type semiconductor layer 20. 如申請專利範圍第1項所述之太陽電池結構的製作方法,其中該表面鈍化層的製作方式,為使用一濺鍍機系統沉積二氧化鉿薄膜,射頻功率控制在100-300瓦,並通入95%氬氣與5%氧氣,時間為4分鐘,腔體壓力控制在5毫托耳,厚度約為80奈米。 The method for fabricating a solar cell structure according to claim 1, wherein the surface passivation layer is formed by depositing a ruthenium dioxide film using a sputtering system, and the RF power is controlled at 100-300 watts. 95% argon and 5% oxygen were added for 4 minutes, the chamber pressure was controlled at 5 mTorr, and the thickness was about 80 nm. 如申請專利範圍第1項所述之太陽電池結構的製作方法,其中該N型金屬接觸電極的製作方式,為以熱蒸鍍機系統蒸鍍鋁於該表面鈍化層上,其厚度約為150奈米,且該N型金屬接觸電極在形成之後,更經過一烘烤程序,藉由該烘烤程序,讓該N型金屬接觸電極滲透該表面鈍化層而進入與該N型半導體層連結。 The method for fabricating a solar cell structure according to claim 1, wherein the N-type metal contact electrode is formed by vapor-depositing aluminum on the surface passivation layer by a thermal vapor deposition system, and has a thickness of about 150. After the N-type metal contact electrode is formed, the N-type metal contact electrode is infiltrated into the surface passivation layer to be connected to the N-type semiconductor layer by a baking process. 如申請專利範圍第1項所述之太陽電池結構的製作方法,其中該微球狀結構化抗反射層的製作方式,為使用旋轉塗佈機將該微球狀結構化抗反射層的材料,二氧化矽顆粒粉末溶液均勻的塗佈在該表面鈍化層具有該N型金屬接觸電極的一側上,此階段控制第一轉在1000rpm,旋塗時間10秒,第二轉控制在1000-5000rpm,旋塗時間20-40秒,將旋塗好的結構放置高溫退火爐內,進行攝氏300度、時間10分鐘的處理,目的將二氧化矽顆粒內部結晶更凝聚。 The method for fabricating a solar cell structure according to claim 1, wherein the microspherical structured antireflection layer is formed by using a spin coater to form the microspherical structured antireflection layer. The cerium oxide particle powder solution is uniformly coated on the side of the surface passivation layer having the N-type metal contact electrode. At this stage, the first rotation is controlled at 1000 rpm, the spin coating time is 10 seconds, and the second rotation is controlled at 1000-5000 rpm. The spin coating time is 20-40 seconds, and the spin-coated structure is placed in a high-temperature annealing furnace for treatment at 300 ° C for 10 minutes for the purpose of crystallizing the interior of the cerium oxide particles.
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