TWI523361B - Applicable to high voltage system - Google Patents

Description

Electrostatic discharge protection circuit for high voltage systems

The invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit suitable for a high voltage system.

The generation of static electricity is ubiquitous, especially the sensitivity of electronic components. When static electricity is generated, the electronic components are used to transmit electronic signals, which is a good conductor relative to the human body, so the static charge is quickly guided. To electronic components, and because the electrostatic discharge (ESD) voltage is much larger than the power supply voltage provided by the general, the general electronic module is likely to suffer from electrostatic discharge in actual use or test. damage.

At present, the most sensitive component for electrostatic discharge is an integrated circuit mainly composed of a metal oxide semiconductor. In view of the fact that when an electronic module encounters an instantaneous electrostatic charge, it is easy to cause damage or burnt of components or conductive lines, thereby affecting the function of the module. Therefore, an electrostatic discharge protection circuit or component needs to be added to the overall module design.

However, the inside of a conventional ESD protection circuit usually has an RC start-up circuit, and the capacitance in the RC start-up circuit is generally designed to be only 5V withstand voltage, so it cannot be applied to a high-voltage system when the high-voltage system is operating or electrostatically discharged. This capacitor is very likely to burn out due to overvoltage or overcurrent.

Accordingly, the present invention has been made in view of the above problems with an electrostatic discharge protection circuit suitable for use in a high voltage system.

An object of the present invention is to provide an ESD protection circuit suitable for a high voltage system, wherein a voltage division of a plurality of resistors is used to limit a voltage across a capacitor of the startup circuit, thereby preventing a capacitor of the startup circuit from operating voltage during operation. Or damage caused by the electrostatic discharge voltage during static electricity protection.

Another object of the present invention is to provide an ESD protection circuit suitable for a high voltage system, which uses a current mirror effect of a mirror circuit to limit the current flowing through the capacitor and prevent the capacitance of the startup circuit from being operated during operation. Damage caused by voltage or static discharge voltage during static electricity protection.

In order to achieve the above-mentioned various purposes, the present invention discloses an electrostatic discharge protection circuit suitable for a high voltage system, comprising: a first resistor coupled to a first power line and according to one of the first power lines Inputting a power source to generate a control voltage; a discharge circuit coupled to the first power line and the first resistor, and discharging the input power source according to the control voltage; and a second resistor coupled to the first resistor and the second power line And generating a resistance current flowing through one of the second resistors according to the control voltage, and generating a resistance voltage across one of the second resistors; a mirror circuit that mirrors a capacitive current according to the resistance current; and a capacitor Receiving and charging according to the capacitor current to generate a capacitor voltage across one of the capacitors, and the voltage drop of the resistor voltage determines the voltage drop of the capacitor voltage.

The electrostatic discharge protection circuit of the present invention applied to a high voltage system limits the voltage across the capacitor by dividing the voltage of the plurality of resistors, and limits the current flowing through the capacitor by the current mirror effect of the mirror circuit, so that the capacitor acts as a capacitor When the capacitance of the starting circuit of the high-voltage circuit is not caused by the operating voltage during operation or the electrostatic discharge voltage during static electricity protection, the capacitor is damaged to achieve the protective effect.

10‧‧‧Electrostatic discharge protection circuit
101‧‧‧Discharge circuit
103‧‧‧Mirror circuit
C‧‧‧ capacitor
GND‧‧‧ ground terminal
L1, L2‧‧‧ power cord
Capacitive current I _C ‧‧‧
I _R ‧‧‧Resistor current
M1, M3, M4‧‧‧P type transistor
M2, M5, M6‧‧‧N type transistors
R1, R2, R3‧‧‧ resistance
R4‧‧‧Adjusting resistance
V _C ‧‧‧capacitor voltage
V _CON ‧‧‧Control voltage
V _DD ‧‧‧ operating voltage
V _ESD ‧‧‧electrostatic discharge voltage
V _R ‧‧‧resistance voltage
V _S ‧‧‧Switching signal
V _SS ‧‧‧negative voltage

Figure 1 is a circuit diagram of an electrostatic discharge protection circuit according to a first embodiment of the present invention;
Figure 2 is a circuit diagram of an electrostatic discharge protection circuit according to a second embodiment of the present invention;
Fig. 3 is a circuit diagram of an electrostatic discharge protection circuit according to a third embodiment of the present invention; and Fig. 4 is a circuit diagram of an electrostatic discharge protection circuit according to a fourth embodiment of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows:

Please refer to FIG. 1, which is a circuit diagram of an electrostatic discharge protection circuit according to a first embodiment of the present invention. As shown, the ESD protection circuit 10 of the present embodiment includes a plurality of resistors R1, R2, a discharge circuit 101, a mirror circuit 103, and a capacitor C. The resistor R1 is coupled to a power line L1 and generates a control voltage V _CON according to one of the input power sources on the power line L1. The discharge circuit 101 is coupled to the resistor R1, the power line L1 and a power line L2, and discharges the input power to the power line L2 according to the control voltage V _CON . The resistor R2 is coupled between the resistor R1 and the power line L2, and generates a resistor current I _R flowing through the resistor R2 according to the control voltage V _CON , and generates a resistor voltage V _R across the resistor R2 , and the resistor of the resistor R2 The value determines the amount of current of the resistor current I _R . The mirror circuit 103 is coupled between the resistor R1 and the resistor R2, the capacitor C, and between the resistor R2, the capacitor C and the power line L2, and is mirrored according to the resistor current I _R to generate a capacitor current I _C . Capacitor C is coupled to the mirror circuit 103, and receives the capacitive current I _C is charged, and the capacitance C by charging the capacitor current I _C, is generated across the capacitor C in one capacitor voltage V _C.

The input power source can be an operating voltage V _DD or an electrostatic discharge voltage V _ESD , that is, the power line L1 can be used to receive the input power supply operating voltage V _DD or the electrostatic discharge voltage V _ESD . The power line L2 can be used to receive a negative voltage V _SS or to be coupled to a ground GND (zero potential).

The discharge circuit 101 of this embodiment includes a P-type transistor M1, a resistor R3, and an N-type transistor M2. One of the P-type transistor M1 coupled to the power source line L1, P-type transistor M1, one gate is coupled to a resistor R1, to receive a control voltage V _CON, and the control voltage V _CON according to the power switch input. The resistor R3 is coupled between the drain of one of the P-type transistors M1 and the power line L2, and receives the input power according to the switching state of the P-type transistor M1 to generate a switching signal V _S . One of the N-type transistors M2 is coupled to the power line L1, one source of the N-type transistor M2 is coupled to the power line L2, and one of the gates of the N-type transistor M2 is coupled to the drain of the P-type transistor M1. To receive and switch according to the switching signal V _S to discharge the input power to the power line L2.

However, the above is only a circuit architecture of a discharge circuit of a preferred embodiment, and is not intended to limit the present invention. Those skilled in the art are familiar with a circuit architecture of a plurality of discharge circuits in place of the discharge circuit 101 described above.

Referring to FIG. 1 , the mirror circuit 103 of the present embodiment includes two sets of current mirrors. A set of current mirrors are coupled between the resistor R2 , the capacitor C and the resistor R1 , and are mirrored according to the resistor current I _R to generate a capacitor current I. _C , and the current mirror comprises a plurality of P-type transistors M3, M4. One source of the P-type transistor M3 is coupled to the resistor R1, and one of the P-type transistors M3 is coupled to the gate of the resistor R2 and the P-type transistor M3. One source of the P-type transistor M4 is coupled to the source of the P-type transistor M3 and the resistor R1, one of the P-type transistors M4 is coupled to the capacitor C, and one of the gates of the P-type transistor M4 is coupled to the P. The gate of the transistor M3.

The other current mirror is coupled between the resistor R2, the capacitor C, and the power line L2, and is mirrored according to the resistor current I _R to generate a capacitor current I _C , and the current mirror includes a plurality of N-type transistors M5 and M6. One of the N-type transistors M5 has a drain and a gate coupled to the resistor R2, and a source of the N-type transistor M5 is coupled to the power line L2. One of the N-type transistors M6 is coupled to the capacitor C, the gate of the N-type transistor M5 of the N-type transistor M6, and the source of the N-type transistor M6 is coupled to the power line L2.

Wherein, the size ratio of the P-type transistors M3 and M4 and the size ratio of the N-type transistors M5 and M6 determine the ratio of the resistance current I _R to the capacitance current I _C , that is, the size ratio of the P-type transistors M3 and M4 and N The size ratio of the type of transistors M5 and M6 determines the amount of current of the capacitor current I _C .

When the ESD protection circuit 10 of the embodiment is in the electrostatic discharge mode, the ESD voltage V _{ESD is} generated on the power line L1. Since the ESD voltage V _ESD rises instantaneously, the ESD voltage V _ESD generates a voltage across the resistor R1. Therefore, the control voltage V _{CON is} at a low level at this moment, and the P-type transistor M1 is turned on, so that the electrostatic discharge voltage V _ESD is transmitted to the resistor R3 via the P-type transistor M1 to generate the switching signal V _S , thereby turning on the N The transistor M2 causes the discharge circuit 101 to discharge the electrostatic discharge voltage V _ESD to the power source line L2 via the N-type transistor M2. Then, the current flowing through the resistor R1 is shunted into the resistor current I _R and the capacitor current I _C through the mirror circuit 103, and the capacitor C is charged by the capacitor current I _C and gradually rises to a high level, that is, the control voltage V _CON gradually rises. At the highest level, the discharge circuit 101 is turned off to stop the discharge.

In addition, in the normal operation mode of the ESD protection circuit 10 of the present embodiment, the operating voltage V _{DD is} generated on the power line L1. Since the rising speed of the operating voltage V _DD is slow, the control voltage V _CON is due to the resistor R1 and the capacitor C. The RC delay (RC Delay) is a high level, and the P-type transistor M1 is turned off. Therefore, the discharge circuit 101 does not discharge the operating voltage V _DD to the power supply line L2.

Because, when both electrostatic discharge mode or the normal operation mode, control the voltage level of the voltage V _CON highest will be only equal to the voltage dividing resistor R1 and the circuit composed of the mirror circuit 103, resistor R2, capacitor C, and resistor R2 The resistance voltage V _R is also limited to the voltage division. If the P-type transistors M3 and M4 of the mirror circuit 103 and the on-voltages of the N-type transistors M5 and M6 are not considered, the control voltage V _CON is equal to the resistance voltage V. _R , and the resistor R2 and the capacitor C are equivalent to a parallel relationship, so the capacitor voltage V _C across the capacitor _C is only charged to be equal to the resistor voltage V _R and will not continue to be charged to the input power source on the power line L1 ( The voltage drop of the electrostatic discharge voltage V _ESD or the operating voltage V _DD ), that is, the resistance voltage V _R , determines the voltage drop of the capacitor voltage V _C .

In addition, since the control voltage V _CON is limited to the voltage division of the circuit composed of the resistor R1 and the mirror circuit 103, the resistor R2, and the capacitor C, the resistance current I _R flowing through the resistor R2 is determined by the control voltage V _CON and The resistance value of the resistor R2, in other words, the amount of current of the resistor current I _R is also limited to the control voltage V _CON divided by the resistor R2. Moreover, since the capacitance current I _C flowing through the capacitor C is mirrored by the mirror circuit 103 according to the resistance current I _R , the current amount of the capacitor current I _C is also limited.

As can be seen from the above, the ESD protection circuit 10 of the present embodiment limits the voltage across the capacitor C (capacitor voltage V _C ) by the voltage division of the resistors R1 and R2, and the P-type transistor M3 of the mirror circuit 103. The current mirror effect of M4 and N-type transistors M5 and M6 to limit the capacitor current I _C flowing through the capacitor _C , so that the capacitor C is used as the capacitor of the startup circuit for high-voltage circuit operation or static electricity protection, not because of the large The voltage or instantaneous high current is damaged and the protective effect is achieved.

Furthermore, the mirror circuit 103 of the ESD protection circuit 10 of the present embodiment includes two sets of current mirrors (P-type transistors M3, M4 and N-type transistors M5, M6), and therefore, can be stably based on the resistance current I. _R and mirroring produces a capacitive current I _C . However, the present invention is not limited thereto, and the present invention can also use only one of the current mirrors composed of the P-type transistors M3, M4 or the N-type transistors M5 and M6 as the current mirror for generating the capacitive current I _C by mirror, and the details The connection relationship of the circuits will be described in the second and third figures.

Please refer to FIG. 2, which is a circuit diagram of an ESD protection circuit according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the mirror circuit of the embodiment includes only the current mirror composed of the P-type transistors M3 and M4, and the working principle of the electrostatic discharge protection circuit 10 of the embodiment is In the same manner as in the previous embodiment, the voltage division of the resistors R1, R2 is used to limit the voltage across the capacitor C (capacitor voltage V _C ), and only by the current mirror effect of the P-type transistors M3, M4 of the mirror circuit 103. In order to limit the capacitive current I _C flowing through the capacitor C, the capacitor C is used as the capacitor of the starting circuit for the operation of the high voltage circuit or the static electricity protection, and is not damaged by the large voltage or the instantaneous large current, thereby achieving the protection effect. .

Please refer to FIG. 3, which is a circuit diagram of an electrostatic discharge protection circuit according to a third embodiment of the present invention. The difference between this embodiment and the first embodiment is that the mirror circuit of the embodiment includes only the current mirror composed of the N-type transistors M5 and M6, and the working principle of the electrostatic discharge protection circuit 10 of the embodiment is In the same manner as the previous embodiment, the voltage division of the resistors R1 and R2 is also used to limit the voltage across the capacitor C (capacitance voltage V _C ), and only by the current mirror effect of the N-type transistors M5 and M6 of the mirror circuit 103. In order to limit the capacitive current I _C flowing through the capacitor C, the capacitor C is used as the capacitor of the starting circuit for the operation of the high voltage circuit or the static electricity protection, and is not damaged by the large voltage or the instantaneous large current, thereby achieving the protection effect. .

Please refer to FIG. 4, which is a circuit diagram of an electrostatic discharge protection circuit according to a fourth embodiment of the present invention. The difference between the present embodiment and the first embodiment is that the ESD protection circuit 10 of the present embodiment further includes an adjustment resistor R4. The adjustment resistor R4 is coupled between the resistor R1 and the resistor R2, and the resistance value of the adjustment resistor R4 determines the control. Voltage level of voltage V _CON . Thus, the resistance can be adjusted by changing the value of the resistor R4, and to adjust the desired voltage level of the control voltage V _CON, the different circuits required to match.

In summary, the electrostatic discharge protection circuit of the present invention suitable for a high voltage system uses a voltage division of a plurality of resistors to limit the voltage across the capacitor and to limit the flow through the capacitor by the current mirror effect of the mirror circuit. When the current is used as the capacitance of the starting circuit of the high-voltage circuit, the capacitor will not be damaged due to the operating voltage during operation or the electrostatic discharge voltage during electrostatic protection, so as to achieve the protective effect.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

10‧‧‧Electrostatic discharge protection circuit

101‧‧‧Discharge circuit

103‧‧‧Mirror circuit

C‧‧‧ capacitor

GND‧‧‧ ground terminal

L1‧‧‧Power cord

L2‧‧‧Power cord

Capacitive current I _C ‧‧‧

I _R ‧‧‧Resistor current

M1‧‧‧P type transistor

M2‧‧‧N type transistor

M3‧‧‧P type transistor

M4‧‧‧P type transistor

M5‧‧‧N type transistor

M6‧‧‧N type transistor

R1‧‧‧ resistance

R2‧‧‧ resistance

R3‧‧‧ resistance

V _C ‧‧‧capacitor voltage

V _CON ‧‧‧Control voltage

V _DD ‧‧‧ operating voltage

V _ESD ‧‧‧electrostatic discharge voltage

V _R ‧‧‧resistance voltage

The switching signal V _S ‧‧‧

V _SS ‧‧‧negative voltage

Claims (10)

An electrostatic discharge protection circuit comprising:
a first resistor coupled to a first power line and inputting a power source according to one of the first power lines to generate a control voltage;
a discharge circuit coupled to the first power line and the first resistor, and discharging the input power according to the control voltage;
a second resistor coupled between the first resistor and a second power line, and generating a resistance current flowing through the second resistor according to the control voltage, and generating a resistance voltage across the second resistor ;
a mirror circuit that mirrors a capacitive current according to the resistance current; and a capacitor that receives and charges according to the capacitor current to generate a capacitor voltage across the capacitor, the voltage drop of the resistor voltage determines The voltage drop of the capacitor voltage. The electrostatic discharge protection circuit of claim 1, wherein the resistance value of the second resistor determines a current amount of the resistor current, and further determines a current amount of the capacitor current. The electrostatic discharge protection circuit of claim 1, further comprising:
An adjustment resistor is coupled between the first resistor and the second resistor, and the resistance value of the adjustment resistor determines a voltage level of the control voltage. The electrostatic discharge protection circuit of claim 1, wherein the mirror circuit comprises:
a current mirror coupled between the first resistor, the second resistor and the capacitor, and mirrored to generate the capacitor current according to the resistor current;
The second resistor is coupled between the current mirror and the second power line, and the capacitor is coupled between the current mirror and the second power line. The electrostatic discharge protection circuit of claim 4, wherein the current mirror comprises:
a first P-type transistor, one source of the first P-type transistor is coupled to the first resistor, and one of the first P-type transistors is coupled to the second resistor and the first P-type a gate of the transistor; and a second P-type transistor, one source of the second P-type transistor is coupled to the source of the first P-type transistor and the first resistor, the second P One of the gates is coupled to the capacitor, and one of the gates of the second P-type transistor is coupled to the gate of the first P-type transistor;
The ratio of the size of the first P-type transistor to the size of the second P-type transistor determines the amount of current of the capacitor current. The electrostatic discharge protection circuit of claim 1, wherein the mirror circuit comprises:
a current mirror coupled between the second resistor, the capacitor and the second power line, and mirrored to generate the capacitor current according to the resistor current;
The second resistor is coupled between the first resistor and the current mirror, and the capacitor is coupled between the first resistor and the current mirror. The electrostatic discharge protection circuit of claim 6, wherein the current mirror comprises:
a first N-type transistor, one source of the first N-type transistor is coupled to the second power line, and one of the first N-type transistors is coupled to the second resistor and the first N a gate of the type of transistor; and a second N-type transistor, one source of the second N-type transistor is coupled to the second power line, and one of the second N-type transistors is coupled to the gate a capacitor, and one of the gates of the second N-type transistor is coupled to the gate of the first N-type transistor;
The ratio of the size of the first N-type transistor to the size of the second N-type transistor determines the amount of current of the capacitor current. The electrostatic discharge protection circuit of claim 1, wherein the mirror circuit comprises:
a first current mirror coupled between the first resistor, the second resistor and the capacitor, and mirrored to generate the capacitor current according to the resistor current; and a second current mirror coupled to the second resistor, The capacitor and the second power line are mirrored according to the resistance current to generate the capacitor current;
The second resistor is coupled between the first current mirror and the second current mirror, and the capacitor is coupled between the first current mirror and the second current mirror. The electrostatic discharge protection circuit of claim 1, wherein the discharge circuit comprises:
a P-type transistor, one source of the P-type transistor is coupled to the first power line, and one of the P-type transistors is coupled to the first resistor, and the input power is switched according to the control voltage ;
a third resistor coupled between the second power line and one of the P-type transistors, and receiving the input power according to a switching state of the P-type transistor to generate a switching signal; and a N a type of transistor, wherein one of the N-type transistors is coupled to the first power line, and one of the N-type transistors is coupled to the third resistor and the drain of the first transistor, and The signal is switched to switch to discharge the input power to the second power line. The ESD protection circuit of claim 1, wherein the first power line receives an operating voltage or an ESD voltage of the input power source, and the second power line is coupled to a ground or receives a Negative voltage.