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TWI523255B - Method for manufacturing light-emitting device on substrate - Google Patents

Method for manufacturing light-emitting device on substrate Download PDF

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Publication number
TWI523255B
TWI523255B TW097105101A TW97105101A TWI523255B TW I523255 B TWI523255 B TW I523255B TW 097105101 A TW097105101 A TW 097105101A TW 97105101 A TW97105101 A TW 97105101A TW I523255 B TWI523255 B TW I523255B
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Taiwan
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metallization
manufacturing
deposited
metal plating
feedthrough
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TW097105101A
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Chinese (zh)
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TW200901511A (en
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許利爾
威雀爾
葛伊森
何思裘
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晶元光電股份有限公司
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/8506Containers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/855Optical field-shaping means, e.g. lenses
    • H10H20/856Reflecting means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/85Packages
    • H10H20/857Interconnections, e.g. lead-frames, bond wires or solder balls
    • H10W72/884
    • H10W90/754

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Description

將發光裝置封裝於基板之製造方法 Method for manufacturing light-emitting device on substrate

本揭示是關於在基板上具有發光裝置的封裝之製造方法。The present disclosure relates to a method of manufacturing a package having a light-emitting device on a substrate.

存放發光二極體(LED)或其他發光裝置之封裝的設計是使自封裝輸出之光線量最佳化的重要因素。LED常被存放在包含多個元件的封裝中,其佔據比LED晶片本身大很多的面積。為了增加自封裝發出之光線量,有時會在封裝的內表面上提供反射性材料,諸如鍍金屬。為了使自封裝反射出的光線量最大化,最好封裝內部的顯要部份上提供反射性材料。The design of a package for storing light-emitting diodes (LEDs) or other light-emitting devices is an important factor in optimizing the amount of light output from the package. LEDs are often stored in packages containing multiple components that occupy a much larger area than the LED chips themselves. In order to increase the amount of light emitted from the package, reflective materials such as metallization are sometimes provided on the inner surface of the package. In order to maximize the amount of light reflected from the package, it is preferred to provide a reflective material on a significant portion of the interior of the package.

在某些封裝中,LED晶片被接合至導熱墊片。反射性鏡面之鍍金屬亦可作為部份傳導墊片和鍍穿晶圓互連的薄膜堆疊。然而,這些處理易使製程複雜化,並減少可被用來自封裝反射出光線的封裝表面量。In some packages, the LED wafer is bonded to a thermally conductive gasket. The metallization of the reflective mirror can also be used as a thin film stack of partially conductive pads and plated through wafer interconnects. However, these processes tend to complicate the process and reduce the amount of package surface that can be used to reflect light from the package.

在一面向中,一種具有諸如LED之發光裝置的封裝之製造方法包含:沉積第一鍍金屬,以形成將在其上安裝該發光裝置的傳導墊片,並形成延伸通過支撐該傳導墊片之半導體材料的一或多個饋通(feed-through)互連。隨後,沉積第二鍍金屬,以形成用於將該發光裝置所發出之光線反射通過該封裝之上蓋的反射面。該第二鍍金屬的沉積與該第一鍍金屬的沉積分離(de-coupled),在某些情況中,其可增加反射性鍍金屬所覆蓋的 面積,從而提高自該封裝反射出的光線量。In one aspect, a method of fabricating a package having a light emitting device such as an LED includes depositing a first metallization to form a conductive pad on which the light emitting device will be mounted, and forming an extension through the support of the conductive pad One or more feed-through interconnections of semiconductor material. Subsequently, a second metallization is deposited to form a reflective surface for reflecting the light emitted by the illumination device through the cover over the package. The deposition of the second metallization is de-coupled from the deposition of the first metallization, which in some cases may increase the coverage of the reflective metallization The area, thereby increasing the amount of light reflected from the package.

在某些實施形態中,沉積該第一鍍金屬以便在該傳導墊片和該等饋通互連之每一者的頂部周圍形成各個懸突部。該第二鍍金屬被沉積在該半導體材料的表面上,使得該等懸突部係作為屏蔽,以實質防止該第二鍍金屬被沉積在該等懸突部正下方的區域上。此一技術使該第二鍍金屬得以形成與該傳導墊片和該等饋通互連電氣地中斷之反射面。In some embodiments, the first metallization is deposited to form respective overhangs around the top of each of the conductive shim and the feedthrough interconnects. The second metallization is deposited on the surface of the semiconductor material such that the overhangs act as a shield to substantially prevent the second metallization from being deposited on regions directly below the overhangs. This technique allows the second metallization to form a reflective surface that is electrically interrupted by the conductive pads and the feedthrough interconnects.

某些實施形態包含在半導體晶圓的第一側形成凹腔,並形成從該凹腔的底部延伸至該晶圓的第二側之一或多個通孔。沉積該第一鍍金屬,以形成用於安裝該發光裝置的該傳導墊片,並形成延伸通過該一或多個通孔的饋通互連。沉積該第一鍍金屬以便在該傳導墊片和該等饋通互連之每一者的頂部周圍形成懸突部。該第二鍍金屬被沉積在該半導體晶圓的該第一側上,包含在該凹腔的底部和側表面上,以及在該傳導墊片和該等饋通互連的上表面上。該等懸突部係作為屏蔽,以實質防止該第二鍍金屬被沉積在該等懸突部正下方的區域上。自該傳導墊片和該等饋通互連的上表面選擇性地移除該第二鍍金屬,使得該剩下的第二鍍金屬形成與該傳導墊片和該等饋通互連電氣地中斷的反射面。然後將該發光裝置安裝在該傳導墊片上。Some embodiments include forming a cavity on a first side of the semiconductor wafer and forming one or more vias extending from a bottom of the cavity to a second side of the wafer. The first metallization is deposited to form the conductive pad for mounting the light emitting device and form a feedthrough interconnect extending through the one or more vias. The first metallization is deposited to form overhangs around the top of each of the conductive pads and the feedthrough interconnects. The second metallization is deposited on the first side of the semiconductor wafer, on the bottom and side surfaces of the cavity, and on the conductive pad and the upper surface of the feedthrough interconnect. The overhangs serve as a shield to substantially prevent the second metallization from being deposited on the area directly under the overhangs. Selectively removing the second metallization from the conductive pads and upper surfaces of the feedthrough interconnects such that the remaining second metallization is electrically interconnected with the conductive pads and the feedthroughs Interrupted reflective surface. The illuminating device is then mounted on the conductive shim.

附圖及以下敘述中將陳述本發明之一或多個實施例的細節。本發明的其他特徵及優點將由詳細說明、附圖、及申請專利範圍所闡明。The details of one or more embodiments of the invention are set forth in the drawings Other features and advantages of the invention will be set forth in the description and appended claims.

如第1圖的範例所述,兩結構12、14被銲接在一起,以提供封入諸如LED 16之發光裝置的密封封裝10。亦可使用銲接以外的技術(例如,但不限於:陽極接合和黏著接合)。上結構12作為上蓋,並可被LED 16發出的波長所穿透。As illustrated in the example of FIG. 1, the two structures 12, 14 are soldered together to provide a hermetic package 10 enclosing a light emitting device such as LED 16. Techniques other than soldering (such as, but not limited to, anodic bonding and adhesive bonding) can also be used. The upper structure 12 acts as an upper cover and can be penetrated by the wavelength emitted by the LEDs 16.

在所述範例中,LED晶片16被安裝在作為基底的下結構14上之傳導墊片18上。在基底結構14的凹腔側表面上設置有銲接密封環20,用以密封地將上蓋12裝附於該基底。In the illustrated example, LED wafer 16 is mounted on conductive spacers 18 on lower structure 14 as a substrate. A welded seal ring 20 is provided on the cavity side surface of the base structure 14 for sealingly attaching the upper cover 12 to the base.

第2圖是LED晶片16被移除之基底14的上視圖。Figure 2 is a top view of the substrate 14 with the LED wafer 16 removed.

如第1圖和第2圖所示,LED 16被安裝在形成於基底14中的凹腔22內,該基底14亦包含饋通鍍金屬24。其他電路及被動元件可被安裝在凹腔22中並封入該封裝內。饋通鍍金屬24延伸通過基底14之下部位中的一或多個微貫孔(亦即:通孔)。如第1圖的範例所述,饋通鍍金屬24沿著基底14的外表面延伸,並可被電連接至印刷電路板組件的銲料隆點26。銲線28可提供從LED晶片16至饋通鍍金屬24的電連接。抑或,可將LED 16直接覆晶連接至饋通鍍金屬24。鍍金屬30亦被設置於基底14的內表面上,包含底部32和側壁34,並作為用以將LED 16所發出之額外光線反射通過上蓋12的鏡面。As shown in FIGS. 1 and 2, the LED 16 is mounted in a cavity 22 formed in a substrate 14, which also includes a feedthrough metallization 24. Other circuits and passive components can be mounted in the cavity 22 and enclosed within the package. The feedthrough metallization 24 extends through one or more microvias (i.e., vias) in the lower portion of the substrate 14. As depicted in the example of FIG. 1, feedthrough metallization 24 extends along the outer surface of substrate 14 and can be electrically connected to solder bumps 26 of the printed circuit board assembly. Wire bond 28 can provide an electrical connection from LED wafer 16 to feedthrough metallization 24. Alternatively, the LED 16 can be directly flip-chip bonded to the feedthrough metallization 24. Metallization 30 is also disposed on the inner surface of substrate 14, including bottom 32 and side walls 34, and serves as a mirror for reflecting additional light from LEDs 16 through upper cover 12.

舉例來說,基底14可由矽晶圓所形成,並使用標準技術將凹腔22和饋通鍍金屬24之通孔蝕刻至其中。舉例來說,可使用雙面蝕刻技術。For example, the substrate 14 can be formed from a germanium wafer and the vias 22 and the vias of the feedthrough metallization 24 are etched therein using standard techniques. For example, a double sided etching technique can be used.

隨後沉積墊片18和饋通連接24之鍍金屬,以及鏡面鍍金屬30。如下文將更詳細說明地,鏡面鍍金屬30之沉積是與墊片18和饋通連接24的鍍金屬之沉積分離。The metallization of the spacer 18 and the feedthrough connection 24 is then deposited, as well as the mirror metallization 30. As will be explained in more detail below, the deposition of mirror metallization 30 is separated from the deposition of metallization of spacers 18 and feedthrough connections 24.

第3~7圖描繪沉積多種鍍金屬層的製造步驟。如第3圖所示,在蝕刻凹腔22和饋通鍍金屬24之通孔,以及沉積或生長鈍化層之後,將薄膜鍍金屬堆疊40沉積在晶圓的表面上,包含在該凹腔和該等通孔中。在所述範例中,薄膜堆疊40包含鋁(Al)、鈦(Ti)、鎳(Ni)和金(Au)之層。其他實施形態可包含少於所有前述材料。此外,在其他實施形態中可針對該薄膜堆疊而包含額外或不同的材料。Figures 3 through 7 depict the manufacturing steps for depositing various metallized layers. As shown in FIG. 3, after etching the recess 22 and the via of the feedthrough metal 24, and depositing or growing a passivation layer, a thin film metallization stack 40 is deposited on the surface of the wafer, contained in the cavity and In these through holes. In the illustrated example, film stack 40 comprises a layer of aluminum (Al), titanium (Ti), nickel (Ni), and gold (Au). Other embodiments may include less than all of the foregoing materials. Furthermore, additional or different materials may be included for the film stack in other embodiments.

接著,將薄鍍模42設置在除了將被沉積饋通鍍金屬24和傳導墊片18之區域以外的矽晶圓表面上。可使用光阻遮罩來作為鍍模42。雖然第3~7圖描繪關於饋通鍍金屬24之範例,但對墊片鍍金屬18亦使用相同的處理。舉例來說,可藉由包含旋塗、浸塗、噴塗或電沉積之數種技術中的任一種來沉積該光阻遮罩。Next, the thin plated mold 42 is placed on the surface of the tantalum wafer except for the region where the feedthrough metallization 24 and the conductive spacer 18 are to be deposited. A photoresist mask can be used as the plating mold 42. Although Figures 3-7 depict an example of feedthrough metallization 24, the same treatment is applied to the gasket metallization 18. For example, the photoresist mask can be deposited by any of several techniques including spin coating, dip coating, spray coating, or electrodeposition.

在沉積鍍模42之後,舉例來說,使用電鍍處理來沉積饋通連接24和墊片18之鍍金屬。所電鍍之鍍金屬18、24係被沉積而使得在各導體線及/或墊片的頂部周圍有懸突部。此一懸突部100的放大例係描繪於第8圖。在後續製程期間,懸突部100係作為屏蔽,以防止鏡面鍍金屬30被沉積得太靠近饋通連接24和墊片18之鍍金屬的側邊緣。After depositing the plating mold 42, for example, a plating process is used to deposit the metallization of the feedthrough connection 24 and the spacer 18. The plated metallization 18, 24 is deposited such that there are overhangs around the top of each conductor wire and/or pad. An enlarged example of this overhanging portion 100 is depicted in Fig. 8. During subsequent processing, the overhang 100 is used as a shield to prevent the mirror metallization 30 from being deposited too close to the metallized side edges of the feedthrough connection 24 and the spacer 18.

在所述範例中,金(Au)或金-錫被用來作為饋通連接24和墊片18的鍍金屬。一旦所沉積之金的厚度超過鍍模42的厚度,該金層的等向性生長便會導致形成懸突部100。在所述範例中,鍍模42的厚度約為7~8微米(μm),而該金鍍金屬的厚度約為10 μm。該等懸突部的厚度約為2~3 μm。同樣地,在所述範例中,懸突部100延伸超過該鍍金屬的下部約2~3 μm。在其他實施形 態中,這些值可不同。In the example, gold (Au) or gold-tin is used as the metallization of the feedthrough connection 24 and the spacer 18. Once the thickness of the deposited gold exceeds the thickness of the plating mold 42, the isotropic growth of the gold layer results in the formation of the overhang 100. In the illustrated example, the thickness of the plating mold 42 is about 7 to 8 micrometers (μm), and the thickness of the gold metal plating is about 10 μm. The thickness of the overhangs is about 2 to 3 μm. Similarly, in the illustrated example, the overhang 100 extends beyond the lower portion of the metallization by about 2 to 3 μm. In other implementations These values can be different.

接著,如第4圖所述,移除鍍模42,並將剩下的薄膜堆疊40圖案化,以在該矽晶圓的背面形成金屬結構,諸如銲接合(solder bond)44和銲壩(solder dam)46。在所述範例中,銲接合44包含膜堆疊40的所有層;銲壩46包含該Al和Ti層。Next, as described in FIG. 4, the plating mold 42 is removed and the remaining film stack 40 is patterned to form a metal structure, such as a solder bond 44 and a solder dam, on the back side of the germanium wafer ( Solder dam)46. In the illustrated example, the weld 44 includes all of the layers of the film stack 40; the weld dam 46 includes the Al and Ti layers.

接著,如第5圖所示,鏡面鍍金屬(例如:鋁)30被實質沉積在基底14之凹腔側的所有露出區域上。可使用蒸鍍或濺鍍技術來沉積鏡面鍍金屬30,其最終厚度應小於饋通連接24和傳導墊片18之鍍金屬的下部之厚度。在所述範例中,鏡面鍍金屬30具有約一百奈米(nm)的厚度。如第5圖所述,該鏡面鍍金屬被沉積在懸突部100的頂部以及基底14之凹腔側的露出區域上。然而,如上所述,且如第9圖所更清楚描繪地,饋通連接24和傳導墊片18的懸突部100係作為屏蔽,並防止該鏡面鍍金屬被沉積得太靠近饋通連接24和墊片18的邊緣。Next, as shown in Fig. 5, a mirror-plated metal (e.g., aluminum) 30 is deposited substantially on all exposed areas on the cavity side of the substrate 14. The mirror metallization 30 can be deposited using evaporation or sputtering techniques, the final thickness of which should be less than the thickness of the feedthrough connection 24 and the metallized lower portion of the conductive spacer 18. In the illustrated example, the mirror metallization 30 has a thickness of about one hundred nanometers (nm). As described in FIG. 5, the mirror metallization is deposited on the top of the overhang 100 and the exposed area on the cavity side of the substrate 14. However, as described above, and as more clearly depicted in FIG. 9, the feedthrough connection 24 and the overhang 100 of the conductive shim 18 serve as a shield and prevent the specular metallization from being deposited too close to the feedthrough connection 24. And the edge of the spacer 18.

如先前敘述所闡明地,沉積鏡面鍍金屬30的處理是與沉積饋通連接24和傳導墊片18之鍍金屬的處理分離。其可導致在防止鏡面鍍金屬30接觸饋通連接24和墊片18的側邊緣時,該鏡面鍍金屬覆蓋大部份的基底14之內表面。As explained in the previous description, the process of depositing the mirror metallization 30 is separate from the process of depositing the metallization of the feedthrough connection 24 and the conductive shim 18. This may result in the mirror metallization covering the inner surface of most of the substrate 14 while preventing the mirror metallization 30 from contacting the side edges of the feedthrough connection 24 and the spacer 18.

接著,如第6圖所示,自鍍金層24、18移除鋁鏡面鍍金屬30(亦即,自饋通連接24和傳導墊片18的頂部移除鋁)。舉例來說,其可藉由選擇性地將光阻層48(例如,藉由電沉積技術)沉積在鋁鏡面鍍金屬層30的區域上而達成,而不沉積在那些鋁鏡面鍍金屬層將被移除的區域上(亦即,不沉積在饋通連接24和傳導墊片18上)。然後,可藉由將該矽晶圓置於鋁蝕刻劑中而移除在金(或金 -錫)饋通連接24和傳導墊片18頂部的露出之鋁鍍金屬。Next, as shown in FIG. 6, the aluminum mirror metallization 30 is removed from the gold plated layers 24, 18 (i.e., the aluminum is removed from the top of the feedthrough connection 24 and the conductive spacer 18). For example, it can be achieved by selectively depositing a photoresist layer 48 (eg, by electrodeposition techniques) on the area of the aluminum mirror metallization layer 30, without depositing on those aluminum mirror metallization layers. The removed area (i.e., not deposited on the feedthrough connection 24 and the conductive shim 18). The gold (or gold) can then be removed by placing the germanium wafer in an aluminum etchant. - Tin) Feedthrough connection 24 and exposed aluminum plated metal on top of conductive spacer 18.

在自饋通連接24和傳導墊片18移除鋁後,剝除電沉積之光阻層48,如第7圖所示。結果是用於LED晶片之半導體基板的內表面之顯要部份被反射性(鏡面)鍍金屬所覆蓋而提高光學輸出。由於懸突部100,該鏡面鍍金屬係與導體線(亦即,饋通連接24和傳導墊片18)電氣地中斷。After the aluminum is removed from the feedthrough connection 24 and the conductive spacer 18, the electrodeposited photoresist layer 48 is stripped as shown in FIG. As a result, a significant portion of the inner surface of the semiconductor substrate for the LED wafer is covered by a reflective (mirror) metallization to enhance the optical output. Due to the overhang 100, the mirror metallization is electrically interrupted from the conductor lines (i.e., the feedthrough connection 24 and the conductive spacer 18).

雖然先前敘述著重於形成單一封裝之基底14,但該處理可被執行如晶圓級之批次處理。While the previous description has focused on forming a single package of substrate 14, this process can be performed as batch processing at the wafer level.

在沉積了多種鍍金屬層之後,將LED晶片16置於傳導墊片18上,並裝附銲線28。可以聚矽氧凝膠填充凹腔22,並將可包含塑膠或玻璃透鏡的透明之上蓋12裝附於基底14。After depositing a plurality of metallization layers, the LED wafer 16 is placed on the conductive pads 18 and the bond wires 28 are attached. The cavity 22 can be filled with a polyoxygel and a transparent top cover 12, which can include a plastic or glass lens, can be attached to the substrate 14.

其他實施形態包含於申請專利範圍中。Other embodiments are included in the scope of the patent application.

10‧‧‧封裝10‧‧‧Package

12‧‧‧上蓋12‧‧‧Upper cover

14‧‧‧基底14‧‧‧Base

16‧‧‧LED16‧‧‧LED

18‧‧‧傳導墊片18‧‧‧ Conductive gasket

20‧‧‧銲接密封環20‧‧‧welding seal ring

22‧‧‧凹腔22‧‧‧ cavity

24‧‧‧饋通鍍金屬(饋通連接)24‧‧•Feed through metallization (feedthrough connection)

26‧‧‧銲料隆點26‧‧‧ solder bumps

28‧‧‧銲線28‧‧‧welding line

30‧‧‧鍍金屬30‧‧‧metal plating

32‧‧‧底部32‧‧‧ bottom

34‧‧‧側壁34‧‧‧ side wall

40‧‧‧薄膜堆疊40‧‧‧ Film stacking

42‧‧‧鍍模42‧‧‧ plating

44‧‧‧銲接合44‧‧‧welding

46‧‧‧銲壩46‧‧‧ soldering dam

48‧‧‧光阻層48‧‧‧ photoresist layer

100‧‧‧懸突部100‧‧‧Overhanging

第1圖是容納發光裝置之封裝的範例之剖面圖。Fig. 1 is a cross-sectional view showing an example of a package accommodating a light-emitting device.

第2圖是該封裝之基底的上視圖。Figure 2 is a top view of the substrate of the package.

第3~7圖描繪用以沉積多種鍍金屬層的製造步驟。Figures 3 through 7 depict fabrication steps for depositing various metallized layers.

第8圖是在饋通和傳導墊片鍍金屬區域頂部之懸突部的放大圖。Figure 8 is an enlarged view of the overhang at the top of the metallization of the feedthrough and conduction pads.

第9圖描繪該等懸突部如何屏蔽與該饋通和傳導墊片鍍金屬區域的側邊緣鄰接之區域不被後續沉積之鍍金屬所覆蓋。Figure 9 depicts how the overhangs shield the area adjacent the side edges of the feedthrough and conductive pad metallization regions from being overlaid by subsequent metallization.

10‧‧‧封裝10‧‧‧Package

12‧‧‧上蓋12‧‧‧Upper cover

14‧‧‧基底14‧‧‧Base

16‧‧‧LED16‧‧‧LED

18‧‧‧傳導墊片18‧‧‧ Conductive gasket

20‧‧‧銲接密封環20‧‧‧welding seal ring

22‧‧‧凹腔22‧‧‧ cavity

24‧‧‧饋通鍍金屬(饋通連接)24‧‧•Feed through metallization (feedthrough connection)

26‧‧‧銲料隆點26‧‧‧ solder bumps

28‧‧‧銲線28‧‧‧welding line

30‧‧‧鍍金屬30‧‧‧metal plating

32‧‧‧底部32‧‧‧ bottom

34‧‧‧側壁34‧‧‧ side wall

Claims (28)

一種在基板上具有發光裝置的封裝之製造方法,該方法包括:沉積一第一鍍金屬,以形成將在其上安裝該發光裝置的傳導墊片,並形成延伸通過支撐該傳導墊片之半導體材料的一或多個饋通(feed-through)互連;以及隨後沉積一第二鍍金屬,以形成用於將該發光裝置所發出之光線反射通過該封裝之上蓋的反射面,其中,該第一鍍金屬係被沉積以便在該傳導墊片和該一或多個饋通互連之每一者的頂部周圍形成各個懸突部,並藉由該等懸突部使沉積該第二鍍金屬與沉積該第一鍍金屬分離(de-coupled)。 A method of fabricating a package having a light-emitting device on a substrate, the method comprising: depositing a first metallization to form a conductive pad on which the light-emitting device is to be mounted, and forming a semiconductor extending through the conductive pad One or more feed-through interconnections of material; and subsequently depositing a second metallization to form a reflective surface for reflecting light emitted by the illumination device through the cover of the package, wherein a first metallization is deposited to form respective overhangs around the top of each of the conductive shim and the one or more feedthrough interconnects, and the second plating is deposited by the overhangs The metal is de-coupled to deposit the first metallization. 如申請專利範圍第1項之製造方法,更包含:沉積該第二鍍金屬在該半導體材料的表面上,包括在該傳導墊片和該一或多個饋通互連的上表面上,其中,該等懸突部係作為屏蔽,以實質防止該第二鍍金屬被沉積在該等懸突部正下方的區域上;以及隨後自該傳導墊片和該一或多個饋通互連的上表面移除該第二鍍金屬。 The manufacturing method of claim 1, further comprising: depositing the second metal plating on a surface of the semiconductor material, including on the conductive pad and the upper surface of the one or more feedthrough interconnections, wherein And the overhangs serve as a shield to substantially prevent the second metallization from being deposited on a region directly under the overhang; and subsequently interconnected from the conductive shim and the one or more feedthroughs The upper surface removes the second metallization. 如申請專利範圍第2項之製造方法,更包含實質沉積該第二鍍金屬在該半導體材料的整個側面上。 The manufacturing method of claim 2, further comprising depositing the second metal plating substantially on the entire side of the semiconductor material. 如申請專利範圍第2項之製造方法,其中,該等懸突部是透過該第一鍍金屬的等向性生長所形成。 The manufacturing method of claim 2, wherein the overhanging portions are formed by isotropic growth of the first metal plating. 如申請專利範圍第4項之製造方法,更包含:在該半導體材料的表面上提供一遮罩層,該遮罩層界定將 被沉積該傳導墊片和該一或多個饋通互連之該第一鍍金屬的開口;以及隨後沉積該第一鍍金屬,其中,該第一鍍金屬的該等向性生長發生在該第一鍍金屬的厚度超過該遮罩層的厚度時。 The manufacturing method of claim 4, further comprising: providing a mask layer on the surface of the semiconductor material, the mask layer defining Depositing the conductive pad and the first metallized opening of the one or more feedthrough interconnects; and subsequently depositing the first metallization, wherein the isotropic growth of the first metallization occurs When the thickness of the first metal plating exceeds the thickness of the mask layer. 如申請專利範圍第5項之製造方法,其中,該遮罩層包括光阻。 The manufacturing method of claim 5, wherein the mask layer comprises a photoresist. 如申請專利範圍第6項之製造方法,其中,該光阻是藉由旋塗所沉積。 The manufacturing method of claim 6, wherein the photoresist is deposited by spin coating. 如申請專利範圍第6項之製造方法,其中,該光阻是藉由浸塗所沉積。 The manufacturing method of claim 6, wherein the photoresist is deposited by dip coating. 如申請專利範圍第6項之製造方法,其中,該光阻是藉由噴塗所沉積。 The manufacturing method of claim 6, wherein the photoresist is deposited by spraying. 如申請專利範圍第6項之製造方法,其中,該光阻是藉由電沉積所沉積。 The manufacturing method of claim 6, wherein the photoresist is deposited by electrodeposition. 如申請專利範圍第2項之製造方法,其中,該第一鍍金屬是藉由電鍍處理所沉積,而該第二鍍金屬是藉由蒸鍍技術所沉積。 The manufacturing method of claim 2, wherein the first metal plating is deposited by a plating process, and the second metal plating is deposited by an evaporation technique. 如申請專利範圍第2項之製造方法,其中,該第一鍍金屬是藉由電鍍處理所沉積,而該第二鍍金屬是藉由濺鍍技術所沉積。 The manufacturing method of claim 2, wherein the first metal plating is deposited by a plating process, and the second metal plating is deposited by a sputtering technique. 如申請專利範圍第2項之製造方法,其中,該等懸突部以數微米的等級延伸超過該傳導墊片和該一或多個饋通互連的各個下部。 The manufacturing method of claim 2, wherein the overhangs extend beyond the conductive pads and the respective lower portions of the one or more feedthrough interconnects on a scale of a few microns. 如申請專利範圍第2項之製造方法,其中,自該傳導墊片和該一或多個饋通互連的上表面移除該第二鍍金屬包含:選擇性地將光阻層提供在除了將被移除之該第二鍍金屬的區域以外之該第二鍍金屬的區域上;以及 蝕刻該第二鍍金屬的露出區域。 The manufacturing method of claim 2, wherein the removing the second metal plating from the conductive pad and the upper surface of the one or more feedthrough interconnects comprises: selectively providing the photoresist layer in addition to The second metallized area outside the second metallized area to be removed; The exposed area of the second metallization is etched. 如申請專利範圍第2項之製造方法,其中,該第一鍍金屬包括金,而該第二鍍金屬包括鋁。 The manufacturing method of claim 2, wherein the first metal plating comprises gold and the second metal plating comprises aluminum. 如申請專利範圍第2項之製造方法,其中,該第一鍍金屬包括金和錫,而該第二鍍金屬包括鋁。 The manufacturing method of claim 2, wherein the first metal plating comprises gold and tin, and the second metal plating comprises aluminum. 如申請專利範圍第2項之製造方法,更包含在該半導體材料中蝕刻一凹腔,其中,該傳導墊片和該一或多個饋通互連被形成在由該凹腔所界定的區域中,且其中,該第二鍍金屬被沉積在該凹腔的底表面上並沿著該凹腔的側壁。 The manufacturing method of claim 2, further comprising etching a cavity in the semiconductor material, wherein the conductive pad and the one or more feedthrough interconnections are formed in an area defined by the cavity And wherein the second metallization is deposited on a bottom surface of the cavity and along a sidewall of the cavity. 如申請專利範圍第2項之製造方法,係被執行如半導體晶圓級之批次處理。 The manufacturing method as in the second application of the patent scope is performed as a batch processing at the semiconductor wafer level. 一種用以容納發光裝置之封裝的製造方法,該方法包括:在一半導體晶圓的第一側形成一凹腔,並形成自該凹腔的底部延伸至該晶圓的第二側之一或多個通孔;沉積一第一鍍金屬,以形成用於安裝該發光裝置的傳導墊片,並形成延伸通過該一或多個通孔的饋通互連,其中,沉積該第一鍍金屬以便在該傳導墊片和該等饋通互連之每一者的頂部周圍形成各個懸突部;沉積一第二鍍金屬在該半導體晶圓的該第一側上,包含在該凹腔的底部和側表面上,以及在該傳導墊片和該等饋通互連的上表面上,其中,該等懸突部係作為屏蔽,以實質防止該第二鍍金屬被沉積在該等懸突部正下方的區域上;自該傳導墊片和該等饋通互連的上表面選擇性地移除該第二鍍金屬,使得該剩下的第二鍍金屬形成與該傳導墊片和該等 饋通互連電氣地中斷的反射面;以及將該發光裝置安裝在該傳導墊片上。 A method of fabricating a package for housing a light emitting device, the method comprising: forming a cavity on a first side of a semiconductor wafer and forming one from a bottom of the cavity to a second side of the wafer or a plurality of vias; depositing a first metallization to form a conductive pad for mounting the light emitting device and forming a feedthrough interconnect extending through the one or more vias, wherein depositing the first metallization Forming respective overhangs around the top of each of the conductive pad and the feedthrough interconnects; depositing a second metallization on the first side of the semiconductor wafer, included in the cavity On the bottom and side surfaces, and on the upper surface of the conductive pad and the feedthrough interconnects, wherein the overhangs serve as a shield to substantially prevent the second metallization from being deposited on the overhangs Selecting the second metallization from the conductive gasket and the upper surface of the feedthrough interconnect such that the remaining second metallization is formed with the conductive spacer and the portion Wait The feedthrough interconnects an electrically interrupted reflective surface; and mounting the illumination device on the conductive spacer. 如申請專利範圍第19項之製造方法,其中,該等懸突部是透過該第一鍍金屬的等向性生長所形成。 The manufacturing method of claim 19, wherein the overhanging portions are formed by isotropic growth of the first metal plating. 如申請專利範圍第20項之製造方法,更包含:在該半導體材料的該第一側上提供遮罩層,該遮罩層界定將被沉積該傳導墊片和該等饋通互連之該第一鍍金屬的開口;以及隨後沉積該第一鍍金屬,其中,該第一鍍金屬的該等向性生長發生在該第一鍍金屬的厚度超過該遮罩層的厚度時。 The manufacturing method of claim 20, further comprising: providing a mask layer on the first side of the semiconductor material, the mask layer defining the conductive pad to be deposited and the feedthrough interconnect a first metallized opening; and subsequently depositing the first metallization, wherein the isotropic growth of the first metallization occurs when the thickness of the first metallization exceeds the thickness of the mask layer. 如申請專利範圍第19項之製造方法,其中,該第一鍍金屬是藉由電鍍處理所沉積,而該第二鍍金屬是藉由蒸鍍技術所沉積。 The manufacturing method of claim 19, wherein the first metal plating is deposited by a plating process, and the second metal plating is deposited by an evaporation technique. 如申請專利範圍第19項之製造方法,其中,該第一鍍金屬是藉由電鍍處理所沉積,而該第二鍍金屬是藉由濺鍍技術所沉積。 The manufacturing method of claim 19, wherein the first metal plating is deposited by a plating process, and the second metal plating is deposited by a sputtering technique. 如申請專利範圍第19項之製造方法,其中,該等懸突部以數微米的等級延伸超過該傳導墊片和該等饋通互連的各個下部。 The manufacturing method of claim 19, wherein the overhangs extend beyond the conductive pads and the respective lower portions of the feedthrough interconnects on a scale of a few microns. 如申請專利範圍第19項之製造方法,其中,該第一鍍金屬包括金,而該第二鍍金屬包括鋁。 The manufacturing method of claim 19, wherein the first metal plating comprises gold and the second metal plating comprises aluminum. 如申請專利範圍第19項之製造方法,其中,該第一鍍金屬包括金和錫,而該第二鍍金屬包括鋁。 The manufacturing method of claim 19, wherein the first metal plating comprises gold and tin, and the second metal plating comprises aluminum. 如申請專利範圍第19項之製造方法,更包含將一發光二極體安裝在該傳導墊片上。 The manufacturing method of claim 19, further comprising mounting a light emitting diode on the conductive spacer. 如申請專利範圍第27項之製造方法,更包含將該發光二極體電耦接至該等饋通互連,並將一透明上蓋裝附在該發光二極體 上。The manufacturing method of claim 27, further comprising electrically coupling the light emitting diode to the feedthrough interconnects, and attaching a transparent upper cover to the light emitting diode on.
TW097105101A 2007-02-15 2008-02-14 Method for manufacturing light-emitting device on substrate TWI523255B (en)

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