TWI523185B - Semiconductor component - Google Patents

Description

Semiconductor component

This invention relates to an electronic component, and more particularly to a semiconductor component.

A semiconductor element (for example, a wafer) is an electronic component that integrates a plurality of conductor layers. In general, a semiconductor component has an alignment mark on the top conductor layer for alignment of the semiconductor component with other devices, such as a carrier in a packaging process. However, in the conventional semiconductor element, no component can be disposed under the alignment mark to avoid the influence of the identification of the alignment mark. A portion of the semiconductor component must be reserved for the alignment mark configuration, so that the configuration of the circuit layer is limited. As a result, the area corresponding to the alignment mark in the semiconductor element cannot be used, and the cost of the semiconductor element is not easily further lowered.

The present invention provides a semiconductor device in which the recognition of the alignment mark can be improved.

A semiconductor device of the present invention includes a substrate and at least one pair of bit marks disposed on the substrate and having at least one hollow pattern.

In an embodiment of the invention, the substrate has a line area and a peripheral area outside the line area, and the alignment mark is disposed in the reserved area of the line area.

In an embodiment of the invention, the reserved area is at a corner of the line area.

In an embodiment of the invention, the alignment mark is formed by a first metal layer disposed on the substrate.

In an embodiment of the invention, the semiconductor device further includes: at least one trace formed by at least one second metal layer. This trace is marked by the alignment. The second metal layer is disposed between the first metal layer and the substrate.

In an embodiment of the invention, the traces described above are filled into the reserved area.

In an embodiment of the invention, the traces described above are line segments.

In an embodiment of the invention, the hollow pattern includes a plurality of sub-hollow patterns, and the sub-empty patterns are substantially the same.

In an embodiment of the invention, each of the sub-hollow patterns has at least one gap, and the size of the gap is smaller than the size of each sub-hollow pattern.

In an embodiment of the invention, each of the sub-hollow patterns described above includes a center pattern and four peripheral patterns surrounding the center pattern. The center pattern has a through hole and is separated from the peripheral pattern. The peripheral patterns are separated from each other.

In an embodiment of the invention, each of the sub-hollow patterns includes a T-shaped pattern, a 1-shaped pattern, and an L-shaped pattern. The T-shaped pattern, the 1-shaped pattern, and the L-shaped pattern are separated from each other.

In an embodiment of the invention, each of the sub-hollow patterns described above includes a box and a block disposed in the box.

In an embodiment of the invention, the at least one hollow pattern is a plurality of hollow patterns, and the hollow patterns are separated from each other.

In an embodiment of the invention, the at least one hollow pattern has a shape of a cross or a square rectangle.

Based on the above, in the semiconductor device of one embodiment of the present invention, the hollow pattern can make the optical characteristics of the alignment mark change drastically, and thus the recognition degree of the alignment mark by the hollow pattern can be improved.

The above described features and advantages of the invention will be apparent from the following description.

1‧‧‧ center pattern

2‧‧‧ peripheral patterns

3‧‧‧T-shaped pattern

4‧‧‧1 pattern

5‧‧‧L-shaped pattern

6‧‧‧ square

7‧‧‧ box

100‧‧‧Semiconductor components

100a‧‧‧Line area

100b‧‧‧ reserved area

100c‧‧‧ surrounding area

110‧‧‧Substrate

120, 120A, 120B‧‧‧ alignment mark

122, 122A, 122B‧‧‧ hollow pattern

128‧‧‧ Solid Department

130‧‧‧ Traces

A-A’‧‧‧ cut line

D‧‧‧ Direction

GI‧‧‧Insulation

K, k‧‧‧ size

L, L', L1, L2‧‧‧ detect light

M1‧‧‧ first metal layer

M2‧‧‧ second metal layer

P, P1~P3‧‧‧ child hollow pattern

PS‧‧‧Void

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention.

2 is an enlarged view of a region of the semiconductor device of FIG. 1.

Fig. 3 is a schematic cross-sectional view showing a semiconductor element corresponding to a line A-A' of Fig. 2.

4 is an enlarged schematic view of the sub-hollow pattern of FIG. 2.

Figure 5 shows an alignment mark of another embodiment of the present invention.

FIG. 6 is an enlarged schematic view of the sub-empty pattern of FIG. 5.

Fig. 7 shows an alignment mark of still another embodiment of the present invention.

Figure 8 is an enlarged schematic view of the sub-hollow pattern of Figure 7.

1 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention. 2 is an enlarged view of a region of the semiconductor device of FIG. 1. Fig. 3 is a schematic cross-sectional view showing a semiconductor element corresponding to a line A-A' of Fig. 2. Referring to FIGS. 1 , 2 and 3 , the semiconductor device 100 includes a substrate 110 and at least one pair of bit marks 120 disposed on the substrate 110 . In the present embodiment, the substrate 110 has a wiring area 100a and a peripheral area 100c outside the wiring area 100a. The registration mark 120 can be disposed in the reserved area 100b in the line area 100a. In the present embodiment, the substrate 110 is, for example, a wafer. However, the invention is not limited thereto.

In detail, as shown in FIG. 1, the reserved area 100b may be at the corner of the line area 100a. The semiconductor device 100 of the present embodiment may include two alignment marks 120. The two alignment marks 120 may be respectively disposed in the reserved area 100b and the other reserved area 100b located at the upper left and upper right corners of the line area 100a. However, the invention is not limited thereto. The number and location of the registration mark 120 and the reserved area 100b may depend on actual needs.

Referring to FIG. 2 and FIG. 3, it is noted that the alignment mark 120 has at least one hollow pattern 122. The hollow pattern 122 causes the optical characteristic change of the alignment mark 120 to be more intense than the conventional solid alignment mark, so the degree of recognition of the alignment mark 120 by the hollow pattern 122 can be improved. In the present embodiment, as shown in FIG. 2, the alignment mark 120 may include two hollow patterns 122 separated from each other. One of the hollow patterns 122 may have a cross shape, and the other hollow pattern 122 may have a square shape. This square can be placed next to the intersection of the cross. However, the invention is not limited thereto. In other embodiments, the shape and relative position of the hollow pattern 122 may depend on actual needs.

In this embodiment, the hollow pattern 122 may include a plurality of sub-hollow patterns P, These sub-hollow patterns P can be substantially the same. For example, as shown in FIG. 2, the hollow pattern 122 may include a plurality of sub-hollow patterns P1. 4 is an enlarged schematic view of the sub-hollow pattern of FIG. 2. Referring to FIG. 4, each sub-hollow pattern P(P1) has at least one void PS, and the dimension k of the void PS is smaller than the dimension K of each sub-hollow pattern P(P1).

Further, in the present embodiment, each sub-hollow pattern P includes a center pattern 1 and four peripheral patterns 2 surrounding the center pattern 1. The center pattern 1 has a through hole (such as the void PS1), and the center pattern 1 is separated from the four peripheral patterns 2. The four peripheral patterns 2 are separated from each other. The shape of the void PS1 may be square. The shape of the void PS (PS2) may be W-shaped. However, the invention is not limited thereto. The sub-hollow pattern P is also of other types. Other types of sub-hollow patterns will be described below by taking FIGS. 5 to 8 as an example.

Figure 5 shows an alignment mark of another embodiment of the present invention. FIG. 6 is an enlarged schematic view of the sub-empty pattern of FIG. 5. The components in FIGS. 5 and 6 are similar to the corresponding components in FIGS. 2 and 4, and therefore the component numbers in FIGS. 5 and 6 are the same as or corresponding to the corresponding components in FIGS. 2 and 4. Referring to FIGS. 5 and 6, the alignment mark 120A has at least one hollow pattern 122A. The hollow pattern 122A includes a plurality of sub-hollow patterns P (P2), and each sub-hollow pattern P (P2) is substantially the same. Referring to FIG. 6, each sub-hollow pattern P(P2) includes a T-shaped pattern 3, a 1-shaped pattern 4, and an L-shaped pattern 5, and the T-shaped pattern 3, the 1-shaped pattern 4, and the L-shaped pattern 5 are separated from each other.

Fig. 7 shows an alignment mark of still another embodiment of the present invention. Figure 8 is an enlarged schematic view of the sub-hollow pattern of Figure 7. The components in FIGS. 7 and 8 are similar to the corresponding components in FIGS. 2 and 4, and therefore the component numbers in FIGS. 7 and 8 are the same as or corresponding to the corresponding components in FIGS. 2 and 4. Please refer to FIG. 7 and FIG. 8 , and the alignment mark 120B has There is at least one hollow pattern 122B. The hollow pattern 122B includes a plurality of sub-hollow patterns P (P3), and each sub-hollow pattern P (P3) is substantially the same. Referring to FIG. 8, each sub-hollow pattern P (P3) includes a box 7 and a block 6 arranged in the box 7. Block 7 is separated from block 6.

Referring again to FIGS. 2 and 3, the alignment mark 120 is formed by the first metal layer M1 disposed on the substrate 110. The semiconductor device 100 further includes at least one trace 130 formed by at least one second metal layer M2. The second metal layer M2 is disposed between the first metal layer M1 and the substrate 110. The insulating layer GI is disposed between the first metal layer M1 and the second metal layer M2. In the present embodiment, trace 130 may pass through alignment mark 120. In other words, the trace 130 may overlap the alignment mark 120 in a direction d perpendicular to the substrate 110. Trace 130 can be filled into reserved area 100b, while trace 130 can be a line segment. However, the invention is not limited thereto. In other embodiments, traces 130 can be other patterns.

It should be noted that when the trace 130 passes the alignment mark 120, the degree of recognition of the alignment mark 120 by the hollow pattern 122 may still be high. In detail, as shown in FIG. 3, all of the detected light L transmitted to the solid portion 128 of the alignment mark 120 can be reflected. However, only a portion L1 of the detected light L' of the gap PS transmitted to the hollow pattern 122 is reflected by the trace 130. That is, the amount of reflected light from the solid portion 128 may be different from the amount of reflected light from the void PS. As such, the contrast of the alignment mark 120 including the hollow pattern 122 having the void PS is sufficient, so that the alignment mark 120 can still be recognized by the alignment machine. That is, the reserved area 100b of the semiconductor element 100 corresponding to the alignment mark 120 can be used for the trace 130, and the cost of the semiconductor element 100 can be further reduced.

In summary, in an embodiment of the invention, the visibility of the alignment mark can be improved by the hollow pattern. In addition, because the identification of the alignment mark can still be high by the hollow pattern, the trace can be marked by the alignment. As a result, the area of the semiconductor element corresponding to the alignment mark can be used for the trace, and the cost of the semiconductor element can be further reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100b‧‧‧ reserved area

110‧‧‧Substrate

120‧‧‧ alignment mark

122‧‧‧ hollow pattern

130‧‧‧ Traces

A-A’‧‧‧ cut line

P, P1‧‧ ‧ child hollow pattern

PS‧‧‧Void

Claims (12)

A semiconductor device comprising: a substrate; at least one pair of bit marks disposed on the substrate and having at least one hollow pattern formed by a first metal layer disposed on the substrate; and at least one trace The trace is formed by the at least one second metal layer, and the trace is disposed between the first metal layer and the substrate. The semiconductor device of claim 1, wherein the substrate has a line region and a peripheral region outside the line region, and the alignment mark is disposed in a reserved region of the line region. The semiconductor component of claim 2, wherein the reserved region is at a corner of the wiring region. The semiconductor device of claim 2, wherein the trace is filled in the reserved region. The semiconductor device of claim 4, wherein the trace is a line segment. The semiconductor device of claim 1, wherein the hollow pattern comprises a plurality of sub-hollow patterns, and the sub-empty patterns are substantially identical. The semiconductor device of claim 6, wherein each of the sub-hollow patterns has at least one void, and the size of the void is smaller than a size of each of the sub-hollow patterns. The semiconductor component according to claim 6, wherein each of the sub-components The hollow pattern includes a center pattern and a four-peripheral pattern surrounding the center pattern, the center pattern having a uniform aperture and being separated from the peripheral patterns, and the peripheral patterns are separated from each other. The semiconductor device of claim 6, wherein each of the sub-hollow patterns comprises a T-shaped pattern, a 1-shaped pattern, and an L-shaped pattern, and the T-shaped pattern, the 1-shaped pattern, and the L The pattern is separated from each other. The semiconductor component of claim 6, wherein each of the sub-hollow patterns comprises a block and a block disposed in the block. The semiconductor device according to claim 6, wherein the at least one hollow pattern is a plurality of hollow patterns, and the hollow patterns are separated from each other. The semiconductor device according to claim 11, wherein the at least one hollow pattern has a shape of a cross or a rectangle.