TWI522985B - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- 239000003990 capacitor Substances 0.000 claims description 161
- 238000005086 pumping Methods 0.000 claims description 32
- 238000010586 diagram Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Description
本發明有關於一種電荷泵浦電路,且特別是有關於一種用於顯示器的電荷泵浦電路。 This invention relates to a charge pumping circuit and, more particularly, to a charge pumping circuit for a display.
請參照第1圖,第1圖係為根據習知之一電荷泵浦電路的電路示意圖。如第1圖所示,電荷泵浦電路9為習知的顯示器領域中所慣用的電荷泵浦電路,此電荷泵浦電路9主要是用於產生閘極截止電壓(low-level gate voltage,亦稱VGL)與閘極導通電壓(high-level gate voltage,亦稱VGH)。其中,閘極導通電壓VGH主要是透過電壓位準產生模組90中的電容C2~C6與二極體D1~D4所產生,而閘極截止電壓VGL主要是透過電壓位準產生模組90中的電容C7~C9與二極體D5~D6所產生。此外,輸入電壓Vin可透過電感L1、二極體D1與電容C1而產生電源類比電壓AVDD,電源類比電壓AVDD為一種提供給源極驅動器(source driver)的電壓。脈波寬度調變積體電路90則包括有電壓調整器920與電晶體M1。 Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a charge pump circuit according to a conventional one. As shown in FIG. 1, the charge pump circuit 9 is a charge pump circuit conventionally used in the field of display. The charge pump circuit 9 is mainly used to generate a low-level gate voltage. VGL) and high-level gate voltage (also known as VGH). The gate turn-on voltage VGH is mainly generated by the capacitors C2~C6 and the diodes D1~D4 in the voltage level generating module 90, and the gate turn-off voltage VGL is mainly generated by the voltage level generating module 90. Capacitors C7~C9 and diodes D5~D6 are produced. In addition, the input voltage Vin can generate a power analog voltage AVDD through the inductor L1, the diode D1 and the capacitor C1, and the power analog voltage AVDD is a voltage supplied to the source driver. The pulse width modulation integrated circuit 90 includes a voltage regulator 920 and a transistor M1.
請參照第2圖,第2圖係為根據習知之另一電荷泵浦電路的電路示意圖。為了節省電荷泵浦電路中的二極體的使用數量,目前的顯示器製造廠商會利用複數個切換開關SW1~SW6 來取代二極體,並將這些切換開關SW1~SW6包在脈波寬度調變積體電路90’中,如第2圖所示。此電荷泵浦電路9’所產生的閘極截止電壓VGL主要是透過第一電壓調整器902’與第一電壓位準產生模組900’中的切換開關SW1、切換開關SW2、電容C1與電容C2所產生。另一方面,此電荷泵浦電路9’所產生的閘極導通電壓VGH主要是透過第二電壓調整器906’與第二電壓位準產生模組904’中的切換開關SW3、切換開關SW4、切換開關SW5、切換開關SW6、電容C3、電容C4、電容C5與電容C6所產生。 Please refer to FIG. 2, which is a circuit diagram of another charge pumping circuit according to a conventional one. In order to save the number of diodes used in the charge pump circuit, current display manufacturers will utilize a plurality of switchers SW1~SW6. The diodes are replaced, and these switches SW1 to SW6 are packaged in the pulse width modulation integrated circuit 90' as shown in Fig. 2. The gate-off voltage VGL generated by the charge pump circuit 9' is mainly transmitted through the first voltage regulator 902' and the switch SW1 in the first voltage level generating module 900', the switch SW2, the capacitor C1 and the capacitor. Produced by C2. On the other hand, the gate-on voltage VGH generated by the charge pump circuit 9' is mainly transmitted through the second voltage regulator 906' and the switch SW3 and the switch SW4 in the second voltage level generating module 904'. The switch SW5, the switch SW6, the capacitor C3, the capacitor C4, the capacitor C5, and the capacitor C6 are generated.
由第2圖可以觀察到,第一電壓位準產生模組900’需透過一級的電荷泵浦來產生電壓位準為-AVDD的閘極截止電壓VGL,而第二電壓位準產生模組904’需透過兩級的電荷泵浦來產生電壓位準為+3AVDD的閘極導通電壓VGH,而使得整個電荷泵浦電路9’需要三級的電荷泵浦,造成製造成本的提高。 It can be observed from FIG. 2 that the first voltage level generating module 900' needs to generate a gate turn-off voltage VGL with a voltage level of -AVDD through one stage of charge pumping, and the second voltage level generating module 904. 'The two-stage charge pumping is required to generate the gate-on voltage VGH with a voltage level of +3 AVDD, so that the entire charge pumping circuit 9' requires three stages of charge pumping, resulting in an increase in manufacturing cost.
有鑒於以上的問題,本揭露提出一種電荷泵浦電路,此電荷泵浦電路透過一種新的充放電路徑來減少電荷泵浦電路中的電荷泵浦的級數。 In view of the above problems, the present disclosure proposes a charge pumping circuit that reduces the number of charge pumping stages in a charge pumping circuit through a new charge and discharge path.
根據本揭露一實施例中的一種電荷泵浦電路,此電荷泵浦電路包括第一電壓位準產生模組與第二電壓位準產生模組。第一電壓位準產生模組具有第一輸出端,且此第一電壓位準產生模組包括第一電容、第二電容以及第一開關組。第二電容的一端耦接第一輸出端。第一開關組用以選擇性地切換導通第一電 流路徑與第二電流路徑。於第一電流路徑導通時,第一電容儲存有第一預設電壓。於第二電流路徑導通時,第一電容串聯耦該第二電容的一端,且此第二電容耦接第一輸出端的一端的端電壓被拉至第二預設電壓。第二電壓位準產生模組具有第二輸出端,且此第二電壓位準產生模組包括第三電容、第四電容以及第二開關組。第四電容的一端耦接第二輸出端。第二開關組用以選擇性地切換導通第三電流路徑與第四電流路徑。於第三電流路徑導通時,第三電容儲存有第三預設電壓,此第三預設電壓為第一預設電壓與第四預設電壓的電壓差值。於第四電流路徑導通時,第三電容串聯耦接第四電容的一端,且此第四電容耦接第三電容的一端的端電壓被拉至第一預設電壓與第三預設電壓的電壓總和。 According to an embodiment of the present disclosure, a charge pumping circuit includes a first voltage level generating module and a second voltage level generating module. The first voltage level generating module has a first output end, and the first voltage level generating module includes a first capacitor, a second capacitor, and a first switch group. One end of the second capacitor is coupled to the first output end. The first switch group is configured to selectively switch to turn on the first power The flow path and the second current path. The first capacitor stores a first predetermined voltage when the first current path is turned on. When the second current path is turned on, the first capacitor is coupled in series with one end of the second capacitor, and the terminal voltage of the second capacitor coupled to the one end of the first output terminal is pulled to a second preset voltage. The second voltage level generating module has a second output end, and the second voltage level generating module includes a third capacitor, a fourth capacitor, and a second switch group. One end of the fourth capacitor is coupled to the second output end. The second switch group is configured to selectively switch between the third current path and the fourth current path. When the third current path is turned on, the third capacitor stores a third preset voltage, where the third preset voltage is a voltage difference between the first preset voltage and the fourth preset voltage. When the fourth current path is turned on, the third capacitor is coupled in series with one end of the fourth capacitor, and the terminal voltage of the fourth capacitor coupled to the end of the third capacitor is pulled to the first preset voltage and the third preset voltage. The sum of the voltages.
於其中一實施例中,第二預設電壓為反向的第一預設電壓,第四預設電壓為第二預設電壓。當第二電流路徑導通時,第一輸出端所輸出的電壓位準為反向的第一預設電壓。當第四電流路徑導通時,第二輸出端所輸出的電壓位準為三倍的第一預設電壓。 In one embodiment, the second preset voltage is a reverse first preset voltage, and the fourth preset voltage is a second preset voltage. When the second current path is turned on, the voltage level output by the first output terminal is a reverse first predetermined voltage. When the fourth current path is turned on, the voltage level output by the second output terminal is three times the first preset voltage.
根據本揭露一實施例中的一種電荷泵浦電路,此電荷泵浦電路包括第一電壓位準產生模組與第二電壓位準產生模組。第一電壓位準產生模組具有第一輸出端,且此第一電壓位準產生模組包括第一電容、第二電容以及第一開關組。第二電容的一端耦接第一輸出端。第一開關組用以選擇性地切換導通第一電流路徑與第二電流路徑。於第一電流路徑導通時,第一電容儲存 有第一預設電壓。於第二電流路徑導通時,第一電容串聯耦該第二電容的一端,且此第二電容耦接第一電容的一端的端電壓被拉至第二預設電壓。第二電壓位準產生模組具有第二輸出端,且此第二電壓位準產生模組包括第三電容、第一二極體、第二二極體、第四電容以及第二開關組。第一二極體的陽極耦接第一預設電壓,第一二極體的陰極耦接第三電容的第一端。第二二極體的陽極耦接於第三電容的第一端與第一二極體的陰極之間,第二二極體的陰極耦接第二輸出端。第四電容耦接於第二二極體的陰極與第二輸出端之間。第二開關組用以選擇性地切換導通第三電流路徑與第四電流路徑。於第三電流路徑導通時,第四電容耦接第二輸出端的一端的端電壓被拉至第一預設電壓。於第四電流路徑導通時,第三電容的第二端耦接第三預設電壓,以使第二輸出端輸出的電壓位準為兩倍的第一預設電壓與第三預設電壓的電壓差值。 According to an embodiment of the present disclosure, a charge pumping circuit includes a first voltage level generating module and a second voltage level generating module. The first voltage level generating module has a first output end, and the first voltage level generating module includes a first capacitor, a second capacitor, and a first switch group. One end of the second capacitor is coupled to the first output end. The first switch group is configured to selectively switch between the first current path and the second current path. The first capacitor is stored when the first current path is turned on There is a first preset voltage. When the second current path is turned on, the first capacitor is coupled in series with one end of the second capacitor, and the terminal voltage of the second capacitor coupled to one end of the first capacitor is pulled to a second preset voltage. The second voltage level generating module has a second output end, and the second voltage level generating module includes a third capacitor, a first diode, a second diode, a fourth capacitor, and a second switch group. The anode of the first diode is coupled to the first predetermined voltage, and the cathode of the first diode is coupled to the first end of the third capacitor. The anode of the second diode is coupled between the first end of the third capacitor and the cathode of the first diode, and the cathode of the second diode is coupled to the second output. The fourth capacitor is coupled between the cathode of the second diode and the second output end. The second switch group is configured to selectively switch between the third current path and the fourth current path. When the third current path is turned on, the terminal voltage of the fourth capacitor coupled to the one end of the second output terminal is pulled to the first preset voltage. When the fourth current path is turned on, the second end of the third capacitor is coupled to the third preset voltage, so that the voltage level output by the second output terminal is twice the first preset voltage and the third preset voltage. Voltage difference.
於其中一實施例中,第二預設電壓為反向的第一預設電壓,第三預設電壓為第二預設電壓。當第二電流路徑導通時,第一輸出端所輸出的電壓位準為反向的第一預設電壓。當第四電流路徑導通時,第三電容的跨壓為第一預設電壓與第三預設電壓的電壓差值。 In one embodiment, the second preset voltage is a reverse first preset voltage, and the third preset voltage is a second preset voltage. When the second current path is turned on, the voltage level output by the first output terminal is a reverse first predetermined voltage. When the fourth current path is turned on, the voltage across the third capacitor is a voltage difference between the first predetermined voltage and the third predetermined voltage.
綜合以上所述,本揭露提供一種電荷泵浦電路,此電荷泵浦電路透過第一電壓位準產生模組中的第一開關組與第二電壓位準產生模組中的第二開關組來選擇性地導通不同的電流路 徑,並藉由複數個電容於不同電流路徑時的充放電特性,來使得第一電壓位準產生模組中的第一輸出端與第二電壓位準產生模組中的第二輸出端可以分別輸出兩個不同電壓位準的電壓。此外,第二電壓位準產生模組更可以依據第一電壓位準產生模組的第一輸出端所輸出的電壓來產生對應的輸出電壓。 In summary, the present disclosure provides a charge pumping circuit that transmits a first switch group in a first voltage level generating module and a second switch group in a second voltage level generating module. Selectively conduct different current paths The first output end of the first voltage level generating module and the second output end of the second voltage level generating module can be made by the charge and discharge characteristics of the plurality of capacitors in different current paths. Two different voltage levels are output separately. In addition, the second voltage level generating module can further generate a corresponding output voltage according to the voltage output by the first output end of the module according to the first voltage level.
以上之關於本揭露內容之說明及以下之實施方式之說明係用以示範與解釋本發明之精神與原理,並且提供本發明之專利申請範圍更進一步之解釋。 The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.
1、1’、9、9’‧‧‧電荷泵浦電路 1, 1', 9, 9' ‧ ‧ charge pump circuit
10、900’‧‧‧第一電壓位準產生模組 10, 900'‧‧‧First voltage level generation module
100‧‧‧第一開關組 100‧‧‧First switch group
12、902’‧‧‧第一電壓調整器 12, 902'‧‧‧First Voltage Regulator
14、14’、904’‧‧‧第二電壓位準產生模組 14, 14', 904'‧‧‧ second voltage level generation module
140、140’‧‧‧第二開關組 140, 140’‧‧‧second switch group
16、906’‧‧‧第二電壓調整器 16, 906’‧‧‧Second voltage regulator
92、90’‧‧‧脈波寬度調變積體電路 92, 90'‧‧‧ pulse width modulation integrated circuit
920‧‧‧電壓調整器 920‧‧‧Voltage regulator
V1、VX、VX’‧‧‧預設電壓 V1, V X , V X '‧‧‧ preset voltage
Vin‧‧‧輸入電壓 Vin‧‧‧Input voltage
AVDD‧‧‧電源類比電壓 AVDD‧‧‧ power analog voltage
VGH‧‧‧閘極導通電壓 VGH‧‧‧ gate conduction voltage
VGL‧‧‧閘極截止電壓 VGL‧‧‧ gate cutoff voltage
C1~C9‧‧‧電容 C1~C9‧‧‧ capacitor
D1~D6‧‧‧二極體 D1~D6‧‧‧ diode
SW1~SW6、SW3’‧‧‧切換開關 SW1~SW6, SW3'‧‧‧ switch
M1‧‧‧電晶體 M1‧‧‧O crystal
L1‧‧‧電感 L1‧‧‧Inductance
a、b‧‧‧切換節點 a, b‧‧‧ switching node
output_1‧‧‧第一輸出端 Output_1‧‧‧first output
output_2‧‧‧第二輸出端 Output_2‧‧‧second output
I1~I4‧‧‧電流路徑 I1~I4‧‧‧ current path
t0~t3、t0’~t3’‧‧‧時間點 T0~t3, t0’~t3’‧‧‧
第1圖係為根據習知之一電荷泵浦電路的電路示意圖。 Figure 1 is a circuit diagram of a charge pump circuit according to one of the conventional ones.
第2圖係為根據習知之另一電荷泵浦電路的電路示意圖。 Figure 2 is a circuit diagram of another charge pumping circuit in accordance with the prior art.
第3圖係為根據本揭露一實施例之電荷泵浦電路的電路示意圖。 3 is a circuit diagram of a charge pumping circuit in accordance with an embodiment of the present disclosure.
第4A圖係為根據第3圖之電荷泵浦電路於導通第一電流路徑時的電路操作模式示意圖。 Fig. 4A is a schematic diagram showing the operation mode of the circuit when the charge pump circuit according to Fig. 3 is turned on the first current path.
第4B圖係為根據第3圖之電荷泵浦電路於導通第二電流路徑時的電路操作模式示意圖。 4B is a schematic diagram of a circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the second current path.
第4C圖係為根據第3圖之電荷泵浦電路於導通第三電流路徑時的電路操作模式示意圖。 Fig. 4C is a schematic diagram showing the circuit operation mode when the charge pump circuit according to Fig. 3 is turned on the third current path.
第4D圖係為根據第3圖之電荷泵浦電路於導通第四電流路徑時的電路操作模式示意圖。 4D is a schematic diagram of a circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the fourth current path.
第5A圖係為根據第3圖之第一電壓位準產生模組的時序圖。 Figure 5A is a timing diagram of the module generated according to the first voltage level of Figure 3.
第5B圖係為根據第3圖之第二電壓位準產生模組的時序圖。 Figure 5B is a timing diagram of the module generated according to the second voltage level of Figure 3.
第6圖係為根據本揭露另一實施例之電荷泵浦電路的電路示意圖。 Figure 6 is a circuit diagram of a charge pumping circuit in accordance with another embodiment of the present disclosure.
以下在實施方式中詳細敘述本發明之詳細特徵以及優點,其內容足以使任何熟習相關技藝者了解本發明之技術內容並據以實施,且根據本說明書所揭露之內容、申請專利範圍及圖式,任何熟習相關技藝者可輕易地理解本發明相關之目的及優點。以下之實施例係進一步詳細說明本發明之觀點,但非以任何觀點限制本發明之範疇。 The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.
請參照第3圖,第3圖係為根據本揭露一實施例之電荷泵浦電路的電路示意圖。如第3圖所示,本發明實施例之電荷泵浦電路1主要包括第一電壓位準產生模組10、第一電壓調整器12、第二電壓位準產生模組14以及第二電壓調整器16。其中,第一電壓位準產生模組10更包括有第一電容C1、第二電容C2以及第一開關組100,第二電壓位準產生模組14更包括有第三電容C3、第四電容C4以及第二開關組140。以下分別就第一電壓位準產生模組10與第二電壓位準產生模組14中的各電子元件的 耦接關係與作動方式作詳細的說明。 Please refer to FIG. 3, which is a circuit diagram of a charge pumping circuit according to an embodiment of the present disclosure. As shown in FIG. 3, the charge pumping circuit 1 of the embodiment of the present invention mainly includes a first voltage level generating module 10, a first voltage regulator 12, a second voltage level generating module 14, and a second voltage adjustment. 16. The first voltage level generating module 10 further includes a first capacitor C1, a second capacitor C2, and a first switch group 100. The second voltage level generating module 14 further includes a third capacitor C3 and a fourth capacitor. C4 and second switch group 140. The following is the respective electronic components in the first voltage level generating module 10 and the second voltage level generating module 14 respectively. The coupling relationship and the actuation mode are described in detail.
第一開關組100用以選擇性地導通第一電流路徑與第二電流路徑,且此第一開關組100包括有第一切換開關SW1與第二切換開關SW2,且第一切換開關SW1與第二切換開關SW2皆具有一個切換節點a(第一切換節點與第三切換節點)、一個切換節點b(第二切換節點與第四切換節點)以及一個共同節點(未標示符號之節點)(第一共同節點與第二共同節點)。第一電容C1的第一端與第二端分別耦接第一切換開關SW1的共同節點與第二切換開關SW2的共同節點。第二電容C2的第一端與第二端分別耦接第一電壓位準產生模組10的第一輸出端output_1與接地電位。第一切換開關SW1的切換節點a耦接預設電壓V1(第一預設電壓),第一切換開關SW1的切換節點b與第二切換開關SW2的切換節點a皆耦接至接地電位,第二切換開關SW2的切換節點b耦接於第二電容C2與第一輸出端output_1之間。 The first switch group 100 is configured to selectively turn on the first current path and the second current path, and the first switch group 100 includes a first switch SW1 and a second switch SW2, and the first switch SW1 and the first switch The two switch SW2s each have a switching node a (a first switching node and a third switching node), a switching node b (a second switching node and a fourth switching node), and a common node (a node not labeled) (No. A common node and a second common node). The first end and the second end of the first capacitor C1 are respectively coupled to a common node of the first switch SW1 and a common node of the second switch SW2. The first end and the second end of the second capacitor C2 are respectively coupled to the first output end_1 of the first voltage level generating module 10 and the ground potential. The switching node a of the first switching switch SW1 is coupled to the preset voltage V1 (the first preset voltage), and the switching node b of the first switching switch SW1 and the switching node a of the second switching switch SW2 are all coupled to the ground potential. The switching node b of the two switching switch SW2 is coupled between the second capacitor C2 and the first output terminal output_1.
第一電壓調整器12耦接第一切換開關SW1與第二切換開關SW2。此第一電壓調整器12用以同時控制第一切換開關SW1與第二切換開關SW2的切換,以使第一電壓位準產生模組10中的第一電流路徑導通或是使第一電壓位準產生模組10中的第二電流路徑導通。換句話說,第一電壓調整器12用以使第一電壓位準產生模組10可以在第一時間導通第一電流路徑,或是使第一電壓位準產生模組10可以在第二時間導通第二電流路徑。於實務上,第一切換開關SW1與第二切換開關SW2可以為一種金 氧半場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)或是雙極性電晶體(bipolar junction transistor,BJT),但不以上述為限。 The first voltage regulator 12 is coupled to the first switch SW1 and the second switch SW2. The first voltage regulator 12 is configured to simultaneously control switching of the first switching switch SW1 and the second switching switch SW2 to turn on or enable the first current path in the first voltage level generating module 10 The second current path in the quasi-production module 10 is turned on. In other words, the first voltage regulator 12 is configured to enable the first voltage level generating module 10 to turn on the first current path at a first time, or to enable the first voltage level generating module 10 to be in a second time. Turning on the second current path. In practice, the first switch SW1 and the second switch SW2 may be a gold type Oxygen half field effect transistor (MOSFET) or bipolar junction transistor (BJT), but not limited to the above.
第二開關組140用以選擇性地導通第三電流路徑與第四電流路徑,且此第二開關組140包括有第三切換開關SW3與第四切換開關SW4,且第三切換開關SW3與第四切換開關SW4皆具有一個切換節點a(第五切換節點與第七切換節點)、一個切換節點b(第六切換節點與第八切換節點)以及一個共同節點(未標示符號之節點)(第三共同節點與第四共同節點)。第三電容C3的第一端與第二端分別耦接第三切換開關SW3的共同節點與第四切換開關SW4的共同節點。第四電容C4的第一端與第二端分別耦接第二電壓位準產生模組14的第二輸出端output_2與接地電位。第三切換開關SW3的切換節點a耦接預設電壓V1,第三切換開關SW3的切換節點b耦接於第四電容C4與第二輸出端output_2之間。第四切換開關SW4的切換節點a耦接預設電壓VX(第四預設電壓),第四切換開關SW4的切換節點b耦接預設電壓V1。 The second switch group 140 is configured to selectively turn on the third current path and the fourth current path, and the second switch group 140 includes a third switch SW3 and a fourth switch SW4, and the third switch SW3 and The four switch SW4s each have a switching node a (a fifth switching node and a seventh switching node), a switching node b (a sixth switching node and an eighth switching node), and a common node (a node not labeled) (No. Three common nodes and a fourth common node). The first end and the second end of the third capacitor C3 are respectively coupled to a common node of the third switch SW3 and a common node of the fourth switch SW4. The first end and the second end of the fourth capacitor C4 are respectively coupled to the second output terminal output_2 of the second voltage level generating module 14 and the ground potential. The switching node a of the third switching switch SW3 is coupled to the preset voltage V1, and the switching node b of the third switching switch SW3 is coupled between the fourth capacitor C4 and the second output terminal output_2. The switching node a of the fourth switching switch SW4 is coupled to the preset voltage V X (fourth preset voltage), and the switching node b of the fourth switching switch SW4 is coupled to the preset voltage V1.
值得注意的是,本發明實施例的預設電壓VX的電壓位準為小於預設電壓V1的電壓位準的任意電壓位準,換句話說,預設電壓VX的電壓位準可以為任意一個小於預設電壓V1的正電壓位準、接地電位或是任意一個負電壓位準,本發明在此不加以限制。 It should be noted that the voltage level of the preset voltage V X in the embodiment of the present invention is any voltage level lower than the voltage level of the preset voltage V1. In other words, the voltage level of the preset voltage V X may be Any one of the positive voltage level, the ground potential or any one of the negative voltage levels less than the preset voltage V1 is not limited herein.
第二電壓調整器16耦接第三切換開關SW3與第四切換開關SW4。此第二電壓調整器16用以同時控制第三切換開關SW3與第四切換開關SW4的切換,以使第二電壓位準產生模組14中的第三電流路徑導通或是使第二電壓位準產生模組14中的第四電流路徑導通。換句話說,第二電壓調整器16用以使第二電壓位準產生模組14可以在第三時間導通第三電流路徑,或是使第二電壓位準產生模組14可以在第四時間導通第四電流路徑。於實務上,第三切換開關SW3與第四切換開關SW4可以為一種金氧半場效電晶體或是雙極性電晶體,但不以上述為限。於其中一個實施例中,第三時間會接續在第二時間之後。 The second voltage regulator 16 is coupled to the third switch SW3 and the fourth switch SW4. The second voltage regulator 16 is configured to simultaneously control switching of the third switching switch SW3 and the fourth switching switch SW4 to turn on or enable the third current path in the second voltage level generating module 14 The fourth current path in the quasi-production module 14 is turned on. In other words, the second voltage regulator 16 is configured to enable the second voltage level generating module 14 to turn on the third current path at a third time, or to enable the second voltage level generating module 14 to be at the fourth time. The fourth current path is turned on. In practice, the third switch SW3 and the fourth switch SW4 may be a metal oxide half field effect transistor or a bipolar transistor, but not limited to the above. In one of the embodiments, the third time will continue after the second time.
為了更清楚地說明第一電壓位準產生模組10於導通第一電流路徑與第二電流路徑的詳細運作情況,以及第二電壓調整器16於導通第三電流路徑與第四電流路徑的詳細運作情況。請參照第4A圖、第4B圖、第4C圖以及第4D圖,第4A圖係為根據第3圖之電荷泵浦電路於導通第一電流路徑時的電路操作模式示意圖;第4B圖係為根據第3圖之電荷泵浦電路於導通第二電流路徑時的電路操作模式示意圖;第4C圖係為根據第3圖之電荷泵浦電路於導通第三電流路徑時的電路操作模式示意圖;第4D圖係為根據第3圖之電荷泵浦電路於導通第四電流路徑時的電路操作模式示意圖。 In order to more clearly explain the detailed operation of the first voltage level generating module 10 to turn on the first current path and the second current path, and the details of the second voltage regulator 16 to turn on the third current path and the fourth current path. Operational situation. Please refer to FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D. FIG. 4A is a schematic diagram of the circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the first current path; FIG. 4B is a diagram FIG. 4C is a schematic diagram of a circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the second current path; FIG. 4C is a schematic diagram of a circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the third current path; The 4D diagram is a schematic diagram of the circuit operation mode when the charge pump circuit according to FIG. 3 is turned on the fourth current path.
如第4A圖所示,當第一電壓位準產生模組10欲導通第一電流路徑I1時,第一切換開關SW1的共同節點會受到第 一電壓調整器12的控制而耦接第一切換開關SW1的切換節點a,第二切換開關SW2的共同節點亦會受到第一電壓調整器12的控制而耦接第二切換開關SW2的切換節點a,據以使得第一電容C1的第一端與第二端會分別耦接預設電壓V1與接地電位。此時,由於第一電容C1耦接於預設電壓V1與接地電位之間的關係,預設電壓V1會開始對第一電容C1進行充電,而形成第一電流路徑I1,並使第一電容C1的跨壓VC1被充電到預設電壓V1的電壓位準。換句話說,於第一電流路徑I1導通時,第一電容C1會儲存有預設電壓V1。 As shown in FIG. 4A, when the first voltage level generating module 10 is to turn on the first current path I1, the common node of the first switching switch SW1 is controlled by the first voltage regulator 12 to be coupled to the first switching. The switching node a of the switch SW1 and the common node of the second switching switch SW2 are also controlled by the first voltage regulator 12 and coupled to the switching node a of the second switching switch SW2, so that the first end of the first capacitor C1 is made The preset voltage V1 and the ground potential are respectively coupled to the second end. At this time, since the first capacitor C1 is coupled to the relationship between the preset voltage V1 and the ground potential, the preset voltage V1 starts to charge the first capacitor C1 to form the first current path I1 and the first capacitor. The voltage across C C1 of C1 is charged to the voltage level of the preset voltage V1. In other words, when the first current path I1 is turned on, the first capacitor C1 stores a preset voltage V1.
如第4B圖所示,當第一電壓位準產生模組10欲導通第二電流路徑I2時,第一切換開關SW1的共同節點會受到第一電壓調整器12的控制而耦接第一切換開關SW1的切換節點b,第二切換開關SW2的共同節點亦會受到第一電壓調整器12的控制而耦接第二切換開關SW2的切換節點b,據以使得第一電容C1的第一端與第二端會分別耦接接地電位與第二電容C2的第一端。此時,由於第一電容C1串聯耦接於接地電位與第二電容C2的第一端之間的關係,第一電容C1會開始對接地電位進行放電,而形成第二電流路徑I2,並使第二電容C2的跨壓VC2被放電到反向的預設電壓V1的電壓位準。換句話說,於第二電流路徑I2導通時,第二電容C2的第一端的端電壓被拉至反向的預設電壓V1,並使得第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓位準為反向的預設電壓V1。 As shown in FIG. 4B, when the first voltage level generating module 10 is to turn on the second current path I2, the common node of the first switching switch SW1 is controlled by the first voltage regulator 12 to be coupled to the first switching. The switching node b of the switch SW1 and the common node of the second switching switch SW2 are also controlled by the first voltage regulator 12 and coupled to the switching node b of the second switching switch SW2, so that the first end of the first capacitor C1 is made And the second end is coupled to the ground potential and the first end of the second capacitor C2. At this time, since the first capacitor C1 is coupled in series to the relationship between the ground potential and the first end of the second capacitor C2, the first capacitor C1 starts to discharge the ground potential, and forms the second current path I2, and The voltage across the second capacitor C2, V C2 , is discharged to the voltage level of the reverse predetermined voltage V1. In other words, when the second current path I2 is turned on, the terminal voltage of the first terminal of the second capacitor C2 is pulled to the reverse preset voltage V1, and the first output of the first voltage level generating module 10 is caused. The voltage level output by the terminal output_1 is the reverse preset voltage V1.
如第4C圖所示,當第二電壓位準產生模組14欲導通第三電流路徑I3時,第三切換開關SW3的共同節點會受到第二電壓調整器16的控制而耦接第三切換開關SW3的切換節點a,第四切換開關SW4的共同節點亦會受到第二電壓調整器16的控制而耦接第四切換開關SW4的切換節點a,據以使得第三電容C3的第一端與第二端會分別耦接預設電壓V1與預設電壓VX。此時,由於第三電容C3耦接於預設電壓V1與預設電壓VX之間的關係,第三電容C3會因為預設電壓V1與預設電壓VX的電位差而開始被充電,據以形成第三電流路徑I3,並使第三電容C3的跨壓VC3被充電到預設電壓V1與預設電壓VX的電壓差值(第三預設電壓)。換句話說,於第三電流路徑I3導通時,第三電容C3會依據預設電壓V1與預設電壓VX的電壓差值而被充電,並使第三電容C3儲存有預設電壓V1與預設電壓VX的電壓差值。 As shown in FIG. 4C, when the second voltage level generating module 14 is to turn on the third current path I3, the common node of the third switching switch SW3 is controlled by the second voltage regulator 16 to be coupled to the third switching. The switching node a of the switch SW3 and the common node of the fourth switching switch SW4 are also controlled by the second voltage regulator 16 to be coupled to the switching node a of the fourth switching switch SW4, so that the first end of the third capacitor C3 is The preset voltage V1 and the preset voltage V X are respectively coupled to the second end. At this time, since the third capacitor C3 is coupled to the relationship between the preset voltage V1 and the preset voltage V X , the third capacitor C3 starts to be charged due to the potential difference between the preset voltage V1 and the preset voltage V X . The third current path I3 is formed, and the voltage across the voltage V C3 of the third capacitor C3 is charged to a voltage difference (a third preset voltage) between the preset voltage V1 and the preset voltage V X . In other words, when the third current path I3 is turned on, the third capacitor C3 is charged according to the voltage difference between the preset voltage V1 and the preset voltage V X , and the third capacitor C3 is stored with the preset voltage V1 and The voltage difference of the preset voltage V X .
如第4D圖所示,當第二電壓位準產生模組14欲導通第四電流路徑I4時,第三切換開關SW3的共同節點會受到第二電壓調整器16的控制而耦接第三切換開關SW3的切換節點b,第四切換開關SW4的共同節點亦會受到第二電壓調整器16的控制而耦接第四切換開關SW4的切換節點b,據以使得第三電容C3的第一端與第二端會分別耦接第四電容C4的第一端與預設電壓V1。此時,由於第四電容C4串聯耦接於第四電容C4的第一端與預設電壓V1之間的關係,預設電壓V1與第三電容C3所儲存的跨壓VC3(即預設電壓V1與預設電壓VX的電壓差值)會開 始對第四電容C4的第二端所耦接的接地電位進行放電,而形成第四電流路徑I4,據以使得第四電容C4的跨壓VC4相當於預設電壓V1與第三電容C3所儲存的跨壓VC3的電壓總合。 As shown in FIG. 4D, when the second voltage level generating module 14 is to turn on the fourth current path I4, the common node of the third switching switch SW3 is controlled by the second voltage regulator 16 to be coupled to the third switching. The switching node b of the switch SW3 and the common node of the fourth switching switch SW4 are also controlled by the second voltage regulator 16 and coupled to the switching node b of the fourth switching switch SW4, so that the first end of the third capacitor C3 is The first end of the fourth capacitor C4 and the preset voltage V1 are respectively coupled to the second end. At this time, because the fourth capacitor C4 is coupled in series with the relationship between the first end of the fourth capacitor C4 and the preset voltage V1, the preset voltage V1 and the cross-voltage V C3 stored by the third capacitor C3 (ie, preset The voltage difference between the voltage V1 and the preset voltage V X starts to discharge the ground potential coupled to the second end of the fourth capacitor C4, and forms a fourth current path I4, so that the fourth capacitor C4 crosses The voltage V C4 is equivalent to the voltage sum of the preset voltage V1 and the voltage across the voltage V C3 stored by the third capacitor C3.
換句話說,於第四電流路徑I4導通時,第四電容C4會依據預設電壓V1與第三電容C3所儲存的跨壓VC3而被充電,使得第四電容C4的第一端的端電壓被拉至預設電壓V1與第三電容C3所儲存的跨壓VC3的電壓總合,並使得第二電壓位準產生模組14的第二輸出端output_2所輸出的電壓位準為預設電壓V1與第三電容C3所儲存的跨壓VC3的電壓總合。 In other words, at the time of the fourth current I4 conduction path, the fourth capacitor C4 will be charged according to a preset voltage V1 and the third capacitor C3 of the voltage V C3 across the reservoir, such that the first end of the end of the fourth capacitor C4 The voltage is pulled to the voltage of the preset voltage V1 and the voltage across the voltage V C3 stored by the third capacitor C3, and the voltage level outputted by the second output terminal_2 of the second voltage level generating module 14 is pre- The voltage V1 is summed with the voltage across the voltage V C3 stored by the third capacitor C3.
於實務上,電荷泵浦電路1可設置在顯示器中,以對顯示器提供複數個不同電壓位準的驅動電壓。舉例來說,若預設電壓V1為一種提供給源極驅動器(source driver)的電源類比電壓(例如AVDD)的話,則第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓位準可以為一種提供給閘極驅動器(gate driver)的閘極截止電壓(low-level gate voltage,亦稱VGL),第二電壓位準產生模組14的第二輸出端output_2所輸出的電壓位準可以為一種提供給閘極驅動器的閘極導通電壓(high-level gate voltage,亦稱VGH)。 In practice, the charge pump circuit 1 can be placed in the display to provide a plurality of different voltage levels of the drive voltage to the display. For example, if the preset voltage V1 is a power analog voltage (for example, AVDD) supplied to the source driver, the voltage level output by the first output terminal_1 of the first voltage level generating module 10 is used. The voltage level of the second output terminal output_2 of the second voltage level generating module 14 can be a gate-off gate voltage (VGL) provided to the gate driver. It can be a high-level gate voltage (VGH) that is supplied to the gate driver.
在實際的操作中,第一電壓位準產生模組10的第一輸出端output_1所輸出的閘極截止電壓可以再反饋至第二電壓位準產生模組14中的用於接收預設電壓VX的節點,使得預設電壓VX即為閘極截止電壓,據以使得第二電壓位準產生模組14可以 依據第一電壓位準產生模組10所產生的閘極截止電壓來產生閘極導通電壓。 In actual operation, the gate cutoff voltage outputted by the first output terminal output_1 of the first voltage level generating module 10 can be fed back to the second voltage level generating module 14 for receiving the preset voltage V. The node of X is such that the preset voltage V X is the gate cutoff voltage, so that the second voltage level generating module 14 can generate the gate cutoff voltage generated by the module 10 according to the first voltage level to generate the gate. Polar conduction voltage.
請一併參照第3圖、第4A圖、第4B圖與第5A圖,第5A圖係為根據第3圖之第一電壓位準產生模組的時序圖。如第5A圖所示,於時間點t0至時間點t1的時間區間時,第一切換開關SW1與第二切換開關SW2的共同節點皆未耦接各自的切換節點a,而是耦接各自的切換節點b。此時,由於第一電容C1的跨壓VC1為零電位的關係,故不會對接地電位進行放電,使得第二電容C2的跨壓VC2亦為零電位。 Please refer to FIG. 3, FIG. 4A, FIG. 4B and FIG. 5A together. FIG. 5A is a timing chart of the module according to the first voltage level of FIG. As shown in FIG. 5A, in the time interval from the time point t0 to the time point t1, the common nodes of the first switch SW1 and the second switch SW2 are not coupled to the respective switching nodes a, but are coupled to the respective Switch node b. At this time, since the voltage V C1 of the first capacitor C1 is at zero potential, the ground potential is not discharged, so that the voltage V C2 of the second capacitor C2 is also zero potential.
於時間點t1至時間點t2的時間區間時,第一切換開關SW1與第二切換開關SW2的共同節點耦接各自的切換節點a。此時,第一電流路徑I1會被導通(如第4A圖所示),並使第一電容C1的跨壓VC1被充電到預設電壓V1的電壓位準,而第二電容C2的跨壓VC2仍為零電位。 During the time interval from the time point t1 to the time point t2, the common node of the first changeover switch SW1 and the second changeover switch SW2 is coupled to the respective switching node a. At this time, the first current path I1 is turned on (as shown in FIG. 4A), and the voltage across the voltage C C1 of the first capacitor C1 is charged to the voltage level of the preset voltage V1, and the cross of the second capacitor C2 The voltage V C2 is still at zero potential.
於時間點t2至時間點t3的時間區間時,第一切換開關SW1與第二切換開關SW2的共同節點改為耦接各自的切換節點b。此時,第二電流路徑I2會被導通(如第4B圖所示),並使第二電容C2的跨壓VC2被放電到反向的預設電壓V1的電壓位準(即-V1)。藉此,第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓位準會為反向的預設電壓V1(即-V1)。 During the time interval from the time point t2 to the time point t3, the common node of the first changeover switch SW1 and the second changeover switch SW2 is coupled to the respective switch node b. At this time, the second current path I2 is turned on (as shown in FIG. 4B), and the voltage across the voltage V C2 of the second capacitor C2 is discharged to the voltage level of the reverse preset voltage V1 (ie, -V1). . Thereby, the voltage level output by the first output terminal output_1 of the first voltage level generating module 10 is a reverse preset voltage V1 (ie, -V1).
請一併參照第3圖、第4C圖、第4D圖與第5B圖,第5B圖係為根據第3圖之第二電壓位準產生模組的時序圖。需 先一提的是,第5B圖之實施例係以預設電壓VX被設定為第二電容C2的第一端被拉至的電壓(亦即第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓)的情況下的時序圖。如第5B圖所示,於時間點t0’至時間點t1’的時間區間時,第三切換開關SW3與第四切換開關SW4的共同節點皆未耦接各自的切換節點a,而是耦接各自的切換節點b。此時,第三電容C3的跨壓VC3與第四電容C4的跨壓VC4皆為零電位。 Please refer to FIG. 3, FIG. 4C, FIG. 4D and FIG. 5B together. FIG. 5B is a timing chart of the second voltage level generating module according to FIG. It should be noted that the embodiment of FIG. 5B is configured to set the voltage to which the first end of the second capacitor C2 is pulled by the preset voltage V X (that is, the first voltage level generating module 10). A timing chart in the case of a voltage output from the output terminal_1. As shown in FIG. 5B, in the time interval from the time point t0' to the time point t1', the common node of the third switch SW3 and the fourth switch SW4 are not coupled to the respective switching node a, but are coupled. The respective switching node b. At this time, the voltage across the third capacitor C3 and cross voltage V V C3 C4 of the fourth capacitor C4 are zero potential.
於時間點t1’至時間點t2’的時間區間時,第三切換開關SW3與第四切換開關SW4的共同節點耦接各自的切換節點a。此時,第三電流路徑I3會被導通(如第4C圖所示),並使第三電容C3的跨壓VC3被充電到預設電壓V1與預設電壓VX的電壓差值。其中,由於預設電壓VX被設定為第二電容C2的第一端被拉至的電壓(即-V1)的關係,使得第三電容C3的跨壓VC3會等於兩倍的預設電壓V1。 During the time interval from the time point t1' to the time point t2', the common node of the third changeover switch SW3 and the fourth changeover switch SW4 is coupled to the respective switching node a. At this time, the third current path I3 is turned on (as shown in FIG. 4C), and the voltage across the voltage V C3 of the third capacitor C3 is charged to a voltage difference between the preset voltage V1 and the preset voltage V X . Wherein, since the preset voltage V X is set to the second capacitor C2 is pulled to a voltage (i.e., -V1) of the relationship between the first end, such that the voltage across the third capacitor C3 will be equal to V C3 twice the preset voltage V1.
於時間點t2’至時間點t3’的時間區間時,第三切換開關SW3與第四切換開關SW4的共同節點耦接各自的切換節點b。此時,第四電流路徑I4會被導通(如第4D圖所示),使得第四電容C4的跨壓VC4相當於預設電壓V1與第三電容C3所儲存的跨壓VC3的電壓總合,亦即第四電容C4的跨壓VC4會等於三倍的預設電壓V1。藉此,第二電壓位準產生模組14的第二輸出端output_2所輸出的電壓位準會為三倍的預設電壓V1(即3V1)。 The common node of the third changeover switch SW3 and the fourth changeover switch SW4 is coupled to the respective switching node b during the time interval from the time point t2' to the time point t3'. In this case, the fourth current I4 is turned path (as shown on FIG. 4D), so that the voltage V across the fourth capacitor C4 C4 preset voltage corresponds to the voltage V1 and the third capacitor C3 stored in the C3 cross voltage V The sum, that is, the voltage across the fourth capacitor C4, V C4 , is equal to three times the preset voltage V1. Thereby, the voltage level outputted by the second output terminal output_2 of the second voltage level generating module 14 is three times the preset voltage V1 (ie, 3V1).
此外,若使用者欲使第二電壓位準產生模組14的第 二輸出端output_2輸出的電壓位準為較高的電壓位準時,第二電壓位準產生模組14中的第二開關組140由於切換開關數量較多且規格耐壓的關係,使得切換開關SW3與切換開關SW4可能會發生電弧效應(electric arc effect)而融化開關觸點。 In addition, if the user wants to make the second voltage level generating module 14 When the voltage level outputted by the output 2 of the output terminal is a higher voltage level, the second switch group 140 in the second voltage level generating module 14 has a large number of switching switches and a voltage withstand specification, so that the switch SW3 is switched. An electric arc effect may occur with the switch SW4 to melt the switch contacts.
請參照第6圖,第6圖係為根據本揭露另一實施例之電荷泵浦電路的電路示意圖。如第6圖所示,本發明實施例之電荷泵浦電路1’主要包括第一電壓位準產生模組10、第一電壓調整器12、第二電壓位準產生模組14’以及第二電壓調整器16。由於本實施例之電荷泵浦電路1’中的大部分功能模組相同於前一實施例之電荷泵浦電路1中的功能模組,故在此不再贅述相同之功能模組的耦接關係與作動方式。 Please refer to FIG. 6. FIG. 6 is a schematic circuit diagram of a charge pumping circuit according to another embodiment of the present disclosure. As shown in FIG. 6, the charge pumping circuit 1' of the embodiment of the present invention mainly includes a first voltage level generating module 10, a first voltage regulator 12, a second voltage level generating module 14', and a second Voltage regulator 16. Since most of the functional modules in the charge pumping circuit 1' of the present embodiment are identical to the functional modules in the charge pumping circuit 1 of the previous embodiment, the coupling of the same functional modules will not be repeated here. Relationship and action.
與前一實施例之電荷泵浦電路1不同的是,本實施例之電荷泵浦電路1’中的第二電壓位準產生模組14’包括有第三電容C3、第四電容C4、第一二極體D1、第二二極體D2以及第二開關組140’,其中第二開關組140’即為第三切換開關SW3’。換句話說,第二開關組140’具有一個切換節點a、一個切換節點b以及一個共同節點(未標示符號之節點)。藉此,本實施例之電荷泵浦電路1’中的第二電壓位準產生模組14’較前一實施例之電荷泵浦電路1中的第二電壓位準產生模組14降低了發生電弧效應的機率。 Different from the charge pump circuit 1 of the previous embodiment, the second voltage level generating module 14' in the charge pumping circuit 1' of the embodiment includes a third capacitor C3, a fourth capacitor C4, and a A diode D1, a second diode D2, and a second switch group 140', wherein the second switch group 140' is the third switch SW3'. In other words, the second switch group 140' has one switching node a, one switching node b, and one common node (nodes not labeled). Thereby, the second voltage level generating module 14' in the charge pumping circuit 1' of the present embodiment is lower than the second voltage level generating module 14 in the charge pumping circuit 1 of the previous embodiment. The probability of an arc effect.
第二開關組140’的切換節點a耦接預設電壓V1,第 二開關組140’的切換節點b耦接預設電壓VX’,第二開關組140’的共同節點耦接第三電容C3的第二端。第一二極體D1的陽極耦接於預設電壓V1與第二開關組140’的切換節點a之間,第一二極體D1的陰極耦接於第三電容C3的第一端與第二二極體D2的陽極之間。第二二極體D2的陽極耦接於第三電容C3的第一端與第一二極體D1的陰極之間,第二二極體D2的陰極耦接於第四電容C4與第二輸出端output_2之間。第四電容C4的第一端耦接於第二二極體D2的陰極與第二輸出端output_2之間,第四電容C4的第二端耦接接地電位。於本實施例中,預設電壓VX’的電壓位準可以為第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓位準或是接地電位,但不以此為限。 The switching node a of the second switch group 140' is coupled to the preset voltage V1, the switching node b of the second switch group 140' is coupled to the preset voltage V X ', and the common node of the second switch group 140' is coupled to the third capacitor. The second end of C3. The anode of the first diode D1 is coupled between the preset voltage V1 and the switching node a of the second switch group 140'. The cathode of the first diode D1 is coupled to the first end of the third capacitor C3. Between the anodes of the diode D2. The anode of the second diode D2 is coupled between the first end of the third capacitor C3 and the cathode of the first diode D1, and the cathode of the second diode D2 is coupled to the fourth capacitor C4 and the second output. Between end output_2. The first end of the fourth capacitor C4 is coupled between the cathode of the second diode D2 and the second output terminal_2, and the second end of the fourth capacitor C4 is coupled to the ground potential. In this embodiment, the voltage level of the preset voltage V X ' may be the voltage level or the ground potential output by the first output terminal output_1 of the first voltage level generating module 10, but not limited thereto. .
第二開關組140’用以選擇性地切換第三電流路徑與第四電流路徑。當第二電壓位準產生模組14’欲導通第三電流路徑時,第二開關組140’的共同節點會受到第二電壓調整器16的控制而耦接第二開關組140’的切換節點a,據以形成由預設電壓V1依序經過第一二極體D1、第二二極體D2與第四電容C4的第三電流路徑。此時,第四電容C4會因為預設電壓V1而被充電,並使第四電容C4的第一端的端電壓被拉至預設電壓V1。 The second switch group 140' is configured to selectively switch the third current path and the fourth current path. When the second voltage level generating module 14 ′ is to conduct the third current path, the common node of the second switch group 140 ′ is controlled by the second voltage regulator 16 and coupled to the switching node of the second switch group 140 ′. a, according to the third voltage path of the first diode D1, the second diode D2 and the fourth capacitor C4 sequentially formed by the preset voltage V1. At this time, the fourth capacitor C4 is charged due to the preset voltage V1, and the terminal voltage of the first terminal of the fourth capacitor C4 is pulled to the preset voltage V1.
當第二電壓位準產生模組14’欲導通第四電流路徑時,第二開關組140’的共同節點會受到第二電壓調整器16的控制而耦接第二開關組140’的切換節點b,據以使得第三電容C3的第二端會耦接預設電壓VX’。此時,第三電容C3的跨壓相當於 預設電壓V1與預設電壓VX’的電壓差值。藉此,當第二開關組140’的共同節點再次耦接至第二開關組140’的切換節點a時,第四電容C4的跨壓會相當於預設電壓V1與第三電容C3的跨壓之電壓總合,據以使得第二電壓位準產生模組14’的第二輸出端output_2所輸出的電壓位準會為兩倍的預設電壓V1與預設電壓VX’的電壓差值。 When the second voltage level generating module 14 ′ is to turn on the fourth current path, the common node of the second switch group 140 ′ is controlled by the second voltage regulator 16 and coupled to the switching node of the second switch group 140 ′. b, so that the second end of the third capacitor C3 is coupled to the preset voltage V X '. At this time, the voltage across the third capacitor C3 is equivalent to the voltage difference between the preset voltage V1 and the preset voltage V X '. Therefore, when the common node of the second switch group 140' is coupled to the switching node a of the second switch group 140', the voltage across the fourth capacitor C4 is equivalent to the span of the preset voltage V1 and the third capacitor C3. The voltage sum of the voltages is such that the voltage level outputted by the second output terminal output_2 of the second voltage level generating module 14' is twice the voltage difference between the preset voltage V1 and the preset voltage V X ' value.
舉例來說,若預設電壓VX’為接地電位的話,則第二電壓位準產生模組14’的第二輸出端output_2所輸出的電壓位準會為兩倍的預設電壓V1;若預設電壓VX’為第一電壓位準產生模組10的第一輸出端output_1所輸出的電壓位準的話,則第二電壓位準產生模組14’的第二輸出端output_2所輸出的電壓位準會為三倍的預設電壓V1。 For example, if the preset voltage V X ' is the ground potential, the voltage level outputted by the second output terminal output_2 of the second voltage level generating module 14' will be twice the preset voltage V1; The preset voltage V X 'is the voltage level outputted by the first output terminal output_1 of the first voltage level generating module 10, and the second voltage level generating module 14' outputs the second output terminal output_2 The voltage level will be three times the preset voltage V1.
綜合以上所述,本發明實施例提供一種電荷泵浦電路,此電荷泵浦電路透過第一電壓位準產生模組中的第一開關組與第二電壓位準產生模組中的第二開關組來選擇性地導通不同的電流路徑,並藉由複數個電容於不同電流路徑時的充放電特性,來使得第一電壓位準產生模組中的第一輸出端與第二電壓位準產生模組中的第二輸出端可以分別輸出兩個不同電壓位準的電壓。此外,第二電壓位準產生模組更可以依據第一電壓位準產生模組的第一輸出端所輸出的電壓來產生對應的輸出電壓。藉此,本發明實施例之電荷泵浦電路可適用在顯示器中,以對顯示器提供兩 個不同電壓位準的閘極截止電壓與閘極導通電壓,並且僅需在用以輸出閘極導通電壓的電壓位準產生模組中設置一組電荷泵浦,降低了製造成本,十分具有實用性。 In summary, the embodiment of the present invention provides a charge pumping circuit that transmits a first switch group in a first voltage level generating module and a second switch in a second voltage level generating module. The group selectively turns on different current paths and generates a first output terminal and a second voltage level in the first voltage level generating module by charging and discharging characteristics of a plurality of capacitors in different current paths The second output of the module can output two voltages of different voltage levels respectively. In addition, the second voltage level generating module can further generate a corresponding output voltage according to the voltage output by the first output end of the module according to the first voltage level. Thereby, the charge pumping circuit of the embodiment of the invention can be applied to the display to provide two for the display. a different gate voltage and gate turn-on voltage of different voltage levels, and only need to set a set of charge pump in the voltage level generating module for outputting the gate turn-on voltage, which reduces manufacturing cost and is very practical. Sex.
雖然本發明以上述之實施例揭露如上,然其並非用以限定本發明。在不脫離本發明之精神和範圍內,所為之更動與潤飾,均屬本發明之專利保護範圍。關於本發明所界定之保護範圍請參考所附之申請專利範圍。 Although the present invention has been disclosed above in the above embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.
1‧‧‧電荷泵浦電路 1‧‧‧Charge pump circuit
10‧‧‧第一電壓位準產生模組 10‧‧‧First voltage level generation module
100‧‧‧第一開關組 100‧‧‧First switch group
12‧‧‧第一電壓調整器 12‧‧‧First voltage regulator
14‧‧‧第二電壓位準產生模組 14‧‧‧Second voltage level generation module
140‧‧‧第二開關組 140‧‧‧Second switch group
16‧‧‧第二電壓調整器 16‧‧‧Second voltage regulator
V1、VX‧‧‧預設電壓 V1, V X ‧‧‧Preset voltage
C1~C4‧‧‧電容 C1~C4‧‧‧ capacitor
SW1~SW4‧‧‧切換開關 SW1~SW4‧‧‧Toggle switch
a、b‧‧‧切換節點 a, b‧‧‧ switching node
output_1‧‧‧第一輸出端 Output_1‧‧‧first output
output_2‧‧‧第二輸出端 Output_2‧‧‧second output
Claims (12)
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| Application Number | Priority Date | Filing Date | Title |
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| TW103106579A TWI522985B (en) | 2014-02-26 | 2014-02-26 | Charge pump circuit |
| CN201410222713.2A CN103956895B (en) | 2014-02-26 | 2014-05-22 | Charge pump circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| TW103106579A TWI522985B (en) | 2014-02-26 | 2014-02-26 | Charge pump circuit |
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| TW201533719A TW201533719A (en) | 2015-09-01 |
| TWI522985B true TWI522985B (en) | 2016-02-21 |
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| TWI691946B (en) * | 2019-06-14 | 2020-04-21 | 大陸商北京集創北方科技股份有限公司 | Charge pump circuit, drive circuit and display device |
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| TWI537932B (en) | 2015-04-01 | 2016-06-11 | 矽創電子股份有限公司 | Power Circuit, Gate Driving Circuit and Display Module |
| KR102509328B1 (en) * | 2016-08-29 | 2023-03-15 | 에스케이하이닉스 주식회사 | Apparatus for Voltage Switching and Semiconductor Memory Apparatus Having the Same |
| CN112087130B (en) * | 2019-06-14 | 2025-05-13 | 北京集创北方科技股份有限公司 | Voltage conversion device, chip and electronic device |
| CN113824317B (en) * | 2021-10-28 | 2022-11-11 | 福州京东方光电科技有限公司 | Charge pump, power supply driving circuit and display |
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| TWI298828B (en) * | 2005-06-29 | 2008-07-11 | Novatek Microelectronics Corp | Charge pump for generating arbitrary voltage level |
| TWM298828U (en) * | 2006-02-23 | 2006-10-01 | East Best Co Ltd | Multi-function adapter for portable hard disc |
| JP2008099481A (en) * | 2006-10-13 | 2008-04-24 | Nec Electronics Corp | Charge pump circuit |
| CN101212175A (en) * | 2006-12-30 | 2008-07-02 | 圆创科技股份有限公司 | Double-side modulation type charge pump circuit and method thereof |
| DE102007020999A1 (en) * | 2007-05-04 | 2008-11-13 | Texas Instruments Deutschland Gmbh | Charge pump for generating an input voltage for an operational amplifier |
| JP5697621B2 (en) * | 2012-02-29 | 2015-04-08 | 株式会社東芝 | DC-DC converter and audio output device |
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| TWI691946B (en) * | 2019-06-14 | 2020-04-21 | 大陸商北京集創北方科技股份有限公司 | Charge pump circuit, drive circuit and display device |
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| CN103956895B (en) | 2017-05-10 |
| CN103956895A (en) | 2014-07-30 |
| TW201533719A (en) | 2015-09-01 |
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