TWI522978B - Inspection and repairing method of display panel - Google Patents

Description

Method of detecting and repairing a display panel

The invention relates to a method for detecting and repairing a display panel, in particular to a method for detecting and repairing a display panel with a gate driver on array (GOA).

In recent years, the development of flat panel displays has become more and more rapid, and has gradually replaced the conventional cathode ray tube display. Today's flat display panels mainly include the following: an organic light emitting diode (OLED) display panel, a plasma display panel (PDP), and a liquid crystal display (LCD). Panels and the like, in which the liquid crystal display panel has the advantages of low power consumption, lightness and high resolution, has become a mainstream product of today's consumer display panels.

The liquid crystal display panel mainly includes a liquid crystal panel and a gate driving circuit and a source driving circuit for driving the pixels. The gate driving circuit and the source driving circuit may be disposed on the display substrate by using a tape carrier package (TCP) or a glass flip chip package (COG), or the gate driving circuit may be directly formed in the substrate of the liquid crystal panel, that is, The so-called Gate Driver-On-Array Circuit (GOA Circuit). When a defect occurs in the gate driving array circuit, since the gate driving array circuit is directly formed in the substrate of the liquid crystal panel, it is difficult to repair the gate driving array circuit.

One of the objects of the present invention is to provide a method for detecting and repairing a display panel, Detecting and/or repairing the gate drive array circuit of the display panel.

One embodiment of the present invention provides a method of detecting and repairing a display panel, including the following steps. A display panel is provided. The display panel includes a plurality of gate lines, a first gate drive array circuit, and a second gate drive array circuit. Each gate line has a first end and a second end. The first gate driving array circuit includes a plurality of first gate driving units electrically connected to the first ends of the gate lines, wherein the first gate driving unit includes a plurality of stages, and the first gate driving of the upper stage The unit is electrically connected to the first gate driving unit of the next stage. The second gate driving array circuit includes a plurality of second gate driving units electrically connected to the second ends of the gate lines, wherein the second gate driving unit includes a plurality of stages, and the second gate driving of the upper stage The unit is electrically connected to the second gate driving unit of the next stage. A first detecting step is performed to detect that one of the first gate driving array circuit and the second gate driving array circuit is disabled. Performing a second detecting step, when the first gate driving array circuit is disabled, inputting a start signal ST, a high frequency signal HC, and a low level to each second gate driving unit of the second gate driving array circuit The bit switching signal (low frequency signal) LC and a low level signal VSS input a low level switching signal LC and a low level signal VSS to each of the first gate driving units of the first gate driving array circuit, and cut off the first A gate drives the start signal ST of each of the first gate driving units of the array circuit and the high frequency signal HC to determine a bad first gate driving unit. Perform a repair step to repair the defective first gate drive unit.

The method for detecting and repairing the display panel of the present invention can effectively detect and repair the gate drive array circuit of the display panel having the bilateral drive architecture, thereby reducing the number of scraps of the display panel, thereby greatly reducing the manufacturing cost of the display panel.

10‧‧‧ display panel

12‧‧‧Substrate

12A‧‧‧ display area

12P‧‧‧ surrounding area

GL1~GLn‧‧‧ gate line

DL1~DLm‧‧‧ data line

P‧‧‧ pixels

First end of t1‧‧

T2‧‧‧ second end

GOA1‧‧‧First Gate Drive Array Circuit

GOA2‧‧‧Second Gate Drive Array Circuit

14‧‧‧Source drive circuit

UA1~UAn‧‧‧first gate drive unit

UB1~UBn‧‧‧Second gate drive unit

21‧‧‧Upper unit

22‧‧‧Drawdown unit

211‧‧‧ Pull-up control circuit

212‧‧‧ Pull-up drive circuit

221‧‧‧ Pull-down control circuit

222‧‧‧ Pull-down drive circuit

ST‧‧‧ start signal

HC‧‧‧High frequency signal

HC1‧‧‧ high frequency signal

HC2‧‧‧ high frequency signal

HC3‧‧‧ high frequency signal

HC4‧‧‧ high frequency signal

HC5‧‧‧ high frequency signal

HC6‧‧‧ high frequency signal

HCn‧‧‧ high frequency signal

LC‧‧‧low level switch signal

LC1‧‧‧first low level switch signal

LC2‧‧‧second low level switch signal

VSS‧‧‧low level signal

30‧‧‧Steps

32‧‧‧Steps

34‧‧‧Steps

36‧‧‧Steps

FIG. 1 is a schematic view showing a display panel according to an embodiment of the present invention.

FIG. 2 is a partial schematic view showing the display panel of FIG. 1.

FIG. 3 is a timing diagram showing driving signals of the gate driving array circuit of the display panel of the embodiment.

FIG. 4 is a flow chart showing a method for detecting and repairing a display panel according to an embodiment of the present invention.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, .

Please refer to Figure 1 and Figure 2. 1 is a schematic view showing a display panel according to an embodiment of the present invention, and FIG. 2 is a partial schematic view showing the display panel of FIG. 1. As shown in FIG. 1 , the display panel 10 of the present embodiment is exemplified by a liquid crystal display panel, but is not limited thereto. The display panel 10 includes a substrate 12 on which a display area (active area) 12A and a peripheral area 12P are defined. The display panel 10 includes a plurality of gate lines GL1 GL GLn, a plurality of data lines DL1 DL DLm, and a plurality of pixels (or sub-pixels) P are disposed in the display area 12A. The gate lines GL1 GL GLn are substantially intersected with the data lines DL1 DL DLm, and the pixels P are respectively disposed at intersections of the gate lines GL1 GL GLn and the data lines DL1 DL DLm. Any one of the gate lines GL1 GL GLn has a first end t1 and a second end t2. The display panel 10 further includes a first gate drive array circuit GOA1, a second gate drive array circuit GOA2, and a source drive circuit 14 disposed in the peripheral region 12P, wherein the first gate drive array circuit GOA1 is connected to the gate The first end t1 of the polar lines GL1 GL GLn is electrically connected, the second gate driving array circuit GOA2 is electrically connected to the second end t2 of the gate lines GL1 GL GLn, and the source driving circuit 14 is connected to the data line DL1 One of the ~DLm is electrically connected.

As shown in FIG. 2, the first gate driving array circuit GOA1 includes a plurality of first gate driving units UA1~UAn electrically connected to the first end t1 of the gate lines GL1 GL GLn, wherein the first gate The driving unit UA1~UAn includes a plurality of stages, wherein the first gate driving unit of the previous stage is electrically connected to the first gate driving unit of the next stage, for example, the first gate driving unit UA1 is The first gate driving unit UA2 is electrically connected, the first gate driving unit UA2 is electrically connected to the first gate driving unit UA3, and so on. The second gate driving array circuit GOA2 includes a plurality of second gate driving units UB1 UBUBn electrically connected to the second terminal t2 of the gate lines GL1 GL GLn respectively, and the second gate driving units UB1 UBUBn include a plurality of stages The second gate driving unit of the upper stage is electrically connected to the second gate driving unit of the next stage, for example, the second gate driving unit UB1 is electrically connected to the second gate driving unit UB2, and the second gate The pole drive unit UB2 is electrically connected to the second gate drive unit UB3, and so on.

In this embodiment, the first gate driving unit UA1~UAn and the second gate driving list The cells UB1 to UBn include a pull-up unit 21 and a pull-down unit 22, respectively. The pull-up unit 21 includes a pull-up control circuit 211 for receiving the start signal ST and the high-frequency signal HC, and a pull-up driving circuit 212, and the pull-up control circuit 211 and the corresponding gate lines GL1 GL GLn. Connected and receives the high frequency signal HC transmitted by the pull-up control circuit 211. The pull-down unit 22 includes a pull-down control circuit 221, and is connected to the pull-up unit 21 for receiving the low-level switching signal LC and the low-level signal VSS, and the pull-down driving circuit 222, and is connected to the pull-up unit 21, wherein the low-leveling The bit switching signal LC is a low frequency signal.

Please refer to Figure 3 and refer to Figure 1 and Figure 2 together. Figure 3 shows the real A timing diagram of a driving signal of a gate driving array circuit of a display panel of the embodiment. In this embodiment, the start signal ST, the first gate to the sixth gate of the first gate drive unit UA1 ~ UA6 HC1 ~ HC6 signal (or the first to sixth level of the second gate drive unit UB1 ~UB6 HC1~HC6 signal), low level switching signals LC1, LC2, and low level signal VSS timing as shown in Figure 3, but not limited to this. The driving principle of the gate driving array circuit of the display panel of this embodiment is as follows. The start signal ST starts the pull-up control circuit 211 of the first stage, and the pull-up control circuit 211 of the first stage outputs the high-frequency signal HC1 to open the pull-up driving circuit 212 of the first stage, and the pull-up driving circuit of the first stage 212 will pass the high frequency signal HC1 to the first gate line GL1, and also play the second level The start signal ST of the control circuit 211 is pulled. The pull-up control circuit 211 of the second stage outputs the high-level signal HC2 to open the pull-up driving circuit 212 of the second stage, and the pull-up driving circuit 212 of the second stage transmits the high-frequency signal HC2 to the second gate line. GL2, and the pull-up driving circuit 212 of the second stage, in addition to turning on the third-stage pull-up control circuit 211, also starts the pull-down driving circuit 222 of the first stage, and the pull-down driving circuit 222 of the first stage will be the first The stage pull-up control circuit 211 and the pull-up drive circuit 212 are turned off. Further, the pull-down control circuit 221 (stabilizing circuit) is always operating to turn off the pull-up control circuit 211 and the pull-up driving circuit 212 of the present stage, except that the pull-up control circuit 211 is turned from on to off. It can be known from the above driving principle that the gate driving array circuit is one level one-level transmission, one level one level, and one another, as long as any level one abnormality will cause all circuit abnormalities. In addition, in the embodiment, the low level switching signal LC is a low frequency signal, and the low level switching signal LC can include a first low level switching signal LC1 and a second low level switching signal LC2, two sets of low frequency signals. The control circuit is controlled in turn, so the life of the voltage regulator circuit can be extended.

The gate driving array circuit of the display panel 10 of this embodiment adopts a bilateral driving frame That is, the two ends of the gate lines GL1 GL GLn respectively receive the gate driving signals provided by the first gate driving array circuit GOA1 and the second gate driving array circuit GOA2, thereby reducing the gate driving The voltage drop caused by the RC loading effect of the signal, especially for large-size display panels, the bilateral drive architecture can effectively reduce the voltage drop caused by the resistor-capacitor loading effect. When the abnormality of one of the first gate driving array circuit GOA1 and the second gate driving array circuit GOA2 of the display panel 10 affects the display effect, the method for detecting and repairing the display panel of the present invention can correctly detect the display. The first gate driving array circuit GOA1 and the second gate driving array circuit GOA2 of the panel 10 are abnormal, and the first gate driving array circuit GOA1 or the second gate driving array circuit GOA2 which is abnormal may be further detected. The bad gate drive unit can further repair the bad gate drive unit.

Please refer to Figure 4 again and refer to Figures 1 to 3 together. Figure 4 shows this A flowchart of a method of detecting and repairing a display panel in an embodiment of the invention. As shown in FIG. 4, the method for detecting and repairing a display panel of the present embodiment includes the following steps.

Step 30: providing display panels of FIGS. 1 and 2; and step 32: performing a first detecting step to detect that one of the first gate driving array circuit GOA1 and the second gate driving array circuit GOA2 is missing Step 34: performing a second detecting step, when the first gate driving array circuit GOA1 is disabled, inputting the start signal ST to the second gate driving units UB1 UBUBn of the second gate driving array circuit GOA2, The high-frequency signal HC, the low-level switching signal LC, and the low-level signal VSS input a low-level switching signal LC and a low-level signal VSS to the first gate driving unit UA1~UAn of the first gate driving array circuit GOA1. And cutting off the start signal ST of the first gate driving unit UA1~UAn of the first gate driving array circuit GOA1 and the high frequency signal HC to determine a bad first gate driving unit; and step 36: performing A repair step to repair the bad first gate drive unit.

The method for detecting and repairing the display panel of the present embodiment will be further described below. The first detecting step of this embodiment includes the following steps. The first gate driving unit UA1~UAn of the first gate driving array circuit GOA1 inputs the start signal ST, the high frequency signal HC, the low level switching signal LC, and the low level signal VSS, and is not driven by the second gate. The second gate driving unit UB1~UBn of the array circuit GOA2 inputs the start signal ST, the high frequency signal HC, the low level switching signal LC and the low level signal VSS to determine whether the first gate driving array circuit GOA1 is disabled. . Since the second gate driving units UB1 UB UBn of the second gate driving array circuit GOA2 do not receive the start signal ST, the high frequency signal HC, the low level switching signal LC, and the low level signal VSS, if the first gate When the pole drive array circuit GOA1 is disabled, the display panel 10 cannot be displayed normally. In addition, the second gate driving unit UB1 UB UBn of the second gate driving array circuit GOA2 inputs the start signal ST, the high frequency signal HC, the low level switching signal LC, and the low level signal VSS, and does not apply to the first gate. The first gate driving unit UA1~UAn of the pole drive array circuit GOA1 inputs a start signal ST, high frequency signal HC, low level switching signal LC and low level signal VSS to determine whether the second gate driving array circuit GOA2 is disabled. The first gate driving unit UA1~UAn of the first gate driving array circuit GOA1 does not receive the start signal ST, the high frequency signal HC, the low level switching signal LC, and the low level signal VSS, so if the second gate When the pole drive array circuit GOA2 is disabled, the display panel 10 cannot be displayed normally. Therefore, when one of the first gate driving array circuit GOA1 and the second gate driving array circuit GOA2 is disabled, it can be detected by the sequential single-sided driving mode described above.

In the second detecting step of this embodiment, when the first gate drives the array circuit GOA1 When the second gate driving unit UB1~UBn of the second gate driving array circuit GOA2 is disabled, a start signal ST, a high frequency signal HC, a low level switching signal LC, and a low level signal VSS are input. Inputting a low level switching signal LC and a low level signal VSS to the first gate driving unit UA1~UAn of the first gate driving array circuit GOA1, and cutting off the first gate of the first gate driving array circuit GOA1 One of the pole drive units UA1~UAn starts the signal ST and a high frequency signal HC. After the high frequency signal HC is cut off, the input end of the high frequency signal HC of the first gate driving unit UA1~UAn of the first gate driving array circuit GOA1 loses the signal level and is in a floating state. This can determine a bad first gate drive unit. The start signal ST and the high frequency signal HC that cut off the first gate driving units UA1 to UAn of the first gate driving array circuit GOA1 can be controlled by, for example, laser cutting or by using a switch. Precisely, since the first end t1 and the second end t2 of the gate lines GL1 GL GLn are electrically connected to the first gate driving array circuit GOA1 and the second gate driving array circuit GOA2, respectively, when the first gate When the start signal ST of the first gate driving unit UA1~UAn of the driving array circuit GOA1 and the high frequency signal HC are cut off, the pull-up control circuit 211 of the first stage cannot be activated, and the pull-up driving circuit 212 is at this time. It also has no effect, but the second gate driving array circuit GOA2 is a normal output, so the second stage to the nth stage pull-up control circuit 211 of the first gate driving array circuit GOA1 can be turned on through the gate lines GL2 GL GLn. And causing the pull-up drive circuit 212 to output a signal, but due to the first gate drive array The high frequency signal HC of the column circuit GOA1 has been cut off, so the level of the output of the pull-up driving circuit 212 is incorrect. Since the second gate driving array circuit GOA2 is normal, the voltage of the gate lines GL2 GL GLn will still be at the Vgh level. . The abnormal level circuit may be a short circuit between the gate line and the signal line transmitting the high frequency signal HC or a short circuit between the gate line and the signal line transmitting the low level signal VSS, even if the second gate drive array circuit GOA2 is normal. The driving voltage of the gate line connected to the first gate driving unit of the abnormal level is still different from the driving voltage of the gate line connected to the first gate driving unit of other stages, so that it can be seen from the display A significant abnormality was detected and a bad first gate drive unit was detected.

After the defective first gate drive unit is detected, the repair steps that may be taken may include The electrical connection between the defective first gate driving unit and the first end of the corresponding gate line is cut off. For example, if the bad first gate driving unit is the first gate driving unit UA3 of the third stage, the first gate driving unit UA3 of the third stage and the first end of the corresponding gate line GL3 can be cut off. Electrical connection of t1. At this time, the pixel P corresponding to the gate line GL3 forms a weak line on the display, but is still an acceptable display.

In addition, the detection method of this embodiment can further determine a bad first gate drive The unit is caused by an abnormality of the pull-down unit or an abnormality of the pull-up unit, and the corresponding repair method is adopted. For example, if the pull-down unit is abnormal, you will see an anomaly with a period of 1.6 seconds. Otherwise, the pull-up unit is abnormal. If the pull-down unit is abnormal, the repairing step may include cutting off the input of the low-level signal VSS of the bad pull-down unit. For example, if the bad pull-down unit is the pull-down unit 22 of the first gate driving unit UA3 of the third stage, the repairing step may include cutting off the low-level signal of the pull-down unit 22 of the first gate driving unit UA3 of the third stage. The end of VSS. If the pull-up unit is abnormal, the repairing step may include cutting off the input end of the high-frequency signal HC of the bad pull-up unit. For example, if the bad pull-up unit is the pull-up unit 21 of the first gate drive unit UA3 of the third stage, the repairing step may include cutting off the pull-up unit 21 of the first gate drive unit UA3 of the third stage. The floating signal at the input.

The above embodiment is an example of the present invention when an abnormality occurs in the first gate driving unit. The method for detecting and repairing the display panel can also use the same method of detecting and repairing the display panel if an abnormality occurs in the second gate driving unit.

In summary, the method for detecting and repairing a display panel of the present invention can effectively detect and The gate drive array circuit of the display panel with the bilateral drive architecture is repaired, thereby reducing the number of scraps of the display panel, thereby greatly reducing the manufacturing cost of the display panel. In addition, the detection and repair display panel of the present invention does not need to additionally provide a repair line on the display panel, and can reduce the layout area of the peripheral area.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ display panel

GL1~GLn‧‧‧ gate line

First end of t1‧‧

T2‧‧‧ second end

GOA1‧‧‧First Gate Drive Array Circuit

GOA2‧‧‧Second Gate Drive Array Circuit

UA1‧‧‧first gate drive unit

UA2‧‧‧first gate drive unit

UA3‧‧‧First Gate Drive Unit

UAn‧‧‧First Gate Drive Unit

UB1‧‧‧Second gate drive unit

UB2‧‧‧Second gate drive unit

UB3‧‧‧Second gate drive unit

UBn‧‧‧Second gate drive unit

21‧‧‧Upper unit

22‧‧‧Drawdown unit

211‧‧‧ Pull-up control circuit

212‧‧‧ Pull-up drive circuit

221‧‧‧ Pull-down control circuit

222‧‧‧ Pull-down drive circuit

ST‧‧‧ start signal

HC‧‧‧High frequency signal

HC1‧‧‧ high frequency signal

HC2‧‧‧ high frequency signal

HC3‧‧‧ high frequency signal

HCn‧‧‧ high frequency signal

LC‧‧‧low level switch signal

VSS‧‧‧low level signal

Claims (6)

A method for detecting and repairing a display panel, comprising: providing a display panel, comprising: a plurality of gate lines, wherein each of the gate lines has a first end and a second end; and a first gate driving array circuit, The first gate driving array circuit includes a plurality of first gate driving units electrically connected to the first ends of the gate lines, and the first gate driving units include a plurality of stages, wherein the first level The first gate driving unit is electrically connected to the first gate driving unit of the next stage; and a second gate driving array circuit, the second gate driving array circuit includes a plurality of second gate driving The second gate driving unit is electrically connected to the second terminals of the gate lines, wherein the second gate driving unit comprises a plurality of stages, wherein the second gate driving unit of the upper stage and the second of the next stage The gate driving unit is electrically connected; performing a first detecting step to detect that one of the first gate driving array circuit and the second gate driving array circuit is disabled; performing a second detecting step, when The first gate drive When the array circuit is disabled, each of the second gate driving units of the second gate driving array circuit inputs a start signal ST, a high frequency signal HC, a low level switching signal LC, and a low level signal VSS. Inputting the low level switching signal LC and the low level signal VSS to each of the first gate driving units of the first gate driving array circuit, and cutting off each of the first gate driving array circuits One of the gate driving units starts the signal ST and a high frequency signal HC to determine a bad first gate driving unit; and performs a repairing step to repair the defective first gate driving unit. The method of detecting and repairing a display panel according to claim 1, wherein repairing the defective first gate driving unit comprises cutting off the defective first gate driving unit and the corresponding gate line Electrical connection at one end. The method for detecting and repairing a display panel according to claim 1, wherein each of the first gate driving unit and each of the second gate driving units respectively comprises: a pull-up unit, comprising: an upper Pulling control circuit for receiving the start signal ST and the high frequency signal HC; and a pull-up driving circuit electrically connected to the pull-up control circuit and the corresponding gate line, and receiving the pull-up control circuit The high frequency signal HC; and a pull-down unit, comprising: a pull-down control circuit, connected to the pull-up unit for receiving the low level switch signal LC and the low level signal VSS; And a pull-down drive circuit is connected to the pull-up unit. The method of detecting and repairing a display panel according to claim 3, wherein the defective first gate driving unit comprises a bad pull-up unit, and the repairing step comprises cutting the high-frequency signal HC of the bad pull-up unit. The method of detecting and repairing a display panel according to claim 3, wherein the bad first gate driving unit comprises a bad pull-down unit, and the repairing step comprises cutting off the low level signal VSS of the bad pull-down unit. The method of detecting and repairing a display panel according to claim 1, wherein the first detecting step comprises: inputting the start signal ST, the height of each of the first gate driving units of the first gate driving array circuit The frequency signal HC, the low level switching signal LC, and the low level signal VSS do not input the start signal ST and the high frequency signal HC to each of the second gate driving units of the second gate driving array circuit. The low level switch signal LC and the low level signal No. VSS to determine whether the first gate driving array circuit is disabled; and inputting the start signal ST, the high frequency signal HC, and the second gate driving unit of the second gate driving array circuit The low level switching signal LC and the low level signal VSS do not input the start signal ST, the high frequency signal HC, and the low level to each of the first gate driving units of the first gate driving array circuit. The switching signal LC and the low level signal VSS are used to determine whether the second gate driving array circuit is disabled.