TWI521610B - Method for manufacturing multi-gate transistor device - Google Patents

Description

Multi-gate polar crystal element manufacturing method

The invention relates to a method for fabricating a multi-gate transistor.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a Fin Field effect transistor (FinFET) component replaces a planar transistor component.

Please refer to FIG. 1 , which is a perspective view of a conventional FinFET device. As shown in FIG. 1 , the conventional FinFET device 100 firstly patterns a single crystal germanium layer on the surface of the insulating substrate 102 by etching or the like to form a fin-shaped germanium film in the insulating substrate 102 ( The figure is not shown, and a high dielectric constant (high-k) insulating layer 104 covering a portion of the germanium film is formed on the germanium film, and the gate 106 is coated with the high dielectric constant insulating layer 104 and germanium. On the film, the source/drain 108 is finally formed in the fin-shaped germanium film not covered by the gate 106 by an ion implantation process and a tempering process. Since the process of the FinFET device 100 can be integrated with a conventional logic device process, it has considerable process compatibility. In addition, due to the special structure of the FinFET element 100, conventional isolation techniques such as shallow trench isolation can be omitted. More importantly, since the three-dimensional structure of the FinFET element 100 increases the contact area of the gate 106 with the fin-shaped germanium substrate, the carrier control of the gate 106 for the channel region can be increased, thereby reducing the size of the small-sized component. The source induced induced drain induced barrier lowering (DIBL) effect and the short channel effect. Furthermore, since the gate 106 of the same length in the FinFET element 100 has a larger channel width, a doubled drain drive current can be obtained.

While the FinFET component 100 can achieve higher drain drive currents, the FinFET component 100 still faces many problems to be solved. For example, the surface roughness of the source/drain 108 fin portion has an effect on the electrical performance of the FinFET element 100, as well as corner leakage that cannot be solved by the fin portion. Therefore, there is still a need for a method of fabricating a multi-gate transistor element that solves the above problems.

Accordingly, it is an object of the present invention to provide a method of fabricating a multi-gate transistor device that solves the above problems.

According to the patent application scope of the present invention, a method for fabricating a multi-gate transistor device is provided. The fabrication method first provides a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask formed thereon. The patterned hard mask is then removed and a heat treatment is performed to fillet the patterned semiconductor layer, and one of the heat treatment processes is less than 800 degrees Celsius (° C.). After the heat treatment, a gate dielectric layer and a gate layer are sequentially formed on the substrate, and the gate dielectric layer and the gate layer cover a portion of the patterned semiconductor layer.

The multi-gate transistor device according to the present invention is manufactured by a heat treatment process having a process temperature lower than 800 ° C, and effectively rounding the top corner of the rectangular patterned semiconductor layer in accordance with the FinFET low thermal budget. , reducing the possibility of leakage at the top corner. At the same time, the method for fabricating the multi-gate transistor device provided by the present invention improves the surface roughness of the patterned semiconductor layer by heat treatment, thereby being more beneficial to the formation of the subsequent gate dielectric layer and the gate layer. And electrical performance of the multi-gate transistor component.

Please refer to FIG. 2 to FIG. 5 . FIG. 2 to FIG. 5 are schematic diagrams showing a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention. As shown in FIG. 2, the preferred embodiment first provides a semiconductor substrate 200, which may include a silicon-on-insulator (SOI) substrate. As is known to those skilled in the art, the SOI substrate may include a substrate 202, a bottom oxide (BOX) layer 204, and a semiconductor layer formed on the bottom oxide layer 204 from bottom to top. Shown as a layer of germanium with a single crystal structure. However, in order to provide better heat dissipation and grounding effects, and to help reduce cost and suppress noise, the semiconductor substrate 200 provided by the preferred embodiment may include a bulk silicon substrate.

Please continue to see Figure 2. A patterned hard mask 208 is then formed over the semiconductor substrate 200 to define fin portions of at least one of the plurality of gate transistor elements. Subsequently, an etching process is performed to remove a portion of the semiconductor layer of the semiconductor substrate 200, and at least one patterned semiconductor layer 206 is formed on the semiconductor substrate 200. The patterned semiconductor layer 206 includes at least one gate as shown in FIG. The fin portion of the polar crystal element. The patterned semiconductor layer 206 has a width and a height, the width having a ratio to the height, and the ratio may be 1:1.5 to 1:2, but is not limited thereto.

Please refer to Figure 3. After the fabrication of the patterned semiconductor layer 206 is completed, the patterned hard mask 208 is removed to expose the patterned semiconductor layer 206. As shown in FIG. 3, the patterned semiconductor layer 206 is an elongated rectangular solid structure. The apex angle of the patterned semiconductor layer 206, as circled by the circle 206a in FIG. 3, is a sharp corner, and thus often occurs at the sharp apex angles after the fabrication of the multi-gate transistor element is completed. The problem of leakage at the top corner.

Please refer to Figure 4. A heat treatment 210 is then performed to fillet the patterned semiconductor layer 206. In detail, the heat treatment 210 provided in the preferred embodiment includes a step of introducing hydrogen gas, and the gas flow rate of hydrogen gas is 10 to 15 standard liter per minute (slm), and the heat treatment 210 has a process pressure. And the process pressure is less than 1 Torr. The process temperature of the heat treatment 210 provided by the preferred embodiment is less than 800 ° C, and preferably less than 740 ° C. In addition, the heat treatment 210 has a process time that does not exceed 2 minutes. Since the apex angle of the patterned semiconductor layer 206 or even the high energy at the corner bordering the bottom oxide layer 204, the ruthenium material at the apex angle and the corner is easily reacted with hydrogen and stripped away from the patterning. Semiconductor layer 206. Therefore, the heat treatment 210 for introducing hydrogen gas can effectively fillet the patterned semiconductor layer 206 under a lower thermal budget and a shorter process time, and as shown in FIG. 4, has a rounded apex angle. (circled by circle 206b) is even a patterned semiconductor layer 206 having rounded corners (circled by circle 206c).

Please refer to Figure 5. Next, a dielectric layer (not shown), a gate forming layer (not shown), and a patterned hard mask 224 are sequentially formed on the semiconductor substrate 200. Subsequently, the dielectric layer and the gate forming layer are patterned, and a gate dielectric layer 220 and a gate layer 222 covering a portion of the patterned semiconductor layer 206 are formed on the semiconductor substrate 200. As shown in FIG. 5, the extension direction of the gate dielectric layer 220 and the gate layer 222 is perpendicular to the extending direction of the patterned semiconductor layer 206, and the gate dielectric layer 220 and the gate layer 222 are partially patterned. The sidewall of the semiconductor layer 206. The gate dielectric layer 220 may comprise a dielectric material such as cerium oxide (SiO), cerium nitride (SiN), cerium oxynitride (SiON) or the like. In the preferred embodiment, the gate dielectric layer 220 may further comprise a high-k material, such as hafnium oxide (HfO), hafnium niobate (HfSiO) or aluminum, zirconium, hafnium, etc. Metallic metal oxides or metal silicates, etc., but are not limited thereto. In addition, when the gate dielectric layer 220 of the preferred embodiment is made of a high-K material, the present invention can be integrated with a metal gate process to provide sufficient control for matching the high-K gate dielectric layer. electrode. Accordingly, the gate layer 222 can be made of a different material depending on the gate-first process or the gate-last process of the metal gate. For example, when the preferred embodiment is integrated with the front gate process, the gate layer 222 may comprise a metal such as tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), or the like. Alloys, metal nitrides such as tantalum nitride (TaN), titanium nitride (TiN), molybdenum nitride (MoN), etc., metal carbides such as tantalum carbide (TaC). And the selection of the metals is based on the principle of the conductive form of the multi-gate transistor element to be obtained, that is, the metal satisfying the required work function of the N-type or P-type transistor is the selection principle, and the gate layer 222 It may be a single layer structure or a multi-layered structure. When the preferred embodiment is integrated with the post gate process, the gate layer 222 acts as a dummy gate, which may comprise a semiconductor material such as a polysilicon or the like.

After the fabrication of the gate dielectric layer 220 and the gate layer 222 is completed, the preferred embodiment can form a source/drain in the first patterned semiconductor layer 206 by oblique ion implantation or the like as needed. Source/drain extension region (not shown). After the source/drain extension region is formed, sidewalls (not shown) are formed on the opposite sidewalls of the gate layer 222 and the gate dielectric layer 220, and the sidewalls may be a single layer structure or a composite layer structure. . After the fabrication of the sidewalls is completed, a selective epitaxial growth (SEG) process can be performed to form an epitaxial layer (not shown) on the surface of the patterned semiconductor layer 206. In addition, in the SEG process, a material having a lattice constant different from the lattice constant of the patterned semiconductor layer 206 may be added according to the conductivity type of the multi-gate transistor element, and may be added during, before, or after the SEG process. The doping of the conductive type, thereby completing the fabrication of the source/drain of the multi-gate transistor element, and simultaneously completing the fabrication of the multi-gate transistor element provided by the preferred embodiment. Since the above-mentioned gate dielectric layer 220, gate layer 222, source/drain extension region, sidewall spacer, and epitaxial source/drainage are known to those skilled in the art, This will not go into details.

The method for fabricating a multi-gate transistor according to the first preferred embodiment is effectively rounded by a heat treatment 210 for introducing hydrogen into a process temperature lower than 740 ° C to meet the FinFET low heat budget. The apex angle of the rectangular patterned semiconductor layer 206 (as indicated by the circle 206b) reduces the likelihood of apex discharge. At the same time, the method for fabricating the multi-gate transistor device provided by the present invention improves the surface roughness of the patterned semiconductor layer 206 by the heat treatment 210, thereby facilitating the formation of the subsequent gate dielectric layer 220 and the gate layer 222. And the electrical performance of multi-gate transistor components. In addition, the heat treatment 210 may also fillet the corners of the patterned semiconductor layer 206 to form a recessed corner (as indicated by the circle 206c), and subsequently form a pad oxide layer at the recessed corner to reduce the tip leakage current.

Next, please refer to FIG. 6. FIG. 6 is a schematic view showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention. It is to be noted that the same components as the first preferred embodiment of the second preferred embodiment are denoted by the same reference numerals, and the materials and forming methods of the same components can be referred to the first preferred embodiment. As described, it will not be repeated here. As shown in FIG. 6, the preferred embodiment first provides a semiconductor substrate 200. The semiconductor substrate 200 can include a silicon-on-insulator (SOI) substrate, and the SOI substrate includes a substrate 202 and a bottom from bottom to top. The oxide layer 204, and a semiconductor layer (not shown) formed on the bottom oxide layer 204, such as a germanium layer having a single crystal structure, the semiconductor substrate 200 provided in the preferred embodiment may comprise a germanium substrate.

As previously described, a patterned hard mask (not shown) is formed over the semiconductor substrate 200 to define the fin portions of at least one of the plurality of gate transistor elements. An etching process is then performed to remove a portion of the semiconductor layer of the semiconductor substrate 200, and at least one patterned semiconductor layer 206 is formed over the semiconductor substrate 200. The patterned semiconductor layer 206 has a width and a height, the width having a ratio to the height, and the ratio may be 1:1.5 to 1:2. After the fabrication of the patterned semiconductor layer 206 is completed, the patterned hard mask is removed to expose the patterned semiconductor layer 206. As described above, the patterned semiconductor layer 206 is an elongated rectangular solid structure having sharp corners at the apex angles, and thus often occurs at the sharp apex angles after the fabrication of the multi-gate transistor element is completed. The problem of leakage at the top corner.

Please refer to Figure 6. A heat treatment 230 is then performed to fillet the patterned semiconductor layer 206. In detail, the heat treatment 230 provided in the preferred embodiment includes a step of introducing hydrogen gas and hydrogen chloride, wherein the gas flow rate of hydrogen gas is 20-40 minutes per minute standard liter; and the gas flow rate of hydrogen chloride is 20-120 standard cubic meters per minute. Standard cubic centimeter per minute (sccm). And the heat treatment 230 has a process pressure that is less than 10 Torr. The process temperature of the heat treatment 230 provided by the preferred embodiment is less than 800 ° C, and preferably less than 720 ° C. In addition, the heat treatment 230 has a process time that does not exceed 2 minutes. Since the apex angle of the patterned semiconductor layer 206 has a high free energy even at the corner bordering the bottom oxide layer 204, the apex material at the apex angle and the corner is easily reacted with hydrogen and stripped away from the patterning. Semiconductor layer 206. Further, since hydrogen chloride is further added to the preferred embodiment, the chloride ion in the hydrogen chloride accelerates the progress of the reaction. The heat treatment 230 system for introducing hydrogen and hydrogen chloride provided by the preferred embodiment can effectively fillet the patterned semiconductor under a lower thermal budget, a wider process pressure, and a shorter process time. Layer 206, and as shown in FIG. 6, forms a patterned semiconductor layer 206 having a circular apex angle (circled by circle 206b) and a rounded corner (circled by circle 206c).

Subsequently, as described above, the gate dielectric layer 220, the gate layer 222, the source/drain extension region, the sidewall spacer, and the epitaxial source/drain may be sequentially fabricated, and the components are The production department is known to those familiar with the art and will not be repeated here.

The method for fabricating a multi-gate transistor according to the second preferred embodiment is effective by a heat treatment 230 for introducing hydrogen and hydrogen chloride at a process temperature lower than 720 ° C to meet the FinFET low heat budget. The rounded corners pattern the apex angle of the semiconductor layer 206, thereby reducing the likelihood of apex discharge. At the same time, the method for fabricating the multi-gate transistor device provided by the present invention improves the surface roughness of the patterned semiconductor layer 206 by heat treatment, thereby facilitating the formation of the subsequent gate dielectric layer and the gate layer and the gate Electrical performance of a polar crystal component. In addition, the heat treatment 230 may also fillet the corners of the patterned semiconductor layer 206 to form a recessed corner (as indicated by the circle 206c), and subsequently form a pad oxide layer at the recessed corner to reduce leakage current.

In summary, the method for fabricating the multi-gate transistor of the present invention is effective by heat treatment at a temperature lower than 800 ° C or even at a temperature lower than 720 ° C in accordance with the low thermal budget of the FinFET. Cornering the corners of the rectangular patterned semiconductor layer reduces the likelihood of apex discharge. At the same time, the method for fabricating the multi-gate transistor device provided by the present invention improves the surface roughness of the patterned semiconductor layer by heat treatment, and even changes the lattice arrangement of the patterned semiconductor layer, thereby further benefiting the subsequent gate dielectric. Formation of layers and gate layers and electrical representation of multi-gate transistor elements.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Fin field effect transistor component

102. . . Overlying insulating substrate

104. . . High dielectric constant insulating layer

106. . . Gate

108. . . Source/bungee

200. . . Semiconductor substrate

202. . .矽 base

204. . . Bottom oxide layer

206. . . Patterned semiconductor layer

206a. . . Top angle

206b. . . Top angle

206c. . . corner

208. . . Patterned hard mask

210. . . Heat treatment

220. . . Gate dielectric layer

222. . . Gate layer

224. . . Patterned hard mask

230. . . Heat treatment

Figure 1 is a perspective view of a conventional FinFET device.

2 to 5 are schematic views showing a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention.

FIG. 6 is a schematic view showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention.

200. . . Semiconductor substrate

202. . .矽 base

204. . . Bottom oxide layer

206. . . Patterned semiconductor layer

206b. . . Top angle

206c. . . corner

210. . . Heat treatment

Claims (11)

A method of fabricating a multi-gate transistor device, comprising: providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask formed thereon; removing the patterned hard mask; performing a heat treatment Filling the patterned semiconductor layer with a fillet, and one of the heat treatment processes is less than 800 degrees Celsius (° C.), and the heat treatment process further includes a step of introducing hydrogen gas and hydrogen chloride (HCl); and Forming a gate dielectric layer and a gate layer, the gate dielectric layer and the gate layer covering a portion of the patterned semiconductor layer. The manufacturing method of claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The manufacturing method of claim 1, wherein the gate dielectric layer comprises a high dielectric constant material. The manufacturing method of claim 1, wherein the heat treatment further comprises a step of introducing hydrogen. The method of claim 4, wherein the heat treatment has a process pressure and the process pressure is less than 1 Torr. The method of claim 4, wherein the heat treatment process temperature is preferably lower than 740 °C. The manufacturing method of claim 1, wherein the heat treatment has a process pressure and the process pressure is less than 10 Torr. The manufacturing method of claim 1, wherein the heat treatment process temperature is preferably less than 720 degrees. The manufacturing method according to claim 1, wherein the hydrogen gas flow rate is 20 to 40 standard liter per minute (slm). The production method according to claim 1, wherein the hydrogen chloride gas flow rate is 20 to 120 standard cubic centimeters per minute (sccm). The manufacturing method of claim 1, wherein the heat treatment process time is less than 2 minutes.