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TWI521677B - Capacitor in integrated circuit - Google Patents

Capacitor in integrated circuit Download PDF

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Publication number
TWI521677B
TWI521677B TW102137369A TW102137369A TWI521677B TW I521677 B TWI521677 B TW I521677B TW 102137369 A TW102137369 A TW 102137369A TW 102137369 A TW102137369 A TW 102137369A TW I521677 B TWI521677 B TW I521677B
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Taiwan
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capacitor
electrode
transistor
integrated circuit
metal
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TW102137369A
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Chinese (zh)
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TW201517244A (en
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葉潤林
廖偉智
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華邦電子股份有限公司
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Description

積體電路的電容 Capacitor of integrated circuit

本發明是有關於一種電容的結構,且特別是有關於一種積體電路的電容的結構。 The present invention relates to a structure of a capacitor, and more particularly to a structure of a capacitor of an integrated circuit.

隨著半導體技術的進步,積體電路已成為電子裝置中重要的元件。其中,在積體電路中配置內嵌的電容,常是晶體電路中的重要構件。然而,要在積體電路中配置具有足夠大電容值的電容,經常耗去積體電路很大的佈局面積,也因此,在積體電路的成本的考量下,如何在積體電路中建構一個具有足夠大電容值的內嵌電容成為該領域設計者所重視的一個課題。 With the advancement of semiconductor technology, integrated circuits have become an important component in electronic devices. Among them, the embedded capacitor in the integrated circuit is often an important component in the crystal circuit. However, it is necessary to dispose a capacitor having a sufficiently large capacitance value in the integrated circuit, which often consumes a large layout area of the integrated circuit, and therefore, how to construct a built-in circuit in consideration of the cost of the integrated circuit Embedded capacitors with large enough capacitance values have become a topic of interest to designers in this field.

本發明提供一種本發明提供一種積體電路的電容,利用有限的面積來提供更大電容值。 The present invention provides a capacitor for an integrated circuit that utilizes a limited area to provide a larger capacitance value.

本發明提供的積體電路的電容包括基底層、第一電容以及第二電容,第一電容配置在基底層中。第二電容配置在第一電容上並至少部份覆蓋第一電容。其中,第一電容的第一電極耦接 至第二電容的第一電極,且第一電容的第二電極耦接至第二電容的第二電極。 The capacitor of the integrated circuit provided by the present invention comprises a base layer, a first capacitor and a second capacitor, and the first capacitor is disposed in the base layer. The second capacitor is disposed on the first capacitor and at least partially covers the first capacitor. Wherein the first electrode of the first capacitor is coupled The first electrode of the second capacitor is coupled to the second electrode of the second capacitor.

基於上述,本發明透過在積體電路中,利用不同的材質來在基底層的同一垂直延伸的方向上進行多個電容的佈局,並透過將這些電容進行並連,以有效的在固定的區域中,可以提供足夠大電容值的電容。如此一來,積體電路中的內嵌電容可以不會佔去過大的佈局面積而影響成本。 Based on the above, the present invention performs a layout of a plurality of capacitors in the same vertical extending direction of the base layer by using different materials in the integrated circuit, and by connecting the capacitors in parallel, effectively in a fixed area. A capacitor with a large enough capacitance value can be provided. In this way, the embedded capacitor in the integrated circuit can not affect the excessive layout area and affect the cost.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.

100、300、600‧‧‧積體電路的電容 100, 300, 600‧‧ ‧ capacitance of integrated circuit

110、510、710‧‧‧基底層 110, 510, 710‧‧ ‧ basal layer

120、320、620、720‧‧‧第一電容 120, 320, 620, 720‧‧‧ first capacitor

130、330、630、730‧‧‧第二電容 130, 330, 630, 730‧‧‧ second capacitor

E11、E21‧‧‧第一電極 E11, E21‧‧‧ first electrode

E12、E22‧‧‧第二電極 E12, E22‧‧‧ second electrode

T1~TN‧‧‧電晶體 T1~TN‧‧‧O crystal

S‧‧‧源極 S‧‧‧ source

D‧‧‧汲極 D‧‧‧汲

G‧‧‧閘極 G‧‧‧ gate

C1、C2‧‧‧接觸窗 C1, C2‧‧‧ contact window

A-A’‧‧‧線段 A-A’‧‧‧ segment

M11~M36‧‧‧金屬圖案 M11~M36‧‧‧ metal pattern

500‧‧‧電晶體電容 500‧‧‧Transistor Capacitance

520、530‧‧‧井區 520, 530‧‧ ‧ well area

541、542‧‧‧摻雜區 541, 542‧‧‧Doped area

550‧‧‧多晶矽層 550‧‧‧ Polycrystalline layer

圖1繪示本發明一實施例的積體電路的電容的示意圖。 FIG. 1 is a schematic diagram showing the capacitance of an integrated circuit according to an embodiment of the present invention.

圖2繪示的積體電路的電容的等效電路圖。 FIG. 2 is an equivalent circuit diagram of the capacitance of the integrated circuit.

圖3繪示本發明另一實施例的積體電路的電容的等效電路圖。 3 is an equivalent circuit diagram of a capacitor of an integrated circuit according to another embodiment of the present invention.

圖4A以及4B分別繪示本發明實施例的積體電路的電容的上市圖及剖面圖。 4A and 4B are respectively a market diagram and a cross-sectional view showing the capacitance of the integrated circuit of the embodiment of the present invention.

圖5繪示本發明實施例的電晶體電容的一實施方式。 FIG. 5 illustrates an embodiment of a transistor capacitor in accordance with an embodiment of the present invention.

圖6A以及圖6B分別繪示本發明再一實施例的積體電路的電容的剖面圖以及等效電路圖。 6A and 6B are respectively a cross-sectional view and an equivalent circuit diagram of a capacitor of an integrated circuit according to still another embodiment of the present invention.

請參照圖1,圖1繪示本發明一實施例的積體電路的電容的示意圖。積體電路的電容100包括基底層110、第一電容120以及第二電容130。第一電容120配置在基底層110中,第二電容130則配置在第一電容120上。並且,第二電容130至少部份覆蓋第一電容120。此外,請同步參照圖2繪示的積體電路的電容的等效電路圖。其中,第一電容120具有第一電極E11以及第二電極E12,而第二電容120則具有第一電極E21以及第二電極E22。並且,第一電容120的第一電極E11耦接至第二電容120的第一電極E21,且第一電容120的第二電極E12耦接至第二電容120的第二電極E22。 Please refer to FIG. 1. FIG. 1 is a schematic diagram showing the capacitance of an integrated circuit according to an embodiment of the present invention. The capacitor 100 of the integrated circuit includes a base layer 110, a first capacitor 120, and a second capacitor 130. The first capacitor 120 is disposed in the base layer 110, and the second capacitor 130 is disposed on the first capacitor 120. Moreover, the second capacitor 130 at least partially covers the first capacitor 120. In addition, please refer to FIG. 2 for an equivalent circuit diagram of the capacitance of the integrated circuit. The first capacitor 120 has a first electrode E11 and a second electrode E12, and the second capacitor 120 has a first electrode E21 and a second electrode E22. The first electrode E11 of the first capacitor 120 is coupled to the first electrode E21 of the second capacitor 120, and the second electrode E12 of the first capacitor 120 is coupled to the second electrode E22 of the second capacitor 120.

值得注意的是,在圖1中,第二電容130可以完全或是部份的覆蓋第一電容120的上表面。重點是,第一電容120與第二電容130是相互重疊於基底層110上的,如此一來,第二電容130的佈局不用透過多餘的積體電路的區域來進行,可有效節省佈局空間。再者,第一電容120以及第二電容130是相互並連耦接的,因此,電容100所提供的電容值可以有效的增大。 It should be noted that in FIG. 1, the second capacitor 130 may completely or partially cover the upper surface of the first capacitor 120. The main point is that the first capacitor 120 and the second capacitor 130 overlap each other on the base layer 110. Therefore, the layout of the second capacitor 130 is not performed through the area of the redundant integrated circuit, which can effectively save layout space. Moreover, the first capacitor 120 and the second capacitor 130 are coupled to each other in parallel, and therefore, the capacitance value provided by the capacitor 100 can be effectively increased.

另外,在本實施例中,第一電容120並不限定其材質。第一電容120可以利用半導體製程中可形成電容的各種材質來建構,例如,電晶體電容、接面電容(junction capacitor)或是金屬-絕緣層-金屬(MIM)電容。 In addition, in the embodiment, the first capacitor 120 is not limited to its material. The first capacitor 120 can be constructed using various materials that can form a capacitor in a semiconductor process, such as a transistor capacitor, a junction capacitor, or a metal-insulator-metal (MIM) capacitor.

以下請參照圖3,圖3繪示本發明另一實施例的積體電路 的電容的等效電路圖。在本實施例中,積體電路的電容300包括相互並連的第一電容320以及第二電容330。其中,第一電容320是由電晶體T1所構成的電晶體電容。其中,電晶體T1的源極S以及汲極D相互耦接已成為第一電容320的第一電極E11,而電晶體T1的閘極G則成為第一電容320的第二電極E12。 Please refer to FIG. 3, which illustrates an integrated circuit according to another embodiment of the present invention. The equivalent circuit diagram of the capacitor. In this embodiment, the capacitor 300 of the integrated circuit includes a first capacitor 320 and a second capacitor 330 that are connected in parallel with each other. The first capacitor 320 is a transistor capacitor formed by the transistor T1. The source S and the drain D of the transistor T1 are coupled to each other to become the first electrode E11 of the first capacitor 320, and the gate G of the transistor T1 is the second electrode E12 of the first capacitor 320.

關於圖3的積體電路的電容300的結構,請參照圖4A以及4B,圖4A以及4B分別繪示本發明實施例的積體電路的電容的上市圖及剖面圖。在圖4A中,第二電容330由金屬圖樣331以及332交錯佈局而成,其中的金屬圖樣331形成第二電容330的第一電極E21,而金屬圖樣332則形成第二電容330的第二電極E22。 For the structure of the capacitor 300 of the integrated circuit of FIG. 3, please refer to FIG. 4A and FIG. 4B. FIG. 4A and FIG. 4B are respectively a market diagram and a cross-sectional view showing the capacitance of the integrated circuit of the embodiment of the present invention. In FIG. 4A, the second capacitor 330 is formed by staggering the metal patterns 331 and 332, wherein the metal pattern 331 forms the first electrode E21 of the second capacitor 330, and the metal pattern 332 forms the second electrode of the second capacitor 330. E22.

第二電容330的第一電極E21以及第二電容330的第二電極E22覆蓋在第一電容320上。而第二電容330的第一電極E21可透過多數個接觸窗(contact window)C1來與第一電容320的第一電極相耦接,而第二電容330的第二電極E22則可透過多數個接觸窗C2來與第一電容320的第二電極相耦接。 The first electrode E21 of the second capacitor 330 and the second electrode E22 of the second capacitor 330 are overlaid on the first capacitor 320. The first electrode E21 of the second capacitor 330 can be coupled to the first electrode of the first capacitor 320 through a plurality of contact windows C1, and the second electrode E22 of the second capacitor 330 can pass through a plurality of The contact window C2 is coupled to the second electrode of the first capacitor 320.

圖4B繪示依據圖4A的線段A-A’的積體電路的電容300的剖面圖。其中,第二電容330包括由分布於不同金屬層的多個金屬圖案M11~M36所構成。其中,金屬圖案M11~M15分布在最頂層的金屬層中,金屬圖案M21~M26則分布在第二金屬層,金屬圖案M31~M36則分布在最底的金屬層中。在本實施例中,相同金屬層中的相鄰的金屬圖案是相互物理性隔離的,並且,在金屬圖案M11~M15中,金屬圖案M11、M13、M15相互耦接以形成第二 電容330的第一電極,而金屬圖案M12及M14相互耦接以形成第二電容330的第二電極。另外,在金屬圖案M21~M26中,金屬圖案M21、M23、M15相互耦接以形成第二電容330的第二電極,而金屬圖案M22、M24、M26相互耦接以形成第二電容330的第一電極。並且,在金屬圖案M31~M36中,金屬圖案M31、M33、M35相互耦接以形成第二電容330的第一電極,而金屬圖案M32、M34、M36相互耦接以形成第二電容330的第二電極。第二電容330為金屬-絕緣層-金屬(MIM)電容。 Fig. 4B is a cross-sectional view showing the capacitor 300 of the integrated circuit in accordance with the line segment A-A' of Fig. 4A. The second capacitor 330 includes a plurality of metal patterns M11 to M36 distributed on different metal layers. The metal patterns M11~M15 are distributed in the topmost metal layer, the metal patterns M21~M26 are distributed in the second metal layer, and the metal patterns M31~M36 are distributed in the bottommost metal layer. In this embodiment, adjacent metal patterns in the same metal layer are physically isolated from each other, and in the metal patterns M11 to M15, the metal patterns M11, M13, and M15 are coupled to each other to form a second The first electrode of the capacitor 330, and the metal patterns M12 and M14 are coupled to each other to form a second electrode of the second capacitor 330. In addition, in the metal patterns M21 to M26, the metal patterns M21, M23, and M15 are coupled to each other to form a second electrode of the second capacitor 330, and the metal patterns M22, M24, and M26 are coupled to each other to form a second capacitor 330. An electrode. Further, in the metal patterns M31 to M36, the metal patterns M31, M33, and M35 are coupled to each other to form a first electrode of the second capacitor 330, and the metal patterns M32, M34, and M36 are coupled to each other to form a second capacitor 330. Two electrodes. The second capacitor 330 is a metal-insulator-metal (MIM) capacitor.

附帶一提的,在圖4B中的多個金屬層中間包括多個絕緣層,並用以隔離各金屬層。 Incidentally, a plurality of insulating layers are included in the plurality of metal layers in FIG. 4B to isolate the metal layers.

當然,圖3實施例的第一電容320利用電晶體電容來建構僅只是一個範例,不用以限縮本發明的範疇。第一電容320也可以利用其他半導體製程中所提供的材質來形成。 Of course, the construction of the first capacitor 320 of the embodiment of FIG. 3 using a transistor capacitor is merely an example and is not intended to limit the scope of the invention. The first capacitor 320 can also be formed using materials provided in other semiconductor processes.

接著請參照圖5,圖5繪示本發明實施例的電晶體電容的一實施方式。電晶體電容500包括基底層510、第一井區520、第二井區530、摻雜區541及542以及多晶矽層550。第一井區520形成在基底層510,第二井區530形成在第一井區520中,摻雜區541、542則形成在第二井區530的兩個不同的區域中以分別形成電晶體的汲極以及源極。多晶矽層550覆蓋在摻雜區541以及542間的區域中以形成電晶體的閘極。 Next, please refer to FIG. 5. FIG. 5 illustrates an embodiment of a transistor capacitor according to an embodiment of the present invention. The transistor capacitor 500 includes a base layer 510, a first well region 520, a second well region 530, doped regions 541 and 542, and a polysilicon layer 550. A first well region 520 is formed in the base layer 510, a second well region 530 is formed in the first well region 520, and doped regions 541, 542 are formed in two different regions of the second well region 530 to respectively form electricity The bungee and source of the crystal. A polysilicon layer 550 is covered in a region between the doping regions 541 and 542 to form a gate of the transistor.

摻雜區541、542相互連接以成為電晶體電容500的第一電極E11,多晶矽層550則為電晶體電容500的第二電極E12。在 本實施方式中,電晶體電容500的第一電極E11以及第二電極E12可以任意的被連接到不同的電壓準位上。 The doped regions 541, 542 are connected to each other to become the first electrode E11 of the transistor capacitor 500, and the polysilicon layer 550 is the second electrode E12 of the transistor capacitor 500. in In this embodiment, the first electrode E11 and the second electrode E12 of the transistor capacitor 500 can be arbitrarily connected to different voltage levels.

在本實施方式中,其中,基底層510可以為P型基底層,第一井區520可以為N型井區,第二井區530可以為P型井區,摻雜區541、542則可以為N型摻雜區。 In this embodiment, the base layer 510 may be a P-type base layer, the first well region 520 may be an N-type well region, the second well region 530 may be a P-type well region, and the doped regions 541 and 542 may be It is an N-type doped region.

請注意,圖5的電晶體電容僅只是一個範例,本發明的第一電容並不限於利用此種電晶體電容來實施。 Please note that the transistor capacitance of FIG. 5 is only an example, and the first capacitor of the present invention is not limited to being implemented by using such a transistor capacitor.

請參照圖6A以及圖6B,圖6A以及圖6B分別繪示本發明再一實施例的積體電路的電容的剖面圖以及等效電路圖。在圖6A以及圖6B中,積體電路的電容600的第一電容620可以利用多個並連的電晶體T1~TN所構成的電晶體電容來實施。其中,電晶體T1~TN的閘極相互連接以形成第一電容620的第二電極,電晶體T1~TN的源極以及汲極相互連接以形成第一電容620的第一電極,並透過第一電極及第二電極與第二電容630並連。 Referring to FIG. 6A and FIG. 6B, FIG. 6A and FIG. 6B are respectively a cross-sectional view and an equivalent circuit diagram of a capacitor of an integrated circuit according to still another embodiment of the present invention. In FIGS. 6A and 6B, the first capacitor 620 of the capacitor 600 of the integrated circuit can be implemented by a transistor capacitor composed of a plurality of parallel transistors T1 to TN. The gates of the transistors T1 T TN are connected to each other to form a second electrode of the first capacitor 620 , and the sources and the drains of the transistors T1 T TN are connected to each other to form a first electrode of the first capacitor 620 and pass through the first electrode. One electrode and the second electrode are connected in parallel with the second capacitor 630.

綜上所述,本發明利用在積體電路相同垂直方向的區域中,利用堆疊的方式形成多個相互並連的電容,有效的在有限的區域內,提升積體電路內電容的電容值。如此一來,可降低積體電路的電容所佔的佈局面積,有效降低產品的成本。 In summary, the present invention utilizes a plurality of mutually parallel capacitors in a stacked manner in the same vertical direction of the integrated circuit to effectively increase the capacitance of the capacitor in the integrated circuit in a limited area. In this way, the layout area occupied by the capacitance of the integrated circuit can be reduced, and the cost of the product can be effectively reduced.

100‧‧‧積體電路的電容 100‧‧‧Capacitance of integrated circuit

110‧‧‧基底層 110‧‧‧ basal layer

120‧‧‧第一電容 120‧‧‧first capacitor

130‧‧‧第二電容 130‧‧‧second capacitor

Claims (7)

一種積體電路的電容,包括:一基底層;一第一電容,配置在該基底層中,其中該第一電容為一電晶體電容,該電晶體電容包括一電晶體,該電晶體具有源極、汲極以及閘極,該電晶體的源極以及汲極相互耦接並成為該第一電容的第一電極,該電晶體的閘極則為該第一電容的第二電極,該電晶體包括:一第一井區,形成在該基底層中;一第二井區,形成在該第一井區中;一第一參雜區,形成在該第二井區中;一第二參雜區,形成在該第二井區中;以及一多晶矽層,覆蓋在該第一參雜區以及該第二參雜區間的區域中,其中,該第一參雜區形成該電晶體的源極,該第二參雜區形成該電晶體的汲極,該多晶矽層形成該電晶體的閘極;以及一第二電容,配置在該第一電容上並至少部份覆蓋該第一電容,其中該第一電容的第一電極耦接至該第二電容的第一電極,且該第一電容的第二電極耦接至該第二電容的第二電極。 A capacitor of an integrated circuit, comprising: a base layer; a first capacitor disposed in the base layer, wherein the first capacitor is a transistor capacitor, the transistor capacitor comprises a transistor, the transistor has a source a pole, a drain, and a gate, wherein a source and a drain of the transistor are coupled to each other and become a first electrode of the first capacitor, and a gate of the transistor is a second electrode of the first capacitor, the electricity The crystal includes: a first well region formed in the base layer; a second well region formed in the first well region; a first doping region formed in the second well region; a second a doping region formed in the second well region; and a polysilicon layer covering the first doping region and the second doping region, wherein the first doping region forms the transistor a source, the second doping region forms a drain of the transistor, the polysilicon layer forms a gate of the transistor; and a second capacitor is disposed on the first capacitor and at least partially covers the first capacitor The first electrode of the first capacitor is coupled to the first electrode of the second capacitor And a second electrode of the first capacitor coupled to the second electrode of the second capacitor. 如申請專利範圍第1項所述之積體電路的電容,其中該基底層為P型基底層,該第一井區為N型井區,該第二井區為P型 井區,該第一及該第二參雜區為N型參雜區。 The capacitor of the integrated circuit according to claim 1, wherein the base layer is a P-type base layer, the first well region is an N-type well region, and the second well region is a P-type In the well region, the first and the second doping regions are N-type doping regions. 如申請專利範圍第1項所述之積體電路的電容,其中當該電晶體電容包括的該至少一電晶體的數量為多個時,各該電晶體具有源極、汲極以及閘極,該些電晶體的源極以及汲極相互耦接以形成該第一電容的第一電極,該些電晶體的閘極相互耦接以形成該第一電容的第二電極。 The capacitor of the integrated circuit of claim 1, wherein when the number of the at least one transistor included in the transistor capacitor is plural, each of the transistors has a source, a drain, and a gate. The sources and the drains of the transistors are coupled to each other to form a first electrode of the first capacitor, and the gates of the transistors are coupled to each other to form a second electrode of the first capacitor. 如申請專利範圍第1項所述之積體電路的電容,其中該第二電容為金屬-絕緣層-金屬電容。 The capacitor of the integrated circuit of claim 1, wherein the second capacitor is a metal-insulator-metal capacitor. 如申請專利範圍第4所述之積體電路的電容,其中該第二電容包括:多數個金屬層,各該金屬層具有多數個金屬圖案,該些金屬圖案的多數個第一部份金屬圖案相互耦接以形成該第二電容的第一電極,該金屬圖案的多數個第二部份金屬圖案相互耦接以形成該第二電容的第一電極。 The capacitor of the integrated circuit of claim 4, wherein the second capacitor comprises: a plurality of metal layers, each of the metal layers having a plurality of metal patterns, and a plurality of first partial metal patterns of the metal patterns The first electrodes are coupled to each other to form the second capacitor, and the plurality of second partial metal patterns of the metal pattern are coupled to each other to form a first electrode of the second capacitor. 如申請專利範圍第5所述之積體電路的電容,其中該第二電容更包括:多數個絕緣層,各該絕緣層配置在該些金屬層中相鄰的二金屬層間。 The capacitor of the integrated circuit of claim 5, wherein the second capacitor further comprises: a plurality of insulating layers, each of the insulating layers being disposed between adjacent two metal layers of the metal layers. 如申請專利範圍第5所述之積體電路的電容,其中各該金屬層中的相鄰的金屬圖案彼此相互物理性隔離。 The capacitor of the integrated circuit of claim 5, wherein adjacent metal patterns in each of the metal layers are physically isolated from each other.
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