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TWI521655B - High frequency module and high frequency module carrying device - Google Patents

High frequency module and high frequency module carrying device Download PDF

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Publication number
TWI521655B
TWI521655B TW102126186A TW102126186A TWI521655B TW I521655 B TWI521655 B TW I521655B TW 102126186 A TW102126186 A TW 102126186A TW 102126186 A TW102126186 A TW 102126186A TW I521655 B TWI521655 B TW I521655B
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Taiwan
Prior art keywords
semiconductor substrate
main surface
module
substrate
connection terminal
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TW102126186A
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Chinese (zh)
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TW201409630A (en
Inventor
野村忠志
高木陽一
小川伸明
鎌田明彥
西田憲正
松本充弘
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村田製作所股份有限公司
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Classifications

    • H10W74/117
    • H10W40/10
    • H10W40/228
    • H10W74/012
    • H10W74/014
    • H10W74/15
    • H10W90/701
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H10W90/724
    • H10W90/734

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

高頻模組及高頻模組搭載裝置 High frequency module and high frequency module mounting device

本發明係關於一種在配線基板之一主面配置有半導體基板之模組及搭載有此模組之模組搭載裝置。 The present invention relates to a module in which a semiconductor substrate is disposed on one main surface of a wiring substrate, and a module mounting device on which the module is mounted.

近年來,隨著行動電話等行動終端裝置之小型、薄型化,要求搭載於此之模組之小型化。因此,在以往,如圖4所示,提案有具備在構成模組100之配線基板101之一主面上以面朝下構裝(覆晶構裝)之半導體基板102、與該半導體基板102配置在同一主面上之柱狀之連接端子103、及被覆半導體基板102及柱狀之連接端子103之樹脂層104之模組(專利文獻1)。 In recent years, with the miniaturization and thinning of mobile terminal devices such as mobile phones, it is required to miniaturize the modules mounted thereon. Therefore, as shown in FIG. 4, a semiconductor substrate 102 having a face-down configuration (flip-chip mounting) on one main surface of the wiring substrate 101 constituting the module 100 is proposed, and the semiconductor substrate 102 is provided. A columnar connection terminal 103 disposed on the same main surface, and a module covering the resin substrate 104 of the semiconductor substrate 102 and the columnar connection terminal 103 (Patent Document 1).

此情形,在模組100之一主面上形成有柱狀之連接端子103後,覆晶構裝半導體基板102,接著,形成被覆該半導體基板102及連接端子103之樹脂層104。接著,以連接端子103與半導體基板102之端面從樹脂層104表面露出之方式,研磨樹脂層104與半導體基板102之上面而形成模組100。 In this case, after the columnar connection terminals 103 are formed on one main surface of the module 100, the semiconductor substrate 102 is flip-chip mounted, and then the resin layer 104 covering the semiconductor substrate 102 and the connection terminals 103 is formed. Next, the resin layer 104 and the upper surface of the semiconductor substrate 102 are polished so that the connection terminal 103 and the end surface of the semiconductor substrate 102 are exposed from the surface of the resin layer 104, and the module 100 is formed.

覆晶構裝之半導體基板102,在與配線基板101之對向面形成有電路,藉由研磨半導體基板102之上面(與配線基板之非對向主面),不改變半導體基板102之特性即可使模組100之高度變低,因此藉由研磨樹脂層104及半導體基板102直到連接端子103之端面露出為止,可使模組100 之高度變低。又,熱傳導率較樹脂層104之樹脂高之半導體基板102之上面從樹脂層104之表面露出,因此模組100之散熱特性亦提升。 The semiconductor substrate 102 having the flip chip structure is formed with a circuit on the opposite surface of the wiring substrate 101, and the upper surface of the semiconductor substrate 102 (with respect to the non-opposing main surface of the wiring substrate) is polished, and the characteristics of the semiconductor substrate 102 are not changed. The height of the module 100 can be lowered. Therefore, the module 100 can be formed by polishing the resin layer 104 and the semiconductor substrate 102 until the end faces of the connection terminals 103 are exposed. The height is lower. Further, since the upper surface of the semiconductor substrate 102 having a higher thermal conductivity than the resin of the resin layer 104 is exposed from the surface of the resin layer 104, the heat dissipation characteristics of the module 100 are also improved.

專利文獻1:日本特開2002-343904號(參照段落0013、圖1等) Patent Document 1: JP-A-2002-343904 (refer to paragraph 0013, FIG. 1 and the like)

然而,在上述習知技術,由於半導體基板102之上面從樹脂層104露出,因此與半導體基板102之上面被樹脂層104覆蓋之模組相較,模組之散熱特性提升,但在構裝發熱性高之半導體基板(例如,在高頻模組等使用之功率放大器IC等)之情形,會有散熱不足、半導體基板102產生誤動作等缺陷之虞,因此要求模組100之散熱特性之進一步提升。 However, in the above-described conventional technique, since the upper surface of the semiconductor substrate 102 is exposed from the resin layer 104, the heat dissipation characteristics of the module are improved as compared with the module in which the upper surface of the semiconductor substrate 102 is covered by the resin layer 104, but the heat is generated in the package. In the case of a high-performance semiconductor substrate (for example, a power amplifier IC used in a high-frequency module or the like), there are defects such as insufficient heat dissipation and malfunction of the semiconductor substrate 102. Therefore, the heat dissipation characteristics of the module 100 are required to be further improved.

本發明係有鑑於上述問題而構成,其目的在於提供一種散熱特性優異之模組及搭載有此模組之模組搭載裝置。 The present invention has been made in view of the above problems, and an object thereof is to provide a module having excellent heat dissipation characteristics and a module mounting device equipped with the module.

為了達成上述目的,本發明之模組,具備:配線基板;半導體基板,構裝在該配線基板之一主面;以及樹脂層,以該半導體基板之未與該配線基板對向側之非對向主面露出之方式被覆該半導體基板,形成在該一主面;在該半導體基板之該非對向主面之至少一部分形成有金屬膜。 In order to achieve the above object, a module of the present invention includes: a wiring substrate; a semiconductor substrate mounted on one main surface of the wiring substrate; and a resin layer, wherein the semiconductor substrate is not opposite to the wiring substrate The semiconductor substrate is coated on the main surface to be formed on the main surface, and a metal film is formed on at least a portion of the non-opposing main surface of the semiconductor substrate.

藉由以上述方式構成,由於能透過熱傳導率較半導體基板高之金屬膜使從模組產生之熱散熱,因此與半導體基板之未與配線基板對向之非對向主面從樹脂層露出之習知模組相較,可提升模組之散熱特性。 According to the above configuration, since the heat generated from the module is dissipated by the metal film having a higher thermal conductivity than the semiconductor substrate, the non-opposing main surface of the semiconductor substrate that is not opposed to the wiring substrate is exposed from the resin layer. Compared with the conventional module, the heat dissipation characteristics of the module can be improved.

又,藉由在半導體基板之未與配線基板對向側之非對向主面之至少一部分形成具有延展性之金屬膜,保護從樹脂層露出之半導體基板之該非對向主面,可抑制半導體基板因來自外部之衝擊等而破損。 Further, by forming a metal film having a ductility on at least a part of the non-opposing main surface on the opposite side of the wiring substrate from the semiconductor substrate, the non-opposing main surface of the semiconductor substrate exposed from the resin layer is protected, and the semiconductor can be suppressed. The substrate is damaged by an impact or the like from the outside.

又,在該金屬膜之表面形成有凹凸亦可。如此,由於從樹脂層之表面露出之金屬膜之表面積增加,因此模組之散熱特性進一步提升。 Further, irregularities may be formed on the surface of the metal film. Thus, since the surface area of the metal film exposed from the surface of the resin layer is increased, the heat dissipation characteristics of the module are further improved.

又,該金屬膜係藉由鍍敷形成亦可。藉由以上述方式構成,能藉由鍍敷形成金屬膜。 Further, the metal film may be formed by plating. By configuring in the above manner, a metal film can be formed by plating.

又,進一步具備豎設在該一主面之柱狀之連接端子;該連接端子之前端面從該樹脂層之表面露出亦可。藉由以上述方式構成,由於熱傳導率較樹脂層高之連接端子之前端面亦從樹脂層露出,因此模組之散熱特性進一步提升。又,藉由連接端子可連接外部之母基板等與模組。 Further, a columnar connection terminal vertically provided on the one main surface is provided; and the front end surface of the connection terminal may be exposed from the surface of the resin layer. According to the above configuration, since the front end surface of the connection terminal having a higher thermal conductivity than the resin layer is also exposed from the resin layer, the heat dissipation characteristics of the module are further improved. Moreover, the external mother substrate or the like can be connected to the module by the connection terminal.

又,本發明之模組搭載裝置,具備:上述模組;以及母基板,與該模組之該金屬膜連接。藉由以上述方式構成,可提供搭載有散熱特性優異之模組之模組搭載基板。 Further, the module mounting device of the present invention includes: the module; and a mother substrate connected to the metal film of the module. According to the above configuration, it is possible to provide a module mounting substrate on which a module having excellent heat dissipation characteristics is mounted.

又,例如,在配線基板之一主面配置半導體基板與連接端子之模組構成之情形,藉由將半導體基板之金屬膜利用於與母基板之連接,能在連接端子與半導體基板之金屬膜之兩方進行模組與母基板之連接,因此與僅以連接端子與母基板連接之習知模組相較,模組與母基板之連接強度增加。 Further, for example, when a module structure of a semiconductor substrate and a connection terminal is disposed on one main surface of the wiring substrate, the metal film of the semiconductor substrate can be used for connection to the mother substrate, and the metal film of the connection terminal and the semiconductor substrate can be used. Since the two modules are connected to the mother substrate, the connection strength between the module and the mother substrate is increased as compared with the conventional module in which only the connection terminal is connected to the mother substrate.

又,若在金屬膜之表面形成有凹凸,則將模組與母基板加以連接時之模組與母基板之連接面積增加,因此模組與母基板之連接強度增加。 Further, when irregularities are formed on the surface of the metal film, the connection area between the module and the mother substrate when the module is connected to the mother substrate is increased, so that the connection strength between the module and the mother substrate is increased.

又,該模組之該金屬膜與形成在該母基板之接地用之接地電極連接亦可。藉由以上述方式構成,以半導體基板之未與配線基板對向側之非對向主面與母基板對向之方式將金屬膜(模組)與母基板加以連接之情 形,與半導體基板之該非對向主面被樹脂覆蓋之習知模組相較,半導體基板與母基板之接地電極之距離變近,因此接地電極造成之半導體基板之屏蔽特性提升。再者,若半導體基板與接地電極之距離變近,則從模組產生之熱易於透過母基板之接地電極散熱,因此模組之散熱特性亦提升。 Further, the metal film of the module may be connected to a ground electrode formed on the ground of the mother substrate. According to the above configuration, the metal film (module) and the mother substrate are connected so that the non-opposing main surface of the semiconductor substrate opposite to the wiring substrate faces the mother substrate. The shape of the semiconductor substrate is closer to the ground electrode of the mother substrate than the conventional module in which the non-opposing main surface of the semiconductor substrate is covered with the resin. Therefore, the shielding property of the semiconductor substrate caused by the ground electrode is improved. Furthermore, if the distance between the semiconductor substrate and the ground electrode is close, the heat generated from the module is easily dissipated through the ground electrode of the mother substrate, so that the heat dissipation characteristics of the module are also improved.

根據本發明,以構裝在配線基板之一主面之半導體基板之未與配線基板對向側之非對向主面露出之方式形成被覆半導體基板之樹脂層,在露出之半導體基板之該非對向主面之至少一部分形成熱傳導率較半導體基板高之金屬膜,藉此,與半導體基板之該非對向主面從樹脂層露出之習知模組相較,可謀求提升模組之散熱特性。 According to the present invention, the resin layer covering the semiconductor substrate is formed such that the semiconductor substrate that is mounted on one of the main surfaces of the wiring substrate is not exposed to the opposite main surface of the wiring substrate, and the non-pair of the exposed semiconductor substrate A metal film having a higher thermal conductivity than the semiconductor substrate is formed on at least a portion of the main surface, whereby the heat dissipation characteristics of the module can be improved as compared with the conventional module in which the non-opposing main surface of the semiconductor substrate is exposed from the resin layer.

1‧‧‧模組搭載裝置 1‧‧‧Modular carrying device

2‧‧‧模組 2‧‧‧ modules

3‧‧‧母基板 3‧‧‧ mother substrate

5‧‧‧接地電極 5‧‧‧Ground electrode

8‧‧‧連接端子 8‧‧‧Connecting terminal

9‧‧‧半導體基板 9‧‧‧Semiconductor substrate

10‧‧‧金屬膜 10‧‧‧Metal film

11‧‧‧配線基板 11‧‧‧Wiring substrate

13a,13b‧‧‧樹脂層 13a, 13b‧‧‧ resin layer

圖1係構裝有本發明一實施形態之模組之模組搭載裝置之剖斷前視圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional front view showing a module mounting device incorporating a module according to an embodiment of the present invention.

圖2(a)~(c)係圖1之模組之製造方法之說明圖。 2(a) to (c) are explanatory views of a method of manufacturing the module of Fig. 1.

圖3(a)、(b)係圖1之模組之製造方法之說明圖。 3(a) and 3(b) are explanatory views showing a method of manufacturing the module of Fig. 1.

圖4係習知模組之剖面圖。 Figure 4 is a cross-sectional view of a conventional module.

(模組搭載裝置之構成) (Composition of module mounting device)

參照圖1說明搭載有本發明一實施形態之模組2之模組搭載裝置1。此外,圖1係搭載有模組2之模組搭載裝置1之剖斷前視圖。 A module mounting device 1 on which a module 2 according to an embodiment of the present invention is mounted will be described with reference to Fig. 1 . In addition, FIG. 1 is a cutaway front view of the module mounting device 1 on which the module 2 is mounted.

搭載有本實施形態之模組2之模組搭載裝置1,如圖1所示,具備母基板3、構裝在該母基板3之模組2、及用以保護母基板3與模組2之連接部之由樹脂形成之底填樹脂層4,搭載於例如行動電話等使用高頻之 電子機器。 As shown in FIG. 1 , the module mounting device 1 equipped with the module 2 of the present embodiment includes a mother substrate 3 , a module 2 mounted on the mother substrate 3 , and a mother substrate 3 and a module 2 . The underfill resin layer 4 formed of a resin in the connection portion is mounted on a mobile phone or the like using a high frequency. Electronic machine.

母基板3,在內部形成有接地用之接地電極5與構成各種電路之配線圖案(未圖示),接地電極5及配線圖案係藉由通孔導體6等連接於既定配線圖案或形成在母基板3之表面背面之構裝用電極7等。本實施形態中,形成在母基板3之接地電極5係透過通孔導體6連接於構裝電極7,該構裝電極7係連接於形成在後述模組2之柱狀之連接端子8及半導體基板9之未與配線基板對向側之非對向主面9a之金屬膜10。又,母基板3由玻璃環氧樹脂、陶瓷等材料形成。此外,接連端子8未必要連接於接地電極5,例如,使圖1所示之二個連接端子8中之僅單側透過通孔導體6與接地電極5連接亦可。 The mother substrate 3 is internally formed with a grounding electrode 5 for grounding and a wiring pattern (not shown) constituting various circuits, and the ground electrode 5 and the wiring pattern are connected to a predetermined wiring pattern or formed in the mother via the via hole conductor 6 or the like. The electrode 7 for mounting on the front and back surfaces of the substrate 3 or the like. In the present embodiment, the ground electrode 5 formed on the mother substrate 3 is connected to the package electrode 7 through the via hole conductor 6, and the structure electrode 7 is connected to the columnar connection terminal 8 and the semiconductor substrate formed in the module 2 to be described later. The metal film 10 of the non-opposing main surface 9a which is not opposite to the wiring substrate. Further, the mother substrate 3 is formed of a material such as glass epoxy resin or ceramic. Further, the connection terminal 8 is not necessarily connected to the ground electrode 5. For example, only one of the two connection terminals 8 shown in FIG. 1 may be connected to the ground electrode 5 via the via hole conductor 6.

又,底填樹脂層4由例如環氧樹脂構成,以將在母基板3上構裝有模組2時之母基板3與模組2之間之間隙填埋之方式填充樹脂而形成。此外,無底填樹脂層4亦可。 Further, the underfill resin layer 4 is made of, for example, an epoxy resin, and is formed by filling a resin so as to fill a gap between the mother substrate 3 and the module 2 when the module 2 is mounted on the mother substrate 3. Further, the bottomless resin layer 4 may also be used.

(模組2之構成) (Composition of Module 2)

接著,參照圖1說明本實施形態之模組2。 Next, the module 2 of this embodiment will be described with reference to Fig. 1 .

模組2,如圖1所示,係具備配線基板11、構裝在該配線基板11之一主面11a之半導體基板9及豎設之柱狀之連接端子8、構裝在配線基板11之另一主面11b之晶片零件12a,12b,12c、被覆配線基板11之一主面11a之半導體基板9與連接端子8之樹脂層13a、被覆配線基板11之另一主面11b之晶片零件12a~12c之樹脂層13b之模組,作為其例,可舉出Bluetooth(註冊商標)模組、無線LAN模組、配置在行動電話之緊鄰天線下方之天線開關模組等。 As shown in FIG. 1, the module 2 includes a wiring board 11, a semiconductor substrate 9 that is mounted on one main surface 11a of the wiring board 11, and a columnar connection terminal 8 that is vertically disposed, and is mounted on the wiring board 11. The wafer part 12a, 12b, 12c of the other main surface 11b, the semiconductor substrate 9 of the main surface 11a of the wiring substrate 11 and the resin layer 13a of the connection terminal 8, and the wafer part 12a of the other main surface 11b of the covered wiring board 11 The module of the resin layer 13b of the ~12c is exemplified by a Bluetooth (registered trademark) module, a wireless LAN module, and an antenna switch module disposed under the antenna immediately adjacent to the mobile phone.

配線基板11由玻璃環氧樹脂基板、低溫同時燒成陶瓷(LTCC)基板、玻璃基板等形成,在其兩主面11a,11b形成構裝用電極15、連接端子8形成用之電極15a、配線圖案(未圖示)等,且在內部形成接地用之接地電極14、其他配線圖案(未圖示)、通孔導體(未圖示)等。此外,配線基板11使用單層基板及多層基板之任一者皆可。 The wiring board 11 is formed of a glass epoxy resin substrate, a low temperature simultaneous firing ceramic (LTCC) substrate, a glass substrate, or the like, and the electrode 15 for forming, the electrode 15a for forming the connection terminal 8, and the wiring are formed on the both main surfaces 11a and 11b. A ground electrode 14 for grounding, another wiring pattern (not shown), a via conductor (not shown), and the like are formed inside the pattern (not shown) or the like. Further, the wiring board 11 may be either a single layer substrate or a multilayer substrate.

例如,配線基板11為LTCC多層基板之情形之製造方法,形成氧化鋁及玻璃等之混合粉末與有機結合劑及溶劑等一起混合後之漿料片化後之陶瓷坯片,在此陶瓷坯片之既定位置藉由雷射加工等形成通孔,將含有Ag或Cu等之導體糊填充於已形成之通孔,形成層間連接用之通孔導體,藉由使用導體糊之印刷形成各種電極圖案。之後,藉由將各陶瓷坯片積層、壓接形成陶瓷積層體,在約1000℃前後之低溫進行燒成、所謂低溫燒成而製造。 For example, in the case where the wiring substrate 11 is a LTCC multilayer substrate, a ceramic green sheet obtained by mixing a mixed powder of alumina, glass, or the like with an organic binder and a solvent, and the like, is formed. A through hole is formed by laser processing or the like, and a conductor paste containing Ag or Cu is filled in the formed via hole to form a via hole conductor for interlayer connection, and various electrode patterns are formed by printing using a conductor paste. . Thereafter, each ceramic green sheet is laminated and pressure-bonded to form a ceramic laminate, which is produced by firing at a low temperature of about 1000 ° C and so-called low-temperature firing.

又,在配線基板11之兩主面11a,11b,作為構裝零件,構裝半導體基板9與晶片零件12a~12c。半導體基板9,藉由在與配線基板11之一主面11a對向之表面形成既定電路,構成例如處理RF訊號或基頻訊號之系統IC,面朝下構裝(覆晶構裝)於配線基板11之一主面11a。又,晶片零件12a~12c由晶片電容器、晶片電感器、晶片電阻構成,藉由周知之表面構裝技術構裝在配線基板11之另一主面11b。又,在配線基板11之一主面11a進一步構裝柱狀(銷狀)之連接端子8。此外,連接端子8以例如Cu為主成分,透過焊料構裝在電極15a。 Further, on both main surfaces 11a and 11b of the wiring board 11, the semiconductor substrate 9 and the wafer components 12a to 12c are mounted as a component. The semiconductor substrate 9 is formed with a predetermined circuit on the surface facing the main surface 11a of the wiring substrate 11, and is configured, for example, to form a system IC for processing an RF signal or a fundamental signal, and to face down (flip-chip) for wiring. One of the main faces 11a of the substrate 11. Further, the wafer components 12a to 12c are composed of a wafer capacitor, a chip inductor, and a chip resistor, and are mounted on the other main surface 11b of the wiring substrate 11 by a known surface mounting technique. Further, a columnar (pin-shaped) connection terminal 8 is further formed on one main surface 11a of the wiring board 11. Further, the connection terminal 8 is made of, for example, Cu as a main component, and is soldered to the electrode 15a.

此情形,在配線基板11之一主面11a僅配置面朝下構裝之半導體基板9與連接端子8,在配線基板11之另一主面11b配置半導體基 板9以外之其他構裝零件(晶片零件12a~12c)。又,在半導體基板9之非對向主面9a與連接端子8之前端面8a形成金屬膜10。此金屬膜10為例如藉由鍍敷處理在半導體基板9之非對向主面9a(或連接端子8之前端面8a)形成Ni層且從該Ni層之上形成有Au層之Ni/Au膜。此外,為在連接端子8之前端面8a未形成金屬膜10之構成亦可。 In this case, only the semiconductor substrate 9 and the connection terminal 8 which face down are disposed on one main surface 11a of the wiring substrate 11, and the semiconductor base is disposed on the other main surface 11b of the wiring substrate 11. Other components (wafer parts 12a to 12c) other than the board 9. Further, the metal film 10 is formed on the end surface 8a of the non-opposing main surface 9a of the semiconductor substrate 9 and the connection terminal 8. This metal film 10 is, for example, a Ni/Au film in which an Au layer is formed on the non-opposing main surface 9a of the semiconductor substrate 9 (or the front end surface 8a of the connection terminal 8) by a plating process, and an Au layer is formed from the Ni layer. . Further, the metal film 10 may not be formed on the end surface 8a before the connection terminal 8.

又,在構裝在配線基板11之另一主面11b之晶片零件12a~12c之中,在分別被構裝之狀態下,有離配線基板11之另一主面11b之高度不同者,本實施形態中,如圖1所示,晶片零件12a在所有晶片零件12a~12c之中離配線基板11之另一主面11b之高度最低。又,半導體基板9與連接端子8分別在構裝或豎設之狀態下,形成為離配線基板11之一主面11a之高度相同。 Further, in the wafer components 12a to 12c which are mounted on the other main surface 11b of the wiring board 11, in the state in which they are respectively mounted, the height of the other main surface 11b of the wiring board 11 is different. In the embodiment, as shown in FIG. 1, the wafer component 12a has the lowest height from the other main surface 11b of the wiring substrate 11 among all the wafer components 12a to 12c. Further, the semiconductor substrate 9 and the connection terminal 8 are formed to have the same height from one main surface 11a of the wiring substrate 11 in a state of being mounted or erected.

再者,在配線基板11之一主面11a,以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較配線基板11之另一主面11b之晶片零件12a(在另一主面11b高度最低之晶片零件)離該另一主面11b之高度H0低之方式形成有半導體基板9(或連接端子8)。 Further, in one main surface 11a of the wiring substrate 11, the height Ht of the semiconductor substrate 9 (or the connection terminal 8) having the highest height from one main surface 11a of the wiring substrate 11 is smaller than the other main surface 11b of the wiring substrate 11. Part wafer 12a (11b the height of the lowest part on the other main surface of the wafer) from a low height H 0 of the mode of the other main surface 11b of the semiconductor substrate 9 is formed (connection terminal 8).

又,使用分別俯視各構裝零件9,12a~12c之情形,半導體基板9較其他構裝零件(各晶片零件12a~12c)之任一者面積(橫剖面積)皆較大者。 Further, in the case where the respective components 9 and 12a to 12c are viewed in plan, the semiconductor substrate 9 has a larger area (cross-sectional area) than any of the other components (the respective wafer components 12a to 12c).

配線基板11之一主面11a之樹脂層13a由例如環氧樹脂構成,如圖1所示,以半導體基板9之非對向主面及連接端子8之前端面8a分別露出之方式,被覆半導體基板9及連接端子8而形成。此時,模組2之配線基板11之一主面側形成為樹脂層13a表面、半導體基板9之非對向 主面9a、及連接端子8之前端面8a構成同一面之所謂面高相同狀態。此外,此面高相同狀態可藉由後述研磨、研削步驟形成。 The resin layer 13a of one main surface 11a of the wiring board 11 is made of, for example, an epoxy resin, and as shown in FIG. 1, the semiconductor substrate is covered so that the non-opposing main surface of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 are respectively exposed. 9 and formed by connecting the terminals 8. At this time, one main surface side of the wiring substrate 11 of the module 2 is formed as a surface of the resin layer 13a and a non-alignment of the semiconductor substrate 9. The main surface 9a and the front end surface 8a of the connection terminal 8 constitute the same state of the so-called surface height. Further, the state in which the surface height is the same can be formed by a polishing and grinding step which will be described later.

配線基板11之另一主面11b之樹脂層13b由例如與一主面11a之樹脂層13a同種之環氧樹脂構成,如圖1所示,以各晶片零件12a~12c不露出之方式在被覆各晶片零件全部之狀態下形成。 The resin layer 13b of the other main surface 11b of the wiring board 11 is made of, for example, the same type of epoxy resin as the resin layer 13a of the main surface 11a, and is covered as shown in Fig. 1 so that the wafer parts 12a to 12c are not exposed. Each wafer component is formed in all states.

此外,在樹脂層13b側之厚度相對於樹脂層13a側之厚度充分厚之情形等,模組2之彎曲較大時,為了抑制該彎曲,較佳為,形成樹脂層13b之樹脂係使用線膨脹係數較形成樹脂層13a之樹脂小者。 Further, when the thickness of the resin layer 13b side is sufficiently thick with respect to the thickness of the resin layer 13a side or the like, when the bending of the module 2 is large, in order to suppress the bending, it is preferable to form the resin-based use line of the resin layer 13b. The coefficient of expansion is smaller than that of the resin forming the resin layer 13a.

(模組2之製造方法) (Manufacturing method of module 2)

接著,參照圖2及圖3說明本實施形態之模組2之製造方法。此外,圖2係顯示製造模組2之各步驟之一部分,圖3係顯示接續圖2之各步驟。 Next, a method of manufacturing the module 2 of the present embodiment will be described with reference to Figs. 2 and 3 . In addition, FIG. 2 shows a part of each step of the manufacturing module 2, and FIG. 3 shows the steps of the subsequent FIG.

首先,如圖2(a)所示,準備配線基板11,該配線基板11,在其內部形成面狀之接地用接地電極14與配線圖案,且在其兩主面11a,11b形成有半導體基板9與各晶片零件12a~12c之構裝用電極15及連接端子形成用之電極15a(配線基板準備步驟)。 First, as shown in FIG. 2(a), a wiring board 11 is prepared in which a planar grounding ground electrode 14 and a wiring pattern are formed, and a semiconductor substrate is formed on both main surfaces 11a, 11b. 9 and the electrode 15 for forming the respective wafer parts 12a to 12c and the electrode 15a for forming a connection terminal (wiring substrate preparation step).

接著,如圖2(b)所示,在配線基板11之構裝用電極15分別對應之位置構裝半導體基板9、連接端子8及各晶片零件12a~12c(零件、連接端子構裝步驟)。此時,將半導體基板9面朝下構裝(覆晶構裝)在配線基板11之一主面11a,將各晶片零件12a~12c藉由周知之表面構裝技術構裝在配線基板11之另一主面11b。又,在配線基板11之連接端子形成用之電極15透過焊料構裝銷狀之連接端子8。作為連接端子8,可使用例如Cu或由以Cu為主成分之合金構成之柱狀之金屬。 Next, as shown in FIG. 2(b), the semiconductor substrate 9, the connection terminal 8, and each of the wafer components 12a to 12c are mounted at positions corresponding to the electrode 15 for the wiring substrate 11 (parts and connection terminal mounting steps). . At this time, the semiconductor substrate 9 is placed face down on the main surface 11a of the wiring substrate 11, and the wafer components 12a to 12c are mounted on the wiring substrate 11 by a known surface mounting technique. The other main face 11b. Moreover, the electrode 15 for forming the connection terminal of the wiring substrate 11 is transmitted through the solder-connected pin-shaped connection terminal 8. As the connection terminal 8, for example, Cu or a columnar metal composed of an alloy containing Cu as a main component can be used.

接著,如圖2(c)所示,在配線基板11之一主面11a,形成被覆半導體基板9及連接端子8之樹脂層13a,且在另一主面11b形成被覆各晶片零件12a~12c之樹脂層13b(樹脂層形成步驟)。此時,使用分配方式或印刷方式等在兩主面11a,11b上塗布或印刷樹脂,放入設定成既定硬化溫度(例如,若為環氧樹脂則為180℃程度)之烤爐,使樹脂硬化而形成兩樹脂層13a,13b。接著,形成藉由樹脂被覆配置在配線基板11之兩主面11a,11b之各構裝零件(9,12a~12c)及連接端子8而成之模組坯體18。 Next, as shown in FIG. 2(c), the resin layer 13a covering the semiconductor substrate 9 and the connection terminal 8 is formed on one main surface 11a of the wiring substrate 11, and the respective wafer parts 12a to 12c are formed on the other main surface 11b. The resin layer 13b (resin layer forming step). At this time, the resin is applied or printed on the both main surfaces 11a and 11b by a distribution method or a printing method, and an oven set to a predetermined curing temperature (for example, 180 ° C in the case of an epoxy resin) is placed in the oven to make the resin. The two resin layers 13a, 13b are formed by hardening. Next, a module blank 18 in which the respective components (9, 12a to 12c) and the connection terminals 8 which are disposed on the both main faces 11a and 11b of the wiring substrate 11 are covered with a resin is formed.

此外,連接端子8之形成方法除了上述方法外,在配線基板11之一主面11a構裝半導體基板9前,藉由鍍敷處理形成柱狀之連接端子8亦可。此情形,在連接端子8形成後構裝半導體基板9,藉由樹脂被覆構裝在一主面11a上之半導體基板9及連接端子8而形成樹脂層13a即可。 Further, in addition to the above method, the connection terminal 8 may be formed by forming a columnar connection terminal 8 by a plating process before the semiconductor substrate 9 is mounted on one main surface 11a of the wiring substrate 11. In this case, the semiconductor substrate 9 is formed after the connection terminal 8 is formed, and the resin layer 13a is formed by coating the semiconductor substrate 9 and the connection terminal 8 on the main surface 11a with a resin.

又,在構裝半導體基板9後、形成連接端子8前,形成樹脂層13a,藉由對樹脂層13a之表面照射雷射等,以連接端子形成用電極15a之表面露出之方式形成連接端子形成用之凹部,使用印刷技術對該凹部填充導電糊(例如,Ag糊或Cu糊)、或藉由鍍敷處理等形成導體(例如,Cu)、或在配線基板11之一主面11a形成柱狀之連接端子8亦可。 In addition, after the semiconductor substrate 9 is formed, the resin layer 13a is formed, and the surface of the resin layer 13a is irradiated with a laser or the like, and the surface of the connection terminal forming electrode 15a is exposed to form a connection terminal. The concave portion is filled with a conductive paste (for example, an Ag paste or a Cu paste) by using a printing technique, or a conductor (for example, Cu) is formed by a plating treatment or the like, or a pillar is formed on one main surface 11a of the wiring substrate 11. The connection terminal 8 of the shape may also be used.

在以鍍敷處理形成連接端子8之情形,與構裝上述銷狀之連接端子8之情形不同,即使研磨或研削連接端子8,配線基板11與連接端子8之接合部之焊料亦不會濕潤連接端子8之側面而從樹脂層13a露出。是以,能在配線基板11之一主面11a上高精度地形成細微徑之連接端子8,能使連接端子8狹間距化。 In the case where the connection terminal 8 is formed by plating treatment, unlike the case where the pin-shaped connection terminal 8 is configured, even if the connection terminal 8 is ground or ground, the solder of the joint portion of the wiring substrate 11 and the connection terminal 8 is not wetted. The side surface of the terminal 8 is connected and exposed from the resin layer 13a. Therefore, the connection terminals 8 having the fine diameter can be formed on the main surface 11a of one of the wiring boards 11 with high precision, and the connection terminals 8 can be narrowed.

接著,如圖3(a)所示,以半導體基板9之非對向主面9a與 連接端子8之前端面8a從樹脂層13a表面露出之方式,研磨或研削模組坯體18之樹脂層13a表面(研磨/研削步驟)。例如,研磨樹脂層13a表面之情形,該研磨可藉由使用杯狀磨石之研磨、使用游離磨粒之拋光研磨、噴砂等進行。 Next, as shown in FIG. 3(a), the non-opposing main surface 9a of the semiconductor substrate 9 is used. The surface of the resin layer 13a of the module blank 18 is polished or ground (the grinding/grinding step) so that the front end surface 8a of the connection terminal 8 is exposed from the surface of the resin layer 13a. For example, in the case of polishing the surface of the resin layer 13a, the polishing can be carried out by grinding using a cup-shaped grindstone, polishing using a free abrasive grain, sand blasting or the like.

此時,在模組坯體18之配線基板11之一主面側,以樹脂層13a表面、半導體基板9之非對向主面9a、及連接端子8之前端面8a構成同一面之所謂面高相同狀態之方式,與樹脂層13a之樹脂一起研磨或研削半導體基板9及連接端子8。 At this time, on the main surface side of the wiring board 11 of the module blank 18, the so-called surface height of the surface of the resin layer 13a, the non-opposing main surface 9a of the semiconductor substrate 9, and the front end surface 8a of the connection terminal 8 constitute the same surface. In the same state, the semiconductor substrate 9 and the connection terminal 8 are ground or ground together with the resin of the resin layer 13a.

又,以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較離配線基板11之另一主面11b之高度最低之晶片零件12a之高度H0低之方式,研磨或研削半導體基板9(或連接端子8)。 Further, the height Ht to one of the wiring board 11 from the main surface of the semiconductor substrate 9 of the maximum height (or terminals 8) of the lowest 11a of the wiring board than from the other main surface 11 of the part 11b of the wafer height of the height H 0 12a In a low manner, the semiconductor substrate 9 (or the connection terminal 8) is ground or ground.

此外,較佳為,以在半導體基板9之非對向主面9a形成凹凸之方式進行研磨或研削。若在半導體基板9之非對向主面9a形成凹凸,則在該主面9a形成有金屬膜10時,亦可在該金屬膜10形成凹凸,能使熱傳導率高之金屬膜10之表面積增加。又,在要求配線基板11之一主面11a側之平坦度之模組2,藉由以填埋半導體基板9之非對向主面9a之凹凸之方式將金屬膜10形成較厚,能使金屬膜10之表面平坦。 Further, it is preferable to perform polishing or grinding so as to form irregularities on the non-opposing main surface 9a of the semiconductor substrate 9. When the unevenness is formed on the non-opposing main surface 9a of the semiconductor substrate 9, when the metal film 10 is formed on the main surface 9a, irregularities can be formed in the metal film 10, and the surface area of the metal film 10 having high thermal conductivity can be increased. . Further, in the module 2 which is required to have a flatness on one side of the main surface 11a of the wiring board 11, the metal film 10 can be formed thick by filling the unevenness of the non-opposing main surface 9a of the semiconductor substrate 9 The surface of the metal film 10 is flat.

然而,若半導體基板9之非對向主面9a之平均粗度(Ra)之值過小,則不易在半導體基板9之非對向主面9a藉由鍍敷處理形成金屬膜10,若平均粗度(Ra)之值過大,則有半導體基板9破損之虞,因此較佳為,半導體基板9之非對向主面9a之表面之平均粗度(Ra)形成在0.1μm~15μm之範圍。 However, if the value of the average thickness (Ra) of the non-opposing principal surface 9a of the semiconductor substrate 9 is too small, it is difficult to form the metal film 10 by the plating treatment on the non-opposing main surface 9a of the semiconductor substrate 9, if the average thickness is coarse If the value of the degree (Ra) is too large, the semiconductor substrate 9 may be damaged. Therefore, the average roughness (Ra) of the surface of the non-opposing main surface 9a of the semiconductor substrate 9 is preferably in the range of 0.1 μm to 15 μm.

接著,如圖3(b)所示,在從樹脂層13表面露出之半導體基板9之非對向主面9a及連接端子8之前端面8a形成金屬膜10(金屬膜形成步驟),製造模組2。此時,金屬膜10係使用鍍敷處理或印刷技術等形成。例如,鍍敷處理之情形,在半導體基板9之非對向主面9a及連接端子8之前端面8a使Ni層成長,從其上使Au層成長以形成金屬膜10。此外,半導體基板9之非對向主面9a之金屬膜10無需形成在半導體基板9之該非對向主面9a之整面,只要形成在至少一部分即可。 Next, as shown in FIG. 3(b), a metal film 10 is formed on the non-opposing main surface 9a of the semiconductor substrate 9 exposed from the surface of the resin layer 13 and the front end surface 8a of the connection terminal 8 (metal film forming step), and a module is manufactured. 2. At this time, the metal film 10 is formed using a plating process, a printing technique, or the like. For example, in the case of the plating treatment, the Ni layer is grown on the end surface 8a of the non-opposing main surface 9a of the semiconductor substrate 9 and the connection terminal 8, and the Au layer is grown thereon to form the metal film 10. Further, the metal film 10 of the non-opposing main surface 9a of the semiconductor substrate 9 need not be formed on the entire surface of the non-opposing main surface 9a of the semiconductor substrate 9, and may be formed in at least a part.

此外,製造模組搭載裝置1之情形,以藉由上述模組2之製造方法製造之模組2之配線基板11之一主面11a(半導體基板9之非對向主面9a)與母基板3對向之方式,透過焊料等將形成在半導體基板9之非對向主面9a及連接端子8之前端面8a之金屬膜10與形成在母基板3之表面之構裝電極7加以連接而製造。 Further, in the case of manufacturing the module mounting device 1, one main surface 11a (non-opposing main surface 9a of the semiconductor substrate 9) and the mother substrate of the wiring substrate 11 of the module 2 manufactured by the manufacturing method of the module 2 are used. In the three-way manner, the metal film 10 formed on the non-opposing main surface 9a of the semiconductor substrate 9 and the front end surface 8a of the connection terminal 8 and the constituent electrode 7 formed on the surface of the mother substrate 3 are connected by solder or the like. .

是以,根據上述實施形態,以半導體基板9之未與配線基板11對向側之非對向主面露出之方式在配線基板11之一主面11a形成樹脂層13a,在從樹脂層13a露出之半導體基板9之非對向主面9a形成熱傳導率較半導體基板9高之金屬膜10,因此與僅半導體基板9之非對向主面9a從樹脂層13a之表面露出之習知模組相較,模組2之散熱特性提升。 According to the above-described embodiment, the resin layer 13a is formed on one main surface 11a of the wiring substrate 11 so that the non-opposing main surface of the semiconductor substrate 9 is not exposed to the opposite side of the wiring substrate 11, and is exposed from the resin layer 13a. The non-opposing main surface 9a of the semiconductor substrate 9 forms the metal film 10 having a higher thermal conductivity than the semiconductor substrate 9, and thus is compared with a conventional module in which only the non-opposing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13a. The heat dissipation characteristics of the module 2 are improved.

又,以在半導體基板9之非對向主面9a形成凹凸之方式研磨或研削半導體基板9之非對向主面9a之情形,由於在形成在該非對向主面之金屬膜10之表面亦可形成凹凸,因此從樹脂層13a之表面露出之金屬膜10之表面積增加,藉此,模組2之散熱特性進一步提升。 Further, in the case where the non-opposing main surface 9a of the semiconductor substrate 9 is polished or ground so as to form irregularities on the non-opposing main surface 9a of the semiconductor substrate 9, the surface of the metal film 10 formed on the non-opposing main surface is also Since the unevenness can be formed, the surface area of the metal film 10 exposed from the surface of the resin layer 13a is increased, whereby the heat dissipation characteristics of the module 2 are further improved.

又,藉由在半導體基板9之非對向主面9a形成具有延展性 之金屬膜10,從樹脂層13a露出之半導體基板9之非對向主面9a受到保護,因此可抑制半導體基板9因來自外部之衝擊等而破損。 Further, by forming the ductility on the non-opposing main surface 9a of the semiconductor substrate 9 In the metal film 10, the non-opposing main surface 9a of the semiconductor substrate 9 exposed from the resin layer 13a is protected, so that the semiconductor substrate 9 can be prevented from being damaged by an external impact or the like.

又,金屬膜10係以Ni/Au膜形成,因此可提升藉由焊料連接模組2與母基板3時之焊料之濕潤性。 Further, since the metal film 10 is formed of a Ni/Au film, the wettability of the solder when the module 2 and the mother substrate 3 are joined by the solder can be improved.

又,在構裝有半導體基板9之配線基板11之一主面11a豎設有熱傳導率較樹脂層13a之樹脂高之連接端子8,由於連接端子8之前端面8a亦從樹脂層13a之表面露出,因此模組2之散熱特性進一步提升。又,藉由連接端子8可連接母基板3與模組2。 Further, the connection terminal 8 having a higher thermal conductivity than the resin of the resin layer 13a is vertically disposed on one main surface 11a of the wiring substrate 11 on which the semiconductor substrate 9 is mounted, and the front end surface 8a of the connection terminal 8 is also exposed from the surface of the resin layer 13a. Therefore, the heat dissipation characteristics of the module 2 are further improved. Moreover, the mother substrate 3 and the module 2 can be connected by the connection terminal 8.

又,藉由研磨或研削樹脂層13a之表面,能使連接於母基板3之接地電極5之連接端子8之長度(離配線基板11之一主面11a之高度)變短,可降低起因於連接端子8之寄生電感,藉此可謀求接地之強化。 Further, by polishing or grinding the surface of the resin layer 13a, the length of the connection terminal 8 connected to the ground electrode 5 of the mother substrate 3 (the height from one main surface 11a of the wiring substrate 11) can be shortened, which can be reduced due to By connecting the parasitic inductance of the terminal 8, the grounding can be enhanced.

然而,本實施形態中,在配線基板11之一主面11a僅配置覆晶構裝之半導體基板9與連接端子8,且在另一主面11b配置晶片電容器等之晶片零件12a~12c。 In the present embodiment, only the semiconductor substrate 9 and the connection terminal 8 of the flip chip are disposed on one main surface 11a of the wiring substrate 11, and the wafer components 12a to 12c such as a wafer capacitor are disposed on the other main surface 11b.

為了使模組2小型化(使配線基板11之構裝面積變小),在配線基板11之兩主面11a,11b配置構裝零件較有效。又,與圖4所示之習知技術相同,藉由將半導體基板9之非對向主面9a與連接端子8一起研磨等而高度變低,對謀求模組2之小型化亦有效。然而,例如,若在配線基板11之相同主面上構裝半導體基板9與各晶片零件12a~12c,則不易研磨半導體基板9之非對向主面9a而謀求使模組2高度變低。其原因在於,若藉由研磨晶片電容器或晶片電感器即各晶片零件12a~12c而研削,則會有特性劣化之虞。因此,若以上述方式構成,則無法使半導體基板9離該相同主 面之高度較構裝在相同主面上之各晶片零件12a~12c之高度低。 In order to reduce the size of the module 2 (to reduce the mounting area of the wiring board 11), it is effective to arrange the components on the both main surfaces 11a and 11b of the wiring board 11. In addition, as in the conventional technique shown in FIG. 4, the non-opposing main surface 9a of the semiconductor substrate 9 and the connection terminal 8 are polished together to be highly lowered, which is also effective for miniaturizing the module 2. However, for example, when the semiconductor substrate 9 and the respective wafer components 12a to 12c are formed on the same main surface of the wiring substrate 11, the non-opposing main surface 9a of the semiconductor substrate 9 is less likely to be polished, and the height of the module 2 is lowered. The reason for this is that if the wafer capacitors or the wafer inductors, that is, the wafer components 12a to 12c, are ground and ground, the characteristics are deteriorated. Therefore, if it is configured as described above, the semiconductor substrate 9 cannot be separated from the same main body. The height of the face is lower than the height of each of the wafer parts 12a to 12c mounted on the same main surface.

因此,本實施形態中,如上述,在配線基板11之一主面11a僅配置即使研磨該非對向主面9a特性亦不會劣化之覆晶構裝之半導體基板9與連接端子8,且在另一主面11b配置晶片電容器或晶片電感器等之各晶片零件12a~12c,將配線基板11之一主面11a之樹脂層13a之表面與半導體基板9及連接端子8一起研磨或研削,藉此成為可謀求模組2高度變低之模組構成。 Therefore, in the present embodiment, as described above, only one of the semiconductor substrates 9 and the connection terminals 8 of the flip chip structure which does not deteriorate even if the characteristics of the non-opposing main surface 9a are polished is provided on one main surface 11a of the wiring substrate 11, and The other main surface 11b is provided with each of the wafer components 12a to 12c such as a wafer capacitor or a chip inductor, and the surface of the resin layer 13a of one of the main surfaces 11a of the wiring substrate 11 is ground or ground together with the semiconductor substrate 9 and the connection terminal 8. This makes it possible to construct a module in which the height of the module 2 is lowered.

又,以離配線基板11之一主面11a之高度最高之半導體基板9(或連接端子8)之高度Ht較離配線基板11之另一主面11b之高度最低之晶片零件12a之高度H0低之方式研磨或研削半導體基板9(或連接端子8),因此可確實地謀求模組2高度變低。 Further, the height Ht to one of the wiring board 11 from the main surface of the semiconductor substrate 9 of the maximum height (or terminals 8) of the lowest 11a of the wiring board than from the other main surface 11 of the part 11b of the wafer height of the height H 0 12a Since the semiconductor substrate 9 (or the connection terminal 8) is ground or ground in a low manner, the height of the module 2 can be surely lowered.

又,藉由以半導體基板9之非對向主面9a從樹脂層13之表面露出之方式研磨或研削樹脂層13a,與半導體基板9之非對向主面9a被樹脂層13a被覆之習知模組相較,在母基板3搭載有模組2時(參照圖1)之半導體基板9之非對向主面9a與母基板3之接地電極5之距離變近,因此容易使從模組2產生之熱透過接地電極5散熱,可提升模組2之散熱特性。又,半導體基板9之金屬膜10係透過焊料與和母基板3之接地電極5連接之構裝用電極7連接,因此能更有效地使從模組2產生之熱散熱。 Further, the resin layer 13a is polished or ground so that the non-opposing main surface 9a of the semiconductor substrate 9 is exposed from the surface of the resin layer 13, and the conventional module in which the non-opposing main surface 9a of the semiconductor substrate 9 is covered with the resin layer 13a In contrast, when the module 2 is mounted on the mother substrate 3 (see FIG. 1 ), the distance between the non-opposing main surface 9 a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3 is increased, so that it is easy to generate from the module 2 . The heat is dissipated through the ground electrode 5 to improve the heat dissipation characteristics of the module 2. Further, since the metal film 10 of the semiconductor substrate 9 is connected to the constituent electrode 7 connected to the ground electrode 5 of the mother substrate 3 through the solder, the heat generated from the module 2 can be more efficiently dissipated.

又,藉由使半導體基板9之非對向主面9a與母基板3之接地電極5之距離變近,半導體基板9之電路面(半導體基板9之與配線基板11之對向面)與接地電極5之距離變近,因此能有效地抑制從半導體基板9之電路面輻射之不需要雜訊之影響,且可抑制從外部對半導體基板9照射 之不需要雜訊。 Further, by bringing the distance between the non-opposing main surface 9a of the semiconductor substrate 9 and the ground electrode 5 of the mother substrate 3, the circuit surface of the semiconductor substrate 9 (opposite surface of the semiconductor substrate 9 and the wiring substrate 11) and grounding Since the distance between the electrodes 5 is close, the influence of unwanted noise radiated from the circuit surface of the semiconductor substrate 9 can be effectively suppressed, and the semiconductor substrate 9 can be suppressed from being irradiated from the outside. No need for noise.

又,藉由將形成在半導體基板9之非對向主面9a之金屬膜10利用在模組2與母基板3之連接,以在連接端子8之前端面8a及半導體基板9之非對向主面9a分別形成之金屬膜10可連接母基板3與模組2,因此與僅以模組2之連接端子8與母基板3連接之習知模組搭載裝置相較,可提升模組2與母基板3之連接強度。 Moreover, the metal film 10 formed on the non-opposing main surface 9a of the semiconductor substrate 9 is used for connection between the module 2 and the mother substrate 3, so that the end face 8a and the semiconductor substrate 9 are not opposite to each other before the connection terminal 8. The metal film 10 formed on the surface 9a can be connected to the mother substrate 3 and the module 2, so that the module 2 and the mother substrate can be improved compared with the conventional module mounting device in which only the connection terminal 8 of the module 2 is connected to the mother substrate 3. 3 connection strength.

又,在半導體基板9之金屬膜10之表面形成凹凸之情形,由於半導體基板9之金屬膜10與母基板3之連接面積增加,因此可進一步提升模組2與母基板3之連接強度。 Further, in the case where irregularities are formed on the surface of the metal film 10 of the semiconductor substrate 9, since the connection area between the metal film 10 of the semiconductor substrate 9 and the mother substrate 3 is increased, the connection strength between the module 2 and the mother substrate 3 can be further improved.

又,若研磨配線基板11之一主面11a之樹脂層13a,則形成樹脂層13a之樹脂之量較另一主面11b之樹脂層13b之樹脂之量少,因此在兩樹脂層13a,13b分別產生之收縮應力失去均衡,會有配線基板11彎曲之虞,但在較形成兩樹脂層13a,13b之樹脂硬之半導體基板9使用構裝在配線基板11之兩主面11a,11b之各構裝零件9,12a~12c中之俯視下面積(橫剖面積)最大者,因此可抑制因上述兩樹脂層13a,13b之收縮應力失去均衡產生之配線基板11之彎曲。 When the resin layer 13a of one main surface 11a of the wiring substrate 11 is polished, the amount of resin forming the resin layer 13a is smaller than the amount of resin of the resin layer 13b of the other main surface 11b, and therefore the resin layers 13a, 13b are formed. The contraction stress generated separately is unbalanced, and the wiring substrate 11 is bent. However, the resin-hardened semiconductor substrate 9 which is formed of the two resin layers 13a and 13b is formed on each of the two main faces 11a and 11b of the wiring substrate 11. Since the area (cross-sectional area) in the plan view of the components 9 and 12a to 12c is the largest, it is possible to suppress the bending of the wiring board 11 caused by the loss of the contraction stress of the two resin layers 13a and 13b.

又,形成樹脂層13b之樹脂係使用線膨脹係數較形成樹脂層13a之樹脂小者,因此可進一步抑制配線基板11之彎曲。 Further, since the resin forming the resin layer 13b is smaller than the resin forming the resin layer 13a, the bending of the wiring substrate 11 can be further suppressed.

此外,本發明並不限於上述各實施形態,只要不脫離其趣旨,除了上述以外可進行各種變更。 The present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

例如,上述各實施形態中,覆晶構裝在配線基板11之一主面11a之半導體基板9為複數個亦可。 For example, in each of the above embodiments, the number of the semiconductor substrates 9 laminated on one main surface 11a of the wiring substrate 11 may be plural.

又,半導體基板9在俯視下之面積較其他構裝零件之任一者之面積小亦可。此外,若為構裝後之高度較研磨或研削後之半導體基板9之高度低之構裝零件,則配置在配線基板11之一主面11a亦可。亦即,只要為在配線基板11之一主面11a構裝或配置可研磨或研削該主面9a之半導體基板9之構成即可,此外,為了縮小配線基板11構裝面積,適當地設計各構裝零件之配置即可。 Further, the area of the semiconductor substrate 9 in a plan view may be smaller than the area of any of the other components. Further, the component which is lower in height after the mounting and the height of the semiconductor substrate 9 after polishing or grinding may be disposed on one main surface 11a of the wiring substrate 11. In other words, the semiconductor substrate 9 on which the main surface 9a can be polished or ground may be disposed or disposed on one main surface 11a of the wiring substrate 11. Further, in order to reduce the mounting area of the wiring substrate 11, each design is appropriately designed. The configuration of the component can be configured.

又,在配線基板11之另一主面11b僅構裝晶片電容器或晶片電感器等之晶片零件12a~12c,但在另一主面11b構裝與構裝在一主面11a之半導體基板9相同或不同之其他半導體基板9亦可。 Further, only the wafer components 12a to 12c such as a wafer capacitor or a chip inductor are mounted on the other main surface 11b of the wiring substrate 11, but the semiconductor substrate 9 is mounted and mounted on the main surface 11a on the other main surface 11b. Other semiconductor substrates 9 which are the same or different may also be used.

又,金屬膜10係使用例如導電性糊形成亦可,藉由濺鍍或蒸鍍形成亦可。 Further, the metal film 10 may be formed using, for example, a conductive paste, and may be formed by sputtering or vapor deposition.

又,形成在配線基板11之一主面11a之連接端子8之個數為任意亦可,在配線基板11之另一主面11b亦配置連接端子8亦可。又,連接端子8並不一定要配置在配線基板11之一主面11a。亦即,連接端子8與半導體基板9配置在配線基板11之不同主面亦可。此外,連接端子與半導體基板9配置在配線基板11之不同主面之情形,金屬膜不僅形成在半導體基板9之非對向主面9a,藉由亦形成在樹脂層13b之周圍,可作用為模組2之屏蔽層。 Further, the number of the connection terminals 8 formed on one main surface 11a of the wiring substrate 11 may be any, and the connection terminal 8 may be disposed on the other main surface 11b of the wiring substrate 11. Further, the connection terminal 8 does not have to be disposed on one main surface 11a of the wiring substrate 11. In other words, the connection terminal 8 and the semiconductor substrate 9 may be disposed on different main faces of the wiring substrate 11. Further, when the connection terminal and the semiconductor substrate 9 are disposed on different main faces of the wiring substrate 11, the metal film is formed not only on the non-opposing main surface 9a of the semiconductor substrate 9, but also around the resin layer 13b, and can function as The shielding layer of module 2.

又,上述各實施形態中,為在配線基板11之另一主面11b未構裝各晶片零件12a~12c之構成亦可。 Further, in each of the above embodiments, the respective wafer components 12a to 12c may not be mounted on the other main surface 11b of the wiring board 11.

又,各樹脂層13a,13b並不一定要設置在配線基板11之兩主面11a,11b亦可。 Further, the resin layers 13a and 13b are not necessarily required to be provided on the two main faces 11a and 11b of the wiring board 11.

又,上述實施形態中,以半導體基板9之非對向主面9a、連接端子8之前端面8a、及樹脂層13a表面構成同一面之所謂面高相同狀態之方式形成各面,但將樹脂層13a之表面高度形成為較半導體基板9(非對向主面9a)及連接端子8(前端面8a)之高度低亦可。亦即,以半導體基板9之端部及連接端子8之端部從樹脂層13a表面突出之方式形成樹脂層13a亦可。藉由以上述方式形成樹脂層13a,熱傳導率較樹脂層13a之樹脂高之半導體基板9及連接端子8分別之端部從樹脂層13a表面露出,因此模組2之散熱特性進一步提升。 In the above-described embodiment, each surface is formed such that the non-opposing main surface 9a of the semiconductor substrate 9, the front end surface 8a of the connection terminal 8, and the so-called surface height of the surface of the resin layer 13a are the same, but the resin layer is formed. The surface height of 13a may be formed to be lower than the height of the semiconductor substrate 9 (non-opposing main surface 9a) and the connection terminal 8 (front end surface 8a). In other words, the resin layer 13a may be formed so that the end portion of the semiconductor substrate 9 and the end portion of the connection terminal 8 protrude from the surface of the resin layer 13a. By forming the resin layer 13a in the above manner, the end portions of the semiconductor substrate 9 and the connection terminal 8 each having a higher thermal conductivity than the resin of the resin layer 13a are exposed from the surface of the resin layer 13a, so that the heat dissipation characteristics of the module 2 are further improved.

再者,本發明若為在配線基板11之一主面11a覆晶構裝有半導體基板9之構成,則可適用於任何模組。 Further, in the present invention, if the semiconductor substrate 9 is formed by laminating a main surface 11a of the wiring substrate 11, it can be applied to any module.

1‧‧‧模組搭載裝置 1‧‧‧Modular carrying device

2‧‧‧模組 2‧‧‧ modules

3‧‧‧母基板 3‧‧‧ mother substrate

4‧‧‧底填樹脂層 4‧‧‧ bottom filling resin layer

5‧‧‧接地電極 5‧‧‧Ground electrode

6‧‧‧通孔導體 6‧‧‧through hole conductor

7‧‧‧構裝用電極 7‧‧‧Electrical electrode

8‧‧‧連接端子 8‧‧‧Connecting terminal

8a‧‧‧前端面 8a‧‧‧ front end

9‧‧‧半導體基板 9‧‧‧Semiconductor substrate

9a‧‧‧非對向主面 9a‧‧‧non-opposite main face

10‧‧‧金屬膜 10‧‧‧Metal film

11‧‧‧配線基板 11‧‧‧Wiring substrate

11a‧‧‧一主面 11a‧‧‧One main face

11b‧‧‧另一主面 11b‧‧‧The other main face

12a,12b,12c‧‧‧晶片零件 12a, 12b, 12c‧‧‧ wafer parts

13a,13b‧‧‧樹脂層 13a, 13b‧‧‧ resin layer

14‧‧‧接地電極 14‧‧‧Ground electrode

15‧‧‧構裝用電極 15‧‧‧Electrical electrode

15a‧‧‧電極 15a‧‧‧electrode

Claims (7)

一種高頻模組,具備:配線基板;半導體基板,構裝在該配線基板之一主面;以及樹脂層,以該半導體基板之未與該配線基板對向側之非對向主面露出之方式被覆該半導體基板,形成在該一主面;在該半導體基板之該非對向主面之至少一部分形成有金屬膜。 A high frequency module comprising: a wiring substrate; a semiconductor substrate mounted on one main surface of the wiring substrate; and a resin layer covered with the non-opposing main surface of the semiconductor substrate not facing the wiring substrate The semiconductor substrate is formed on the one main surface, and a metal film is formed on at least a portion of the non-opposing main surface of the semiconductor substrate. 如申請專利範圍第1項之高頻模組,其中,在該金屬膜之表面形成有凹凸。 The high frequency module of claim 1, wherein the surface of the metal film is formed with irregularities. 如申請專利範圍第1或2項之高頻模組,其中,該金屬膜係藉由鍍敷形成。 The high frequency module of claim 1 or 2, wherein the metal film is formed by plating. 如申請專利範圍第1或2項之高頻模組,其進一步具備豎設在該一主面之柱狀之連接端子;該連接端子之前端面從該樹脂層之表面露出。 The high frequency module according to claim 1 or 2, further comprising a columnar connection terminal erected on the one main surface; the front end surface of the connection terminal is exposed from a surface of the resin layer. 如申請專利範圍第3項之高頻模組,其進一步具備豎設在該一主面之柱狀之連接端子;該連接端子之前端面從該樹脂層之表面露出。 The high frequency module of claim 3, further comprising a columnar connection terminal erected on the main surface; the front end surface of the connection terminal is exposed from a surface of the resin layer. 一種高頻模組搭載裝置,具備:申請專利範圍第1至5項中任一項之高頻模組;以及母基板,與該高頻模組之該金屬膜連接。 A high-frequency module mounting device comprising: the high-frequency module according to any one of claims 1 to 5; and a mother substrate connected to the metal film of the high-frequency module. 如申請專利範圍第6項之高頻模組搭載裝置,其中,該高頻模組之該金屬膜與形成在該母基板之接地用之接地電極連接。 The high frequency module mounting device according to claim 6, wherein the metal film of the high frequency module is connected to a ground electrode formed on the ground of the mother substrate.
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