TWI521642B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a structure for integrating a metal-gate transistor and a polysilicon resistor and a method of fabricating the same.

As the size of semiconductor components continues to shrink, the conventional method utilizes a tunneling effect that reduces the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-K) materials have an effective reduction in physical limit thickness and are under the same equivalent oxide thickness (EOT). It effectively reduces the leakage current and achieves the equivalent capacitance to control the channel switch. It is used to replace the traditional germanium dioxide layer or the yttria layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching High-K gate dielectric layer. Control electrode.

However, even if a high-K gate dielectric layer is used to replace the conventional germanium dioxide or yttria gate dielectric layer, and a metal gate with a matching work function is substituted for the conventional polysilicon gate, how to make a work function metal The integration of other passive components such as capacitors or resistors with gated transistors while achieving cost reduction and competing products is an important issue today.

Therefore, the main object of the present invention is to provide a method and structure for fabricating an integrated resistor and a metal gate transistor.

A preferred embodiment of the invention discloses a method of fabricating a semiconductor device. First, a substrate is provided having a transistor region and a resistive region defined thereon. Then, a shallow trench is formed to be isolated from the resistive region of the substrate, a recess is formed in the shallow trench isolation of the resistive region, and a shallow trench isolation surface is formed in the recess of the resistive region and on both sides of the recess.

According to another embodiment of the invention, a semiconductor device includes a substrate having a transistor region and a resistive region; a shallow trench is isolated from the resistive region of the substrate; and a recess is disposed in the resistive region In the trench isolation; and a shallow trench isolation surface provided in the recess and on both sides of the recess.

Please refer to FIG. 1 to FIG. 8 . FIG. 1 to FIG. 8 are schematic diagrams showing an integrated resistor and a transistor having a metal gate according to a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 12 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. At least one resistive region 14 and a transistor region 16 are defined in the substrate 12, and a shallow trench isolation (STI) 18 structure and a plurality of isolation transistor regions are formed in the substrate 12 of the resistive region 14. The shallow trench of 16 is isolated 18. The method for fabricating the shallow trench isolation 18 generally involves the steps of: covering a substrate 12 with a selective buffer layer such as a thin oxide layer, and then completely covering a hard mask layer such as a tantalum nitride layer; Forming a region of the shallow trench isolation 18, and then trenching the substrate 12 in the region by an etching process; forming an insulating material such as yttrium oxide on the substrate 12 to fill the trench to form the shallow trench isolation 18; The heat treatment is selectively performed, such as heat treatment in an oxygen-containing environment to densify the insulating material and repair the entire structure; and the excess insulating material is removed by a planarization treatment such as chemical mechanical polishing to expose the substrate 12.

A patterned hard mask is then formed, such as a tantalum nitride mask over the surface of the shallow trench isolation 18 that was previously used to define the shallow trench isolation and the substrate 12 and expose portions of the resistive regions 14 and then utilize this pattern. The hard mask is subjected to an etching process to remove a portion of the shallow trench isolation 18 of the resistive region 14 to a predetermined depth to form a recess 76 in the shallow trench isolation 18. The etching process may be a dry etching process or a wet etching process or a combination thereof, and the etching process may be a single etching process (completed in the same machine) or a combination of multiple etching processes (completed in the same machine or different machines) Completed in Taichung). After the recess 76 is formed, the patterned hard mask is removed from the aforementioned hard mask. Generally, the top surface of the shallow trench isolation 18 structure obtained after removing the hard mask layer is slightly higher than the top surface of the substrate 12 (in order to reduce the complexity of the illustration, this feature is not shown in the figure), but shallow The height of the top surface of the trench isolation 18 structure will gradually change with subsequent processes.

Then, as shown in FIG. 2, a selective dielectric layer 20 composed of a dielectric material such as an oxide or a nitride, a high-k dielectric layer 22, and a selective mask layer are formed (not shown). And a stacked film 74 of a barrier layer 24 on the substrate 12, and then a polysilicon layer 26 is formed on the stacked film 74 in a comprehensive manner. The dielectric layer 20 is a single layer structure, but is not limited thereto. The dielectric layer 20 may include an oxide layer or a multilayer structure.

In the preferred embodiment, the high-k dielectric layer 22 may comprise a metal oxide layer, such as a rare earth metal oxide layer, and optionally hafnium oxide (HfO ₂ ), bismuth citrate Compound (hafnium silicon oxide, HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (lanthanum aluminum) oxide, LaAlO), tantalum oxide _{(tantalum oxide, Ta 2 O 3} ), zirconia (zirconium oxide, ZrO _2), zirconium silicate oxide compound (zirconium silicon oxide, ZrSiO), hafnium zirconium (hafnium zirconium oxide, HfZrO) , strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate , a group consisting of BaxSr _1-x TiO ₃ , BST) and the like. The cover layer may be lanthanum oxide (LaO), dysprosium oxide (Dy ₂ O _3), or a combination thereof; barrier layer 24 is preferably formed of titanium nitride (of TiN); the polysilicon layer 26 may have any of a non-doped It is composed of an undoped polycrystalline germanium material, a polycrystalline germanium material having an N+ dopant, or an amorphous germanium material.

Next, the polysilicon layer 26 is undoped, and an ion implantation process is performed to implant the boron atoms into the polysilicon layer 26 to a predetermined depth, so that a portion of the polysilicon layer 26, for example, the upper half. A polycrystalline germanium layer 28 having a dopant is formed while a lower polycrystalline germanium layer 26 is maintained in the lower half. In a preferred embodiment, the thickness of the non-doped polysilicon layer 26 is approximately less than or equal to the depth of the recess 76 in the shallow trench isolation 18.

As shown in FIG. 3, a hard mask 30 is formed to cover the entire polysilicon layer 28, and then another patterned photoresist layer (not shown) is formed on the hard mask 30, and the patterned photoresist layer is utilized. Performing a pattern transfer process as a mask, removing a portion of the hard mask 30, the polysilicon layer 28/26 and the stacked film 74 in a single etching or successive etching step, and stripping the patterned photoresist layer to form the resistive region 14 A polysilicon resistor 34 formed by the patterned mask layer 30 and the patterned polysilicon layer and a dummy gate 32 formed by the patterned mask layer 30 and the patterned polysilicon layer are formed in the transistor region 16. In the present embodiment, the hard mask 30 is preferably made of SiO ₂ , lanthanum nitride (SiN), tantalum carbide (SiC) or lanthanum oxynitride (SiON), and the polysilicon resistor 34 is disposed in addition to The grooves 76 are simultaneously disposed on the shallow trench isolations 18 on both sides of the recess 76.

Then, as shown in FIG. 4, a first sidewall 36 and a second sidewall 38 are formed on the sidewalls of the dummy gate 32 and the polysilicon resistor 34, respectively, and the first sidewall 36 and the second sidewall in the transistor region 16. A lightly doped drain 40 and a source/drain 42 of a corresponding conductivity type are respectively formed in the substrate 12 on both sides of the 38.

Then, a selective epitaxial growth process can be performed on the transistor region 16. For example, two recesses are first etched into the substrate 12 on both sides of the second sidewall sub-38 of the transistor region 16, and then formed in each of the recesses. An epitaxial layer containing bismuth telluride or tantalum carbide (not shown). In this embodiment, the epitaxial layer preferably comprises germanium germanium, and may be formed in a single layer or multiple layers; when the epitaxial layer is grown, it may be doped in-situly, and the doping may be performed in a gradual manner (for example, The bottom layer has no dopant, the first layer is lightly doped, the second layer is thicker, the third layer is rich, ... the top layer is free of dopants or light dopants; the hetero atom is (in this case The concentration of helium atoms can also be changed in a gradual manner. The concentration will vary depending on the lattice constant and surface traits. However, the surface will be expected to have a lighter erbium atom concentration or no ruthenium atoms for subsequent bismuth formation. In addition, the ion implantation of the source/drain 42 in this embodiment is performed before the epitaxial layer, but may be performed in the formation of the epitaxial layer according to the process requirements.

Subsequently, a metal telluride process can be performed. For example, a metal layer (not shown) made of cobalt, titanium, nickel, platinum, palladium, molybdenum or the like is formed on the substrate 12 and covers the source/drain 42 and then The metal layer is reacted with the source/drain 42 using at least one rapid thermal anneal (RTP) process to form a deuterated metal layer 44 on the surface of the source/drain 42. Finally, the unreacted metal is removed.

The hard mask 30 can then be selectively removed to form a contact etch stop layer 46 on the surface of the substrate 12 and overlying the dummy gate 32 and the polysilicon resistor 34, and then forming an interlayer dielectric layer 48 on the substrate 12 and covering the contacts. The hole etch stop layer 46. In the present embodiment, the contact hole etch stop layer 46 is preferably composed of tantalum nitride, and it may have different stresses for the different transistor types in the transistor region 16, and the interlayer dielectric layer 48 is preferably oxidized. The crucible is constructed and may have a thickness of between 1,500 and 5,000 angstroms, preferably about 3,000 angstroms.

As shown in FIG. 5, a planarization process is performed, for example, a portion of the interlayer dielectric layer 48 and a portion of the contact hole etch stop layer 46 are removed by a chemical mechanical polishing process, so that the partial contact hole etch stop layer 46 still covers the dummy layer. Gate 32 and polysilicon resistor 34. Then, an etching process is performed to remove a portion of the interlayer dielectric layer 48 of the transistor region 16 and the resistor region 14 and a portion of the contact hole etch stop layer 46 and expose the surface of the dummy gate 32 and the recess 76 on both sides of the resistor region 14 Boron-doped polycrystalline germanium layer 28.

Next, as shown in FIG. 6, a dry etching process is performed on the hollow crystal region 16 and a portion of the polysilicon layer of the resistive region 14, in particular, the polysilicon layer 28 having a boron dopant and the resistor in the dummy gate 32 of the transistor region 16. Zone 14 has a boron-doped polysilicon layer 28 on both sides of groove 76. Subsequently, a wet etching process is performed to remove the polysilicon layer 26 remaining in the dummy gate 32 of the transistor region 16 and the remaining polysilicon layer 26 on both sides of the recess 76 of the resistor region 14 to form a plurality of openings 50. Since the present invention forms a recess 76 on the shallow trench isolation 18 of the resistive region 14, and implants boron atoms into a portion of the polysilicon layer to form a polysilicon layer 28 having boron dopants by ion implantation, the wet The etching process can effectively hollow out the opening 50 by removing the polysilicon layer 26 remaining on both sides of the recess 76 of the resistive region 14 by a different etching selectivity ratio of the polysilicon layer 28 having boron dopants and the polysilicon layer 26 on both sides. The polysilicon layer 26 does not produce lateral etching of the polysilicon layer 28 having boron dopants.

Next, as shown in FIG. 7, a work function metal layer 52 and a low-resistance conductive layer 54 are sequentially formed to fill the opening 50, and then a planarization process is performed, for example, a chemical mechanical polishing process is used to remove a portion of the work function metal layer. 52 and the conductive layer 54 form a metal gate 56 in the transistor region 16 and two contacts 58 connecting the polysilicon resistor 34 in the resistor region 14. It should be noted that since the work function metal layer 52 covers the sidewalls of the openings 50 first, the metal gate 56 and the contacts 58 which are simultaneously fabricated in the same process have a U-shaped work function metal layer 52 and a conductive layer. 54 is located on it.

In the present embodiment, the work function metal layer 52 may be composed of an N-type work function metal or a P-type work function metal depending on the type of the transistor. For example, if the transistor to be subsequently prepared in the transistor region 16 is a PMOS transistor, the metal layer 52 may be selected from titanium nitride (TiN) or tantalum carbide (TaC). If the prepared transistor is an NMOS transistor, the metal layer 52 may be selected from titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl) or tantalum aluminide (HfAl). ) The group resistance formed. In addition, the low-impedance conductive layer 54 may be selected from aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN). ), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W) or titanium and titanium nitride (Ti/TiN), etc., but not limited thereto.

It should be noted that, in the above embodiment, although the high-k first process is used to complete the fabrication of the semiconductor device, the spirit of the present invention can be applied to the post-high-k dielectric layer (high- k last) Process, which is also within the scope of the present invention.

For example, as shown in FIG. 8, a dummy gate structure and a polysilicon resistor as shown in FIG. 3 may be formed on the substrate 12, wherein the dummy gate and the polysilicon resistor include only one dielectric layer, The polysilicon layer and a hard mask do not have a high-k dielectric layer and a barrier layer. Then, the process of FIG. 4 is sequentially performed, including forming a first sidewall 36 and a second sidewall 38 around the dummy gate and the polysilicon resistor, and the substrate 12 on both sides of the first sidewall 36 and the second sidewall 38 Forming a lightly doped drain 40 and a source/drain 42 with a corresponding conductivity type, forming a contact etch stop layer 46 and an interlayer dielectric layer 48 on the surface of the substrate 12, and removing a portion of the contact hole by a planarization process The layer 46 and the interlayer dielectric layer 48 are stopped and the polysilicon layer on both sides of the dummy gate and the resistor region recess is hollowed out to form an opening 50 or the like. Then, as shown in FIG. 8, a high-k dielectric layer 22 is first deposited in the opening 50, such as the bottom portion and the sidewall of the opening 50 of the transistor region 16 and the resistive region 14, and then forms a height of approximately 50 openings. One of the barrier layers, such as a patterned photoresist layer (not shown), is on the high-k dielectric layer 22 within the opening 50. Then, the patterned photoresist layer is used as a mask to perform an etching process, and the high-k dielectric layer 22 whose sidewalls of the opening 50 are not shielded by the patterned photoresist layer is removed to form an approximately U-shaped portion at the bottom of the opening 50. High dielectric constant dielectric layer 22.

Then, the patterned photoresist layer is removed, and a barrier layer 24, a work function metal layer 52, and a low-resistance conductive layer 54 are sequentially formed in the opening 50 and fill the opening 50. Then, a planarization process is performed, for example, a portion of the barrier layer 24, the work function metal layer 52, and the conductive layer 54 are removed by a chemical mechanical polishing process to form a metal gate 56 in the transistor region 16 and form the resistor region 14. An embodiment in which the two contacts 58 of the polysilicon resistor 34 are connected to complete the post-high-k dielectric layer process.

As shown in FIG. 9, after the metal gate 56 and the contact 58 are completed, a protective layer 60 may be selectively deposited on the interlayer dielectric layer 48, and then another dielectric layer 62 may be formed on the surface of the protective layer 60. In the present embodiment, the protective layer 60 is preferably used to protect the conductive layer material in the metal gate 54 and the contact 58. It may be composed of SiCN or an oxide of the gate, but is not limited thereto. Finally, a plug process is performed to form a plurality of contact plugs 64 in the protective layer 60 and the dielectric layer 62 and connect the metal gates 54 of the transistor region 16 with the contacts of the source/drain electrodes 42 and the resistive regions 14. 58. Thus, the fabrication of a semiconductor device of a preferred embodiment of the present invention has been completed.

In general, the current process of integrating metal gate transistor and polysilicon resistors often encounters two problems, including the removal of a portion of the polysilicon layer to form the junction opening of the polysilicon resistor due to the hard mask on the surface of the polysilicon layer. Poorly causing lateral etching, and subsequent filling of the low-resistance conductive material in the opening and polishing, the conductive material remains due to the difference in height of the hard mask. Therefore, the present invention first forms a groove on the shallow trench isolation of the resistive region before patterning the polysilicon layer to form the dummy gate and the polysilicon resistor pattern, so that the subsequently completed polysilicon resistor body is disposed in the shallow trench isolation trench. The contacts on both sides are placed on the shallow trench isolation on both sides of the groove, and the two are at the different horizontal planes but the top is flush with the metal gate of the transistor region. Subsequent ion implantation is used to implant boron atoms into a portion of the polysilicon layer, such that a portion of the body of the subsequent polysilicon resistor and the contacts on both sides produce different etching selectivity ratios. Through these two steps, the present invention can simultaneously solve the above-mentioned problem of lateral etching of the polysilicon layer and residual of the conductive material due to the difference in height of the hard mask.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

12. . . Base

14. . . Resistance zone

16. . . Transistor region

18. . . Shallow trench isolation

20. . . Dielectric layer

twenty two. . . High dielectric constant dielectric layer

twenty four. . . Barrier layer

26. . . Polycrystalline layer

28. . . Polycrystalline layer

30. . . Hard mask

32. . . Virtual gate

34. . . Polysilicon resistor

36. . . First side wall

38. . . Second side wall

40. . . Lightly doped bungee

42. . . Source/bungee

44. . . Deuterated metal layer

46. . . Contact hole etch stop layer

48. . . Interlayer dielectric layer

50. . . Opening

52. . . Work function metal layer

54. . . Conductive layer

56. . . Metal gate

58. . . contact

60. . . The protective layer

62. . . Dielectric layer

64. . . Contact plug

76. . . Groove

1 to 9 are schematic views showing a semiconductor device having a metal gate and a polysilicon resistor in accordance with a preferred embodiment of the present invention.

12. . . Base

14. . . Resistance zone

16. . . Transistor region

18. . . Shallow trench isolation

20. . . Dielectric layer

twenty two. . . High dielectric constant dielectric layer

twenty four. . . Barrier layer

26. . . Polycrystalline layer

28. . . Polycrystalline layer

30. . . Hard mask

32. . . Virtual gate

34. . . Polysilicon resistor

36. . . First side wall

38. . . Second side wall

40. . . Lightly doped bungee

42. . . Source/bungee

44. . . Deuterated metal layer

46. . . Contact hole etch stop layer

48. . . Interlayer dielectric layer

50. . . Opening

52. . . Work function metal layer

54. . . Conductive layer

56. . . Metal gate

58. . . contact

60. . . The protective layer

62. . . Dielectric layer

64. . . Contact plug

76. . . Groove

Claims (19)

A method of fabricating a semiconductor device, comprising: providing a substrate having a transistor region and a resistive region defined thereon; forming a shallow trench to isolate the resistive region in the substrate; forming a recess in the resistive region In the shallow trench isolation; forming a shallow trench isolation surface in the recess of the resistive region and on both sides of the recess; and removing the resistor on the shallow trench isolation surface on both sides of the recess and forming a A work function metal layer and a conductive layer. The method of claim 1, wherein the forming the recess further comprises: sequentially forming a dielectric layer, a high-k dielectric layer, a barrier layer, and a polysilicon layer and covering the resistive region. The groove and the surface of the substrate of the transistor region; performing an ion implantation process to implant a dopant into a portion of the polysilicon layer; and patterning the dielectric layer, the high-k dielectric layer, a barrier layer and the polysilicon layer to form a gate in the transistor region and to form the resistor in the resistor region. The method of claim 2, wherein the dopant comprises boron atom. The method of claim 2, wherein after forming the gate and the resistor, further comprising: forming at least one sidewall on the sidewall of the gate and the resistor; and the sidewall of the gate A source/drain is formed in the substrate on both sides. The method of claim 4, wherein after forming the source/drain, further comprising: forming a contact hole etch stop layer and covering the gate and the resistor; forming a first dielectric layer and covering The contact hole etch stop layer; performing a first planarization process, removing a portion of the first dielectric layer and a portion of the contact hole etch stop layer: and performing an etch back process to expose the gate top and the recess The contact hole etch stop layer on the surface of the polysilicon layer and the contact hole etch stop layer on the surface of the polysilicon layer on both sides of the recess. The method of claim 5, further comprising: performing a dry etching process to remove the transistor region and implanting the doped polysilicon layer in the resistive region; performing a wet etching process to remove the transistor region and The polysilicon layer of the dopant is not implanted in the resistive region to form a plurality of openings in the transistor region and the resistive region; Forming the work function metal layer and the conductive layer to fill the openings; and performing a second planarization process to remove a portion of the work function metal layer and the conductive layer such that the conductive layer surface and the first dielectric layer The surface is flush such that a metal gate is formed in the transistor region and a plurality of contacts are formed on both sides of the recess in the resistor region. The method of claim 6, further comprising: forming a protective layer on the surface of the first dielectric layer; forming a second dielectric layer and covering the protective layer; and the protective layer and the second A plurality of contact plugs are formed in the dielectric layer and the metal gates and the contacts are connected. The method of claim 7, wherein the protective layer may comprise SiCN or an oxide of the gate. A semiconductor device comprising: a substrate having a transistor region and a resistance region; a shallow trench separating the resistor region disposed in the substrate; a recess disposed in the shallow trench isolation of the resistor region; And a shallow trench isolation surface disposed in the recess and on both sides of the recess, the resistor comprising a polysilicon layer and the polysilicon layer is disposed only in the recess. The semiconductor component of claim 9, further comprising two contacts disposed on the shallow trench isolation on both sides of the recess. The semiconductor device of claim 10, further comprising a contact hole etch stop layer disposed on a portion of the surface of the substrate and the surface of the polysilicon layer, and the contact hole etch stop layer is flush with the surface of the contact. The semiconductor device of claim 9, wherein at least a portion of the polysilicon layer comprises a dopant. The semiconductor device of claim 12, wherein the dopant comprises a boron atom. The semiconductor device of claim 10, wherein each of the contacts comprises a dielectric layer, a high-k dielectric layer, a barrier layer, a work function metal layer, and a conductive layer. The semiconductor device of claim 14, wherein the high-k dielectric layer is U-shaped or in-line. The semiconductor component of claim 14, wherein the work function metal layer is U-shaped. The semiconductor device of claim 11, further comprising a metal gate disposed in the transistor region, and the top of the metal gate is flush with the surface of the contact hole etch stop layer. The semiconductor device of claim 17, further comprising: a first dielectric layer disposed on the contact hole etch stop layer on the surface of the substrate; a protective layer disposed on the metal gate, the first dielectric layer An electrical layer and the contact hole etch stop layer; a second dielectric layer is disposed on the protective layer; and a plurality of contact plugs are disposed in the second dielectric layer, the protective layer and the first dielectric layer To connect the metal gate to the contacts. The semiconductor device of claim 18, wherein the protective layer may comprise SiCN or an oxide of the gate.