TWI518817B - Hierarchical wafer yield predicting method and hierarchical lifetime predicting method - Google Patents

Description

Hierarchical wafer yield prediction method and hierarchical wafer life cycle prediction method

The invention discloses a hierarchical wafer yield prediction method and a hierarchical wafer life cycle prediction method, in particular, a definition has a yield/lifetime domain, an integral domain (Integral Domain), A hierarchy of different levels of predictive yield or life cycle, such as electrical/layout, a metrology/defect domain, and a Machine Sensor Domain Wafer yield prediction method and hierarchical wafer life cycle prediction method.

In a typical wafer process, wafer yield is intensively monitored as a reference for improving yield. Furthermore, the yield can be predicted by observing data generated by a mechanical sensor based on Fault Detection and Classification (FDC) technology, which is used to sense wafer defects.

However, in the wafer process, there are many intermediate programs, and these intermediate programs introduce a large amount of noise in the process of predicting the yield. If these intermediate programs are also highly correlated with each other, or if these intermediate programs are implemented in the form of a flat algorithm, the effects of noise become more severe.

The present invention discloses a hierarchical wafer yield prediction method. The method includes measuring a total yield of a plurality of wafers; determining a systematic yield and a random yield based on the total yield; according to the system yield, and Using a 3-Sigma Binomial Analysis method to determine at least one system integral value; determining at least one systematic fault detection and classification value based on the at least one system integral value; Random yield, and using a three sigma dichotomy to determine a random integral value; and determining a random error detection and discrimination value based on the random integral value.

The present invention further discloses a hierarchical wafer life cycle prediction method. The method includes measuring a total life cycle of a plurality of wafers; determining an internal life cycle (Intrinsic Lifetime) and an external life cycle (Extrinsic Lifetime) according to the total life cycle; according to the external life cycle, and using the three-sigger The horse binary analysis method determines at least one external integral value; determines at least one external error detection and discrimination value according to the at least one external integral value; and determines an internal integral according to the internal life cycle and using the three sigma binary analysis method a value; and determining an internal error detection and discrimination value based on the internal integration value.

The hierarchical wafer yield prediction method and the hierarchical wafer life cycle prediction method disclosed by the present invention can reduce the noise in the wafer yield prediction model or the life cycle prediction model to improve the yield prediction model. Or the accuracy of the life cycle prediction model.

In order to improve the accuracy of predicting yield, the present invention discloses a hierarchical wafer yield prediction method using a yield/lifecycle domain, an integration domain, an electrical/layout domain, a metering/defective domain, and a machine. Five different classes, such as the sensor domain. The present invention further discloses a wafer life cycle prediction method that uses the same hierarchy as the wafer yield prediction method described above for predicting the life cycle of a wafer.

Please refer to FIG. 1 , which is a schematic diagram of a hierarchical architecture used in a hierarchical wafer yield prediction method according to a first embodiment of the present invention.

(a) Yield field

As shown in Figure 1, the total yield Y _{T of the} wafer will be measured first. A system yield Y _S and a random yield Y _R are then cut from the total yield Y _T . As shown in Figure 1, the system yield Y _S and the random yield Y _{R are} all in the yield domain.

(b) Integral domain

By using the 3-Sigma Binomial Analysis, the system yield Y _S is converted into a system wafer acceptance test integral value λ _{S , WAT} and a system defect density integral value λ _{S , DD} , wherein the three sigma dichotomy method is used to collect values within a distribution of intermediate values (Mean) within three standard deviations (Standard Deviation), and the distribution is the system wafer acceptance test integral value λ _{S , WAT} and system defect density integral values λ _{S , DD} are formed. Most of the noise will not be collected by the three sigma dichotomy, which is due to the fact that the noise mainly falls outside the three standard deviations from the median.

Similarly, the random yield Y _{R is} also converted to a random defect density integral value λ _{R , DD} by the use of the three sigma dichotomy. As shown in Fig. 1, the system wafer acceptance test integral value λ _{S , WAT} , the system defect density integral value λ _{S , DD} , and the random defect density integral value λ _{R , DD} belong to an integration domain.

(c) Electrical/layout domains, metering/defective domains, and mechanical sensor domains

In the present invention, the electrical/layout domain, the metering/defective domain, and the mechanical sensor domain are implemented by Principal Component Analysis (PCA) and Partial Least Square Analysis (PLS analysis).

Principal component analysis is mainly used to resolve the main factors or variables in the data. In this way, principal component analysis can determine the main factors that cause defects in the wafer.

The partial least squares analysis is mainly used to determine the correlation between various factors in the data. Therefore, by partial least squares analysis, the correlation between the various factors causing wafer defects can be determined.

For clarity of description, the system wafer acceptance test integral values λ _{S , WAT} , system defect density integral values λ _{S , DD} , and random defect density integral values λ _{R , DD} will be further described separately.

(c-1) System wafer acceptance test integral value λ _{S , WAT}

The system wafer acceptance test integral value λ _{S , WAT} will be processed according to the wafer acceptance test (Wafer Acceptance Test) based on principal component analysis or partial least squares analysis, wherein the wafer acceptance test is used To verify defects in the indirect points of the transistors arranged on the wafer. In this way, a plurality of wafer acceptance test parameters WAT _s belonging to the electrical/layout domain can be determined.

According to the system wafer acceptance test integral value λ _{S , WAT} is a characteristic of a plurality of wafer acceptance test parameters WAT _s and a plurality of measurement parameters MET _s , and a plurality of wafer acceptance test parameters WAT _{s are} then converted For a plurality of measurement parameters MET _s .

Finally, a plurality of measurement parameters MET _s are converted into a plurality of first system error detection and discrimination values FDC _s1 by using principal component analysis and partial least squares analysis, wherein the plurality of first system error detection and discrimination values The purpose of FDC _s1 is to indicate the prediction of the cause of wafer defects. A plurality of first system error detection and discrimination values FDC _s1 belong to the mechanical sensor domain.

(c-2) System defect density integral value λ _{S , DD}

The system defect density integral value λ _{S , DD} is processed by principal component analysis or partial least squares analysis to generate a plurality of system key region parameters CA _s belonging to the electrical/layout domain.

Since the system defect density integral value λ _{S , DD} is the integral of the plurality of system key area parameters CA _s and the plurality of system defect density parameters DD _s , the plurality of system key area parameters CA _{s are} then converted into a plurality of items belonging to the measurement / The system defect density parameter DD _{s of the} defect domain.

Similarly, a plurality of system defect density parameters DD _s are converted into a plurality of second system error detection and discrimination values FDC _S2 belonging to the mechanical sensor domain by using principal component analysis or partial least squares analysis.

(c-3) Random defect density integral value λ _{R , DD}

The random defect density integral value λ _{R , DD} after processing by principal component analysis or partial least squares analysis will generate a plurality of random key region parameters CA _R belonging to the electrical/layout domain.

Since the random defect density integral value λ _{R , DD} is the integral of the random key region parameter CA _R and the random defect density parameter DD _R , the plurality of random key region parameters CA _R can then be converted into a plurality of random belonging to the measurement/defect domain. Defect density parameter DD _R .

Similarly, a plurality of random defect density parameters DD _R can be converted into a plurality of random error detection and discrimination values FDC _R belonging to the mechanical sensor domain by using principal component analysis or partial least squares analysis.

After receiving a plurality of first system error detection and discrimination values FDC _s1 , a plurality of second system error detection and discrimination values FDC _S2 , and a plurality of random error detection and discrimination values FDC _R , the wafer can be implemented The yield prediction model is used to improve defects in the wafer process.

The hierarchical structure shown in Fig. 1 is implemented layer by layer and top to bottom.

In addition to yield prediction, in accordance with an embodiment of the present invention, the hierarchical structure shown in FIG. 1 can also be used to predict the life cycle of each transistor on the wafer or the lifetime of the wafer itself. Please refer to FIG. 2, which is a schematic diagram of a hierarchical architecture for a hierarchical wafer lifecycle prediction method according to a second embodiment of the present invention.

(d) Life cycle domain

As shown in Figure 2, the total life cycle LT _T is first measured in the wafer process. Then one of the life cycle of the internal total life cycle with an external LT _ID lifecycle LT _ED is parsed by the total life cycle LT _T out, wherein the internal LT _ID life cycle is determined by total internal factors in the life cycle of LT _T The external life cycle LT _ED is determined by external factors in the total life cycle LT _T . As shown in Fig. 2, the internal life cycle LT _ID and the external life cycle LT _ED belong to a life cycle domain, similar to the situation when the yield is predicted. Please also refer to FIG. 3, which is a schematic diagram of the relationship between the lifetime of the wafer and the Vary Rate of the wafer, wherein the relationship between the life cycle of the wafer and the rate of change forms a normal distribution ( Normal Distribution), where the above internal factors correspond to a longer life cycle in the wafer, and external factors correspond to shorter life cycles in the wafer.

(e) Integral domain

By using the three sigma binary analysis method, the internal life cycle LT _ID is converted into a system wafer acceptance test integral value λ _{SS , WAT} to collect the system wafer acceptance test integral value λ _{SS , WAT} distribution The value within three standard deviations of its mean (Mean).

The external life cycle LT _{ED is} also converted to a system defect density integral value λ _{SS , DD} and a random defect density integral value λ _{RR , DD} by using a three sigma binary analysis method. The system wafer acceptance test integral value λ _{SS , WAT} , the system defect density integral value λ _{SS , DD} , and the random defect density integral value λ _{RR, DD} belong to the integral domain as shown in FIG. 2 .

(f) Electrical/layout domains, metering/defective domains, and mechanical sensor domains

Similar to the yield prediction, the values of the electrical/layout domain, the metering/defective domain, and the mechanical sensor domain are also processed by principal component analysis or partial least squares analysis during the prediction of the life cycle, and the system wafers are accepted. The test integral values λ _{SS , WAT} , the system defect density integral value λ _{SS , DD} , and the random defect density integral value λ _{RR, DD} will also be individually described.

(f-1) System wafer acceptance test integral value λ _{SS , WAT}

Analysis or partial least squares analysis of the process, the wafer acceptance test system integrated value λ _{SS, WAT} used to determine a plurality of electrically belongs / wafer acceptance test WAT _SS layout parameter domain via the main component.

Since the system wafer accepts the test integral value λ _{SS , the WAT} is the integral of the wafer acceptance test parameter WAT _SS and the measurement parameter MET _SS , and the plurality of wafer acceptance test parameters WAT _{SS are} then converted into a plurality of The measurement parameter MET _SS belonging to the measurement/defect domain.

Finally, a plurality of metering parameters MET _SS are converted into a plurality of first system error detection and discrimination values FDC _SS1 belonging to the mechanical sensor domain.

(f-2) System defect density integral value λ _{SS , DD}

By using principal component analysis and partial least squares analysis, the system defect density integral value λ _{SS , DD} is used to determine a plurality of system critical region parameters CA _SS belonging to the electrical/layout domain.

Due to the system defect density integral value λ _{SS , DD} is the integral of the system key area parameter CA _SS and the system metering parameter DD _SS , and the plurality of system key area parameters CA _{SS are} then used to convert into a plurality of systems belonging to the metering/defective domain. Measurement parameter DD _SS .

Similarly, a plurality of defect density parameters DD _SS are converted into a plurality of second system error detection and discrimination values FDC _SS2 belonging to the mechanical sensor domain by principal component analysis or partial least squares analysis.

(f-3) Random defect density integral value λ _{RR, DD}

By using principal component analysis and partial least squares analysis, the random defect density integral value λ _{RR, DD} is used to determine a plurality of random key region parameters CA _RR belonging to the electrical/layout domain.

Due to the random defect density integral value λ _{RR, DD} is the integral of the random key area parameter CA _RR and the stochastic measurement parameter DD _RR , and the plurality of random key area parameters CA _{RR are} then used to convert into a plurality of random belonging to the measurement/defect field. Measurement parameter DD _RR .

Similarly, a plurality of random defect density parameters DD _RR are converted into a plurality of system error detection and discrimination values FDC _RR belonging to the mechanical sensor domain by principal component analysis or partial least squares analysis.

The life of the wafer can be realized after obtaining a plurality of first system error detection and discrimination values FDC _SS1 , a plurality of second system error detection and discrimination values FDC _SS2 , and a plurality of system error detection and discrimination values FDC _RR The cycle prediction model and the improvement of the wafer process accordingly.

Similar to the yield prediction, the hierarchical architecture disclosed in Figure 2 is implemented layer by layer and top to bottom.

Please refer to FIG. 4, which is a flow chart of a method for predicting the rate of the layered wafer according to the first embodiment of the present invention. The hierarchical wafer yield prediction method includes the following steps:

Step 102: measuring the total yield Y _T ;

Step 104: Determine the system yield Y _S and the random yield Y _R according to the total yield Y _T ;

Step 106: Determine a system wafer acceptance test integral value λ _{S , WAT} , a system defect density integral value λ _{S , DD} , and a random defect density integral value λ _{R , DD} using a three sigma binary analysis method;

Step 108: Determine a plurality of wafer acceptance test parameters WAT _S , a plurality of system key area parameters CA _S , and a plurality of random key area parameters CA _R by using principal component analysis or partial least squares analysis;

Step 110: determining a plurality of metering parameters MET _S , a plurality of system defect density parameters DD _S , and a plurality of random defect densities DD _R ;

Step 112: Determine a plurality of first system error detection and discrimination values FDC _S1 , a plurality of second system error detection and discrimination values FDC _S2 , and a plurality of random error detection and discrimination values FDC _R .

Please refer to FIG. 5, which is a schematic flowchart of a hierarchical wafer life cycle prediction method according to a second embodiment of the present invention. The steps shown in Figure 5 are as follows:

Step 202: Measure the total life cycle LT _T ;

Step 204: Determine an internal life cycle LT _ID and an external life cycle LT _ED according to the total life cycle LT _T ;

Step 206: Determine the system wafer acceptance test integral value λ _{SS , WAT} , the system defect density integral value λ _{SS , DD} , and the random defect density integral value λ _{RR , DD} using the three sigma binary analysis method;

Step 208: using principal component analysis or partial least squares analysis, determining a plurality of wafer acceptance test parameters WAT _SS , a plurality of system key region parameters CA _SS , and a plurality of random key region parameters CA _RR ;

Step 210: Determine a plurality of measurement parameters MET _SS , a plurality of system defect density parameters DD _SS , and a plurality of random defect density parameters DD _RR ;

Step 212: Determine a plurality of first system error detection and discrimination values FDC _SS1 , a plurality of second system error detection and discrimination values FDC _SS2 , and a plurality of system error detection and discrimination values FDC _RR .

Figures 4 and 5 are a summary of the methods for implementing the hierarchical architecture shown in Figures 1 and 2 to predict the yield or life cycle of the wafer. However, the various embodiments formed by the steps of Figure 4 or Figure 5 in a reasonable combination or arrangement, or the various limitations mentioned in this specification are added to the steps of Figure 4 or Figure 5, should still It is considered as an embodiment of the present invention.

The hierarchical wafer yield prediction method and the hierarchical wafer life cycle prediction method disclosed by the present invention can reduce the noise in the wafer yield prediction model or the life cycle prediction model to improve the yield prediction model. Or the accuracy of the life cycle prediction model, while avoiding the problem of the prior art that the intermediate programs are highly correlated with each other and cannot effectively eliminate noise.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

102, 104, 106, 108, 110, 112, 202, 204, 206, 208, 210, 212. . . step

1 is a schematic diagram of a hierarchical architecture used in a hierarchical wafer yield prediction method according to a first embodiment of the present invention.

2 is a schematic diagram of a hierarchical architecture for a hierarchical wafer lifecycle prediction method of the present invention, in accordance with a second embodiment of the present invention.

Figure 3 is a schematic diagram of the relationship between the life cycle of a wafer and the rate of change of the wafer.

4 is a flow chart showing a method for predicting a slice wafer yield according to a first embodiment of the present invention.

FIG. 5 is a schematic flow chart of a hierarchical wafer life cycle prediction method according to a second embodiment of the present invention.

102, 104, 106, 108, 110, 112. . . step

Claims (16)

A hierarchical wafer yield prediction method includes: measuring a total yield of a plurality of wafers; determining a systematic yield and a random good according to the total yield Rate (Random Yield); based on the system yield, and using 3-Sigma Binomial Analysis to determine at least one system integral value; determining at least one system error detection based on the at least one system integral value And a systematic fault detection and classification value; according to the random rate, a three-sigma dichotomy method is used to determine a random integral value; and a random error detection and discrimination value is determined according to the random integral value. The method of claim 1, wherein the at least one system error detection and discrimination value is determined according to the at least one system integral value is Principal Component Analysis (PCA) and partial least squares analysis (Partial Least Square). Analysis, PLS analysis), and determining the at least one system error detection and discrimination value according to the at least one system integral value. The method of claim 2, wherein determining the at least one system integral value according to the system yield is to determine a system Wafer Acceptance Test (WAT) integral value and a system defect according to the system yield. Defect Density (DD) integral value. The method of claim 3, wherein determining the at least one system error and the authentication value according to the at least one system integration value is to determine a first system error and an authentication value according to the system wafer acceptance test integration value, and A second system error and an authentication value are determined based on the system defect density integral value. The method of claim 4, wherein determining the first system error and the authentication value according to the system wafer acceptance test integral value comprises: determining a wafer acceptance test parameter according to the system wafer acceptance test integral value Determining a Metrology parameter according to the wafer acceptance test parameter; and determining the first system error and the identification value according to the measurement parameter; wherein the system wafer acceptance test integral value is the wafer acceptance test The integral of the parameter with this measurement parameter. The method of claim 4, wherein determining the second system error and the authentication value according to the system defect density integral value comprises: determining a system critical area parameter according to the system defect density integral value; The key area parameter determines a system defect density parameter; and the second system error and the discrimination value are determined according to the system defect density parameter; wherein the system defect density integral value is an integral of the system key area parameter and the system defect density parameter. The method of claim 1, wherein the random error detection and discrimination value is determined according to the random integral value is a principal component analysis and a partial least squares analysis, and the random error detection and discrimination is determined according to the random integral value. value. The method of claim 7, wherein determining the random error detection and discriminating value according to the random integral value comprises: determining a random key region parameter according to the random integral value; determining a random defect density parameter according to the random key region parameter And determining the random error detection and discrimination value according to the random defect density parameter; wherein the random integral value is an integral of the random key region parameter and the random defect density parameter. A hierarchical wafer life cycle prediction method includes: measuring a total life cycle of a plurality of wafers; determining an internal life cycle (Intrinsic Lifetime) and an external life cycle (Extrinsic Lifetime) according to the total life cycle According to the external life cycle, and using the three sigma binary analysis method to determine at least one external integral value; determining at least one external error detection and discrimination value according to the at least one external integral value; according to the internal life cycle, and A three-sigma dichotomy method is used to determine an internal integral value; and an internal error detection and discrimination value is determined based on the internal integral value. The method of claim 9, wherein the at least one external error detection and discrimination value is determined according to the at least one external integration value is a principal component analysis and a partial least squares analysis, and the at least one external integration value is determined according to the at least one external integration value. At least one external error detection and discrimination value. The method of claim 10, wherein the at least one external integral value is determined according to the external life cycle to determine a system defect density integral value and a random defect density integral value according to the system life cycle. The method of claim 11, wherein the at least one external error and the authentication value are determined according to the at least one external integrated value to determine a first external error and the authentication value according to the system defect density integral value, and according to the random The defect density integral value determines a second external error and the discrimination value. The method of claim 12, wherein determining the first system error and the authentication value according to the system wafer acceptance test integral value comprises: determining a system key region parameter according to the system defect density integral value; The regional parameter determines a system defect density parameter; and the first external error and the discrimination value are determined according to the system defect density parameter; wherein the system defect density integral value is an integral of the system key region parameter and the system defect density parameter. The method of claim 12, wherein determining the second external error and the discriminating value according to the random defect density integral value comprises: determining a random key region parameter according to the random defect density integral value; determining according to the random key region parameter a random defect density parameter; and determining the second external error and the discrimination value according to the random defect density parameter; wherein the random defect density integral value is an integral of the random key region parameter and the random defect density parameter. The method of claim 9, wherein the internal integrated value determines the internal error detection and discrimination value is a principal component analysis and a partial least squares analysis, and the internal error detection and the identification value are determined according to the internal integration value. . The method of claim 15, wherein determining the internal error detection and discrimination value according to the internal integration value comprises: determining a wafer acceptance test parameter according to the internal integration value; determining one according to the wafer acceptance test parameter The measurement parameter; and determining the internal error detection and discrimination value according to the measurement parameter; wherein the internal integration value is an integral of the wafer acceptance test parameter and the measurement parameter.