TWI518793B - Nmos transistor with low trigger voltage and method of manufacturing nmos transistor with low trigger voltage - Google Patents

Description

N-type MOS transistor with low trigger voltage and manufacturing method thereof

The present invention relates to a metal-oxide-semiconductor transistor, and more particularly to an n-type metal-oxide-semiconductor (hereinafter referred to as NMOS) transistor having a low trigger voltage and Process method.

In today's applications of semiconductor components, MOS transistors are the most widely used and continue to receive attention. Common MOS transistors include vertical double-diffused MOS (VDMOS) transistors and laterally-diffused MOS (LDMOS) transistors. LDNMOS transistors are widely used in high-voltage operating environments due to their high operating bandwidth and operating efficiency, as well as planar structures that are easily integrated with other integrated circuits, such as CPU power supply. ), power management systems, AC/DC converters, and power amplifiers in high or high frequency bands. The operating characteristics of LDNMOS transistors are similar to those of general NMOS transistors, except that the N-type drift region of the NMOS transistor has a high doping concentration, the N-type drift region of the LDNMOS has a low doping concentration, and the N-type drift region of the LDNMOS The drift region withstands most of the voltage drop between the gate and the drain, thereby reducing the high electric field between the gate and the drain, causing the LDNMOS transistor to have a high breakdown voltage.

Please refer to FIG. 1 , which is a schematic diagram of a conventional open-pole circuit 100 . As shown in FIG. 1, the internal circuit 10 in the open-drain circuit 100 is connected to an output driving element 11. Generally, the effect of electro-discharge is caused by the input terminal 15, the output terminal 16, and the high. The voltage terminal contact 13 and the low voltage terminal 14 are generated. In order to avoid damage to the output driving element 11 caused by electrostatic discharge, the open-pole circuit 100 incorporates a clamper 12 having a low trigger voltage to protect the output driving element 11 Since the trigger voltage is generally lower than the output driving element 11, the above electrostatic discharge flows to the clamper 12 without affecting the output driving element 11.

The clamp is usually fabricated in an NMOS transistor. The NMOS transistor with a low trigger voltage has better clamp characteristics, that is, the NMOS transistor can introduce electrostatic discharge more quickly and protect other circuit components. The current way to reduce the trigger voltage is generally to reduce the NMOS breakdown voltage by reducing the channel length of the NMOS transistor. However, reducing the channel length of the NMOS transistor also causes a leakage current effect on the NMOS transistor, which in turn affects the reliability of the NMOS transistor and the characteristics of the clamp.

An embodiment of the present invention provides a method of forming an N-type MOS transistor, the method comprising: forming a P-type substrate; forming an N-type well on the P-type substrate; forming an N-type on the N-type well a drift region; forming an n+ drain on the N-type drift region; forming a plurality of first contacts along the longitudinal direction on the n+ drain; forming a P-type substrate on the N-well; and forming the P-type substrate on the P-type substrate Forming a source, the source includes a plurality of n+ doped regions and at least one p+ doped region, the plurality of n+ doped regions and at least one p+ doped region are arranged along the longitudinal direction; and the plurality of n+ doped Forming a plurality of second contacts on the impurity region and the at least one p+ doping region; forming a polysilicon gate on the P-type substrate; and forming a gate oxide layer between the polysilicon gate and the source.

Another embodiment of the present invention provides an N-type MOS transistor including a P-type substrate; an N-type well formed on the P-type substrate; and an N-type drift region formed on the N-type well; An n+ drain is formed on the N-type drift region; a plurality of first contacts are arranged along the longitudinal direction on the n+ drain; a P-type substrate is formed on the N-well; a source is formed in The P-type substrate, the source includes a plurality of n+ doped regions and at least one p+ doped region, and the plurality of n+ doped regions and the at least one p+ doped region are arranged along the longitudinal direction; And a gate electrode formed on the P-type substrate; and a gate oxide layer formed on the polysilicon gate and Between the sources.

Through the NMOS transistor provided by the invention and the manufacturing method thereof, the NMOS transistor can have a low trigger voltage without changing the breakdown voltage, so as to be a better performance clamper.

2 and 3, FIG. 2 is a schematic view of the NMOS transistor 200 of the present invention, and FIG. 3 is a cross-sectional view of the NMOS transistor 200 taken along line 2-3' of FIG. The NMOS transistor 200 can be an LDNMOS transistor, and the NMOS transistor 200 includes a P-type substrate 20, a deep N-type well 21 formed on the P-type substrate 20, and an N-type drift formed on the deep N-type well 21. a region 22, a P-type substrate 205 formed on the N-type well 21, and a source 23 formed on the P-type substrate 205. The source 23 in FIGS. 2 and 3 includes a plurality of n+ doped regions 28 And at least one first p+ doping region 26, and each of the n+ doping regions 28 and the first p+ doping region 26 form a contact point 204. A polysilicon gate 24 is further formed on the P-type substrate 20, and a gate oxide layer 206 is formed between the source and the source. An n+ drain 202 is formed on each of the N-type drift regions 22, and a plurality of contact points 210 arranged in a longitudinal direction are formed thereon, that is, arranged along the y-axis perpendicular to the x-axis as shown in FIG. 2, and n+ A first field oxide layer 207 is formed between the drain and the polysilicon gate 24. In addition, a ring-shaped second p+ doping region 29 is formed on the P-type substrate 20, and a plurality of contact points 212 arranged in a ring shape are formed thereon, and the second p+ doping region 29 serves as an annular protection region (guard). Ring) protects the components on the P-type substrate 20, and the second p+ doping region 29 is separated from the N-type drift region 22 by a second field oxide layer 208.

The n+ doping region 28 of the source 23 and the first p+ doping region 26 are arranged along the longitudinal direction, that is, arranged along the y axis as shown in FIG. 2, by such a longitudinal arrangement, the n+ doping region 28 and The distance between the contact points 204 of the first p+ doped region 26 can be increased in the longitudinal direction. The NMOS transistor 200 described in the embodiments of FIGS. 2 and 3 has a plurality of contact points 204 on the doped regions on the source 23 which are separated from each other. Therefore, when the distance between the n+ doping region 28 and the contact point 204 of the first p+ doping region 26 increases, the internal resistance 203 of the source 23 and the N-type drift region 22 increases, and the NMOS transistor The trigger voltage is also reduced.

Please refer to Fig. 4. Fig. 4 is a graph showing the current and the trigger voltage of an NMOS transistor operating at a voltage of 40 volts. From the curve of Fig. 4, it can be seen that under the same current condition, when n+ doping The larger the pitch of the contact point 204 of the region 28 and the first p+ doped region 26, the smaller the trigger voltage of the NMOS transistor.

Please refer to FIG. 5. FIG. 5 is a schematic diagram showing the adjustment of the contact pitch of the NMOS transistor 200 shown in FIG. The size of the internal resistance 503 depends on the distance between the first effective contact point 501 and the second effective contact point 502. Since the distance between the first effective contact point 501 and the second effective contact point 502 is small in this embodiment, the internal resistance is 503 is also small, so the trigger voltage of the NMOS transistor can only be reduced slightly.

Please refer to FIG. 6. FIG. 6 is another schematic diagram of adjusting the contact pitch of the NMOS transistor 200 of FIG. The size of the internal resistance 603 depends on the distance between the first effective contact point 601 and the second effective contact point 602. Because the distance between the first effective contact point 601 and the second effective contact point 602 is large in this embodiment, the internal resistance is 603 is also large, so the trigger voltage of the NMOS transistor can be greatly reduced.

In summary, the device and method provided by the present invention, in particular, using the n+ doping region 28 of the source 23 and the first p+ doping region 26 arranged along the longitudinal direction, so that the n+ doping region 28 and the The distance between the contact points 204 of a p+ doped region 26 can be increased in the longitudinal direction, and the contact pitch of the source 23 of the NMOS transistor 200 can be increased, thereby reducing the trigger voltage of the NMOS transistor 200. That is, through the device and method provided by the present invention, an NMOS transistor with a low trigger voltage can be obtained without changing the breakdown voltage, and can be used as a better performance clamp to protect the required circuit.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10, 503, 603. . . Internal circuit

11. . . Output drive component

12. . . Clamp

13. . . High voltage termination point

14. . . Low voltage termination point

15. . . Input termination

16. . . Output contact

20. . . P-type substrate

twenty one. . . Deep N well

twenty two. . . N-type drift zone

twenty three. . . Source

twenty four. . . Polycrystalline gate

26. . . First p+ doped region

28. . . n+ doped region

29. . . Second p+ doped region

200. . . NMOS transistor

202. . . N+ bungee

203, 503, 603. . . Internal resistance

204, 210, 212‧‧‧ touch points

205‧‧‧P type substrate

206‧‧‧ gate oxide layer

207‧‧‧First oxide layer

208‧‧‧Second oxide layer

501, 601‧‧‧ first effective contact point

502, 602‧‧‧ second effective contact point

Figure 1 is a schematic diagram of a conventional open-circuit circuit;

2 is a schematic view of an NMOS transistor of the present invention;

Figure 3 is a plan view of the NMOS transistor of Figure 2 taken along line 3-3' of Figure 2;

Figure 4 is a graph showing the current and trigger voltage of the NMOS transistor according to Figure 2;

Figure 5 is a schematic view showing the adjustment of the contact pitch of the NMOS transistor according to Figure 2;

Fig. 6 is another schematic view showing the adjustment of the contact pitch of the NMOS transistor according to Fig. 2.

20. . . P-type substrate

twenty one. . . Deep N well

twenty two. . . N-type drift zone

twenty three. . . Source

twenty four. . . Polycrystalline gate

26. . . First p+ doped region

28. . . n+ doped region

29. . . Second p+ doped region

200. . . NMOS transistor

202. . . N+ bungee

203. . . Internal resistance

204, 210, 212. . . Contact point

205. . . P type substrate

206. . . Gate oxide layer

207. . . First oxide layer

208. . . Second oxide layer

Claims (16)

A method of forming an N-type gold oxide semiconductor (NMOS), the method comprising: forming a P-type substrate; forming an N-type well on the P-type substrate; forming an N-type drift region on the N-type well; Forming an n+ drain on the drift region; forming a plurality of first contacts along the longitudinal direction on the n+ drain; forming a P-type substrate on the N-well; forming a source on the P-type substrate, The source includes a plurality of n+ doped regions and at least one p+ doped region, the plurality of n+ doped regions and at least one p+ doped region are arranged along the longitudinal direction; and the plurality of n+ doped regions and the at least one Forming a plurality of second contacts on the p+ doped region, wherein the second contacts are separated from each other independently; forming a polysilicon gate on the P-type substrate; and forming a gate between the polysilicon gate and the source A gate oxide layer. The method of claim 1, further comprising forming a field oxide layer between the n+ drain and the polysilicon gate. The method of claim 1, wherein the plurality of second contacts are formed on the plurality of n+ doped regions and the at least one p+ doped region, and the at least one second is formed on each of the n+ doped regions. contact. The method of claim 1, further comprising forming a P-type well surrounding the N-type well on the P-type substrate. The method of claim 4, further comprising forming a p+ guard ring on the P-well. The method of claim 5, further comprising forming a plurality of third contacts on the p+ guard ring. The method of claim 5, further comprising forming a field oxide layer between the p+ guard ring and the N-well. The method of claim 1, wherein the N-type well is formed on the P-type substrate to form a deep N-type well on the P-type substrate. An N-type gold-oxide semiconductor (NMOS) comprising: a P-type substrate; an N-type well formed on the P-type substrate; an N-type drift region formed on the N-type well; and an n+ drain formed on The N-type drift region; a plurality of first contacts arranged along the longitudinal direction on the n+ drain; a P-type substrate formed on the N-type well; and a source formed on the P-type substrate, the The source includes a plurality of n+ doped regions And at least one p+ doped region, wherein the plurality of n+ doped regions and the at least one p+ doped region are arranged along the longitudinal direction; a plurality of second contacts formed in the plurality of n+ doped regions and the at least a p+ doped region, wherein the second contacts are separated from each other; a polysilicon gate is formed on the P-type substrate; and a gate oxide layer is formed on the polysilicon gate and the source between. The N-type metal oxide semiconductor (NMOS) according to claim 9, further comprising a field oxide layer formed between the n+ drain and the polysilicon gate. The N-type metal oxide semiconductor (NMOS) according to claim 9, wherein at least one second contact is formed on each of the n+ doping regions. The N-type metal oxide semiconductor (NMOS) according to claim 9 further comprising a P-type well formed on the P-type substrate and surrounding the N-type well. The N-type metal oxide semiconductor (NMOS) as claimed in claim 12, further comprising a p+ guard ring formed on the P-type well. The N-type metal oxide semiconductor (NMOS) according to claim 13 further comprising a plurality of third contacts formed on the p+ guard ring. An N-type metal oxide semiconductor (NMOS) as described in claim 13 further comprising a field oxidation A layer is formed between the p+ guard ring and the N-type well. An N-type metal oxide semiconductor (NMOS) according to claim 9, wherein the N-type well is a deep N-type well.