TWI518689B - Non-volatile memory device having vertical structure and method of operating the same - Google Patents

Description

Non-volatile memory component with vertical structure and method of operation thereof [Cross-Reference to Related Applications]

This U.S. non-provisional patent application is part of the continuation of U.S. Patent Application Serial No. 12/658,072, filed on Feb. 2, 2010, which is hereby filed on the The Korean Patent Application No. -0083148 and the Korean Patent Application No. 10-2010-0006475, filed on Jan. 25, 2010, the entire content of which is hereby incorporated by reference.

The inventive concept relates to semiconductor components, and more particularly to non-volatile memory components having a vertical structure and methods of operation thereof.

Although the size of electronic components has continued to decrease, it still needs to process a large amount of data. Therefore, in order to reduce the size while maintaining or improving the processing capability, the non-volatile memory elements used in such electronic components need to be reduced in size while increasing their integration degree. For this reason, non-volatile memory elements having a vertical structure have been considered in place of non-volatile memory elements having a conventional flat structure. However, non-volatile memory elements having a vertical structure are relatively complicated to manufacture, and thus their reliability tends to be lower than that of conventional memory elements having a flat structure.

According to the present invention, there is provided a non-volatile memory element having a vertical structure and a method of operating the same that enhances the reliability of the memory element.

In accordance with an aspect of the inventive concept, a method of operating a non-volatile memory component is provided. The method includes applying a turn-on voltage to each of a first string selection transistor and a second string selection transistor of a first NAND string; applying a first voltage and a second voltage to a second NAND string, respectively a third string selection transistor and a fourth string selection transistor; and a high voltage applied to the word lines connected to the memory cells of the first NAND string and the second NAND string.

The second voltage may have a higher level than the first voltage.

The first voltage may have a level lower than a ground voltage.

The second voltage may have a lower level than a threshold voltage of the fourth string of selected transistors.

The third string selection transistor is connectable between the fourth string selection transistor and a bit line corresponding to the second NAND string.

The method of operating a non-volatile memory component can further include: applying a second high voltage to a dummy cell between the first to fourth string selection transistors and the memory cell, wherein the second high voltage has a low At the level of the high voltage.

According to another aspect of the inventive concept, a non-volatile memory element is provided. The non-volatile memory component includes: an array of memory cells; and peripheral circuitry configured to access the array of memory cells. The memory cell array includes a substrate and a plurality of memory cell groups arranged in columns and rows on the substrate. Each memory cell group includes a plurality of memory cells stacked in a direction crossing the substrate; a plurality of first selected transistor groups respectively provided between the substrate and the plurality of memory cell groups And a plurality of second selected transistor groups respectively provided on the plurality of memory cell groups. The peripheral circuitry can be configured to independently drive a second selection transistor of a second selected transistor population corresponding to the unselected memory cell population of the plurality of memory cell groups during the stylizing operation.

The peripheral circuitry can be further configured to drive the second selected transistor of the second selected transistor group at a different voltage during a stylizing operation.

During a stylization operation, a specific second selection transistor of the second selected transistor group may be driven by a first voltage, and the second selected transistor group is provided to the specific second selection transistor and the Another second selection transistor between the unselected memory cell groups can be driven by a second voltage that is higher than the first voltage.

According to still another aspect of the inventive concept, a memory system is provided. The memory system includes: a non-volatile memory component; and a controller configured to control the non-volatile memory component. The non-volatile memory component includes an array of memory cells and peripheral circuitry configured to access the array of memory cells. The memory cell array includes a plurality of memory cell strings having a 3-dimensional structure. Each memory cell string includes at least two first selection transistors provided on one side and at least two second selection transistors provided on the other side. The peripheral circuitry can be configured to drive the at least two second selection transistors of the unselected memory cell strings of the plurality of memory cell strings at different voltages during a stylizing operation.

Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention conveys the inventive concept to those skilled in the art. In the figures, the dimensions of each component can be exaggerated for clarity.

The terms used in the following examples are to be understood as being generally known in the art to which the concept of the invention pertains. For example, the term "at least one" includes one or more of the associated listed items, and is intended to include both the singular and plural.

It will be understood that, although the terms first, second, etc. are used herein to describe various components, such components are not limited by such terms. These terms are used to distinguish one component from another, but do not imply a required sequence of components. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when a component is referred to as "on another component" or "connected" or "coupled" to another component, it can be directly on the other component or connected or coupled to the other A component, or an interventional component may be present. In contrast, when a component is referred to as being "directly on another component" or "directly connected to" or "directly coupled" to another component, there is no intervening component. Other words used to describe the relationship between the components should be interpreted in a similar manner (for example, "between", "directly between", "adjacent to", "directly adjacent", etc.).

The terminology used herein is for the purpose of describing particular embodiments and is not intended to As used herein, the singular forms " " It will be further understood that the terms "including" and / or "comprising" are used in the context of the specification of the features, steps, operations, components and/or parts of the present invention, but do not exclude one or more other features, steps, operations, The presence or addition of components, parts, and/or groups thereof.

Spatially relative terms such as "below", "under", "lower", "above", "upper" and similar terms may be used to describe a component and / or feature and another component and / Or the relationship of features, such as illustrated in the figure. It will be appreciated that the spatially relative terms are intended to encompass different orientations of the elements in use and/or operation in addition to those illustrated in the figures. For example, if the elements in the figures are turned over, the components described as "under other components or features" and/or "under other components or features" will be "above" the other components or features. The elements may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatially relative terms used herein are interpreted accordingly.

1 is a circuit diagram of a non-volatile memory element in accordance with an embodiment of the inventive concept. Referring to Fig. 1, a NAND string NS may extend in a vertical direction, that is, it may have a vertical structure with respect to a substrate (not shown). The NAND string NS may have at least one pair of string selection transistors TS1 and TS2, a plurality of memory cells MC, and at least one pair of ground selection transistors TG1 and TG2. The bit line BL may be connected to one end of the NAND string NS, and the common source line CSL may be connected to the other end of the NAND string NS.

The memory cells MC can be arranged in series in the vertical direction. The memory unit MC can store data. A plurality of word lines WL0, WL1 to WLn-1, and WLn (where "n"+1 is the number of word lines) may be coupled to the memory cells MC, respectively, to control the memory cells MC. The total number of memory cells MC can be determined based on the capacity of the non-volatile memory components.

The string selection transistors TS1 and TS2 may be disposed near one end of the memory cell MC. For example, the string selection transistors TS1 and TS2 may be located between the bit line BL and the memory cell MC, and may be connected in series to the memory cell MC. The string selection transistors TS1 and TS2 can control the signal exchange between the bit line BL and the memory cell MC. The first string selection line SSL1 may be coupled to the first string selection transistor TS1, and the second string selection line SSL2 may be coupled to the second string selection transistor TS2. Therefore, the first string selection transistor TS1 and the second string selection transistor TS2 can be operated separately and independently.

At least one pair of first ground selection transistor TG1 and second ground selection transistor TG2 may be disposed adjacent to each other at one end of the NAND string NS, the one end and the string selection transistor TS1 at the other side of the memory cell MC TS2 is relative. For example, the ground selection transistors TG1, TG2 may be located between the common source line CSL and the memory unit MC, and may be connected in series with the memory unit MC. The first ground selection line GSL1 may be coupled to the first ground selection transistor TG1, and the second ground selection line GSL2 may be coupled to the second ground selection transistor TG2. Therefore, the first ground selection transistor TG1 and the second ground selection transistor TG2 can be separated and operated independently. In a modified example of this embodiment, the first ground selection transistor TG1 and the second ground selection transistor TG2 can be coupled to a single ground selection line GSL.

In the following, embodiments of an operational method that can be used with this embodiment of a non-volatile memory element will be described.

In this example, for a stylized operation, 0 V or an operating voltage can be applied to the bit line BL, and 0 V can be applied to the common source line GSL. When 0 V is applied to the bit line BL, this NAND string NS is selected for stylization. However, when an operating voltage is applied to the bit line BL, stylization of this NAND string NS is prevented by channel boosting.

A stylized voltage can be applied to the selected memory cells in the memory cell MC, and a pass voltage can be applied to the remaining memory cells. The transfer voltage can be lower than the stylized voltage and can be higher than the threshold voltage of the memory cell MC. The stylized voltage can be selected to inject charge into the memory cell MC by F-N tunneling.

A turn-off voltage (off voltage) may be applied to the first ground selection line GSL1 and the second ground selection line GSL2. A first voltage may be applied to the second string select line SSL2 directly adjacent to the memory cell MC, and a second voltage may be applied to the first string select line SSL1 directly adjacent to the bit line BL.

The second voltage can be selected to be as low as possible to reduce the off current while the first string of selected transistors is turned on. For example, the second voltage may be higher than or equal to the threshold voltage of the first string selection transistor TS1 and may be equal to the aforementioned operating voltage.

The first voltage can be selected to reduce the voltage difference between the second string selection transistor TS2 and the memory cell MC adjacent thereto. For example, the first voltage can be substantially equal to the transfer voltage. Therefore, by setting the first voltage to be higher than the second voltage, by reducing the difference between the transfer voltage and the first voltage, generation of the second string selection transistor TS2 adjacent to the memory cell MC can be prevented. Leakage current and thus reduced channel boost efficiency.

Therefore, in this embodiment of the method of operating the non-volatile memory device, the off current and the drain current can be simultaneously reduced by independently operating the first string selection transistor TS1 and the second string selection transistor TS2. The function for preventing leakage will be described in more detail with reference to FIGS. 2 to 4.

To perform the read operation, a read voltage can be applied to the bit line BL, and an "on" voltage can be applied to the string selection lines SSL1 and SSL2 and the ground selection lines GSL1 and GSL2. The reference voltage may be applied to the memory cell MC selected from the memory cell MC, and the transfer voltage may be applied to other memory cells.

To perform the erase operation, an erase voltage may be applied to the body of the memory cell MC, and 0 V may be applied to the word lines WL0, WL1 to WLn-1, and WLn. Therefore, the data can be erased from the memory cell MC at the same time.

2 is a circuit diagram of a non-volatile memory element in accordance with another embodiment of the inventive concept. The non-volatile memory component of Figure 2 can correspond to an array of a plurality of non-volatile memory components such as that shown in Figure 1. Therefore, a description of the operation or characteristics of the same components as in FIG. 1 will not be provided herein.

Referring to FIG. 2, a plurality of NAND strings NS11, NS12, NS21, NS22 having a vertical structure may be configured in a matrix configuration. The first bit line BL1 may be commonly connected to one end of each of the NAND strings NS11, NS21 disposed in the first row, and the second bit line BL2 may be commonly connected to the NAND string disposed in the second row One end of each of NS12 and NS22. The common source line CSL may be commonly connected to the other end of the NAND strings NS11, NS12, NS21, NS22 opposite to the first bit line BL1 and the second bit line BL2. The number of NAND strings NS11, NS12, NS21, NS22 and the number of bit lines BL1, BL2 are illustrative and not limiting the scope of this embodiment or the invention.

The word lines WL0, WL1, ... WLn-1, WLn can be commonly connected to the memory cells MC disposed in the respective layers thereof. The first string selection line SSL1 may be commonly coupled to the first string selection transistor TS1 of the NAND strings NS11, NS12 disposed on the first column. The second string selection line SSL2 may be commonly coupled to the second string selection transistor TS2 of the NAND strings NS11, NS12 disposed in the first column. The third string selection line SSL3 may be commonly coupled to the first string selection transistor TS1 of the NAND strings NS11, NS12 disposed in the second column. The fourth string selection line SSL4 may be commonly coupled to the second string selection transistor TS2 of the NAND strings NS11, NS12 disposed in the second column.

The first ground selection line GSL1 may be commonly coupled to the first ground selection transistor TG1 of the NAND strings NS11, NS12 disposed on the first column. The second ground selection line GSL2 may be commonly coupled to the second ground selection transistor TG2 of the NAND strings NS11, NS12 disposed in the first column. The third ground selection line GSL3 may be commonly coupled to the first ground selection transistor TG1 of the NAND strings NS11, NS12 disposed on the second column. The fourth ground selection line GSL4 may be commonly coupled to the second ground selection transistor TG2 of the NAND strings NS11, NS12 disposed in the second column.

To perform the stylization operation, 0 V can be applied to the bit line selected from the bit lines BL1 and BL2, and the "on" voltage (on voltage) can be applied to the other bit line BL1 or BL2 for use. The channel is boosted. Moreover, the "on" voltage can be applied to the string selection line selected from the string selection lines SSL1 to SSL4, and the "off" voltage can be applied to the other string selection lines SSL1 and SSL2 or SSL3 and SSL4. Accordingly, NAND strings that are commonly connected to the selected location line and the string select lines from the NAND strings NS11, NS12, NS21, and NS22 can be selectively operated.

To perform the read operation, a read voltage may be applied to the bit line selected from the bit lines BL1 and BL2, and the other bit line BL1 or BL2 may float. Moreover, the "on" voltage can be applied to the string selection line selected from the string selection lines SSL1 to SSL4, and the "off" voltage can be applied to the other string selection lines SSL1 and SSL2 or SSL3 and SSL4. Accordingly, NAND strings that are commonly connected to the selected location line and the string select lines from the NAND strings NS11, NS12, NS21, and NS22 can be selectively operated.

To perform the erase operation, an erase voltage may be applied to the body of the memory cell MC, and 0 V may be applied to the word lines WL0, WL1 to WLn-1, and WLn. Therefore, data can be erased from the memory cells MC of the NAND strings NS11, NS12, NS21, and NS22 at the same time.

FIG. 3 illustrates voltage bias conditions when a stylization operation is performed in the memory device of FIG. In this stylized operation example, it is assumed that one of the memory cells arranged in the first NAND string NS11 in the first column is programmed. That is, it is assumed that the second NAND string NS disposed in the first column and the NAND and the NAND strings NS21 and NS22 disposed in the second column are prevented from being programmed.

Referring to FIG. 2 and FIG. 3, since the memory cells arranged in the first NAND string NS11 in the first column are programmed, the ground voltage Vss is supplied to the first bit line BL1 connected to the first NAND string NS11. . The first NAND string NS21 of the second column is also connected to the first bit line BL1 to which the ground voltage Vss is supplied.

Since the second NAND string NS12 disposed in the first column is prevented from being programmed, the power supply voltage Vcc is supplied to the second bit line BL2 connected to the second NAND string NS12. The second NAND string NS22 of the second column is also connected to the second bit line BL2 to which the power supply voltage Vcc is supplied.

Since the first NAND string NS11 of the first column is programmed, the turn-on voltage is supplied to the first string selection line SSL1 and the second string selection line SSL2 connected to the first NAND string NS11. The turn-on voltage may be a voltage for turning on the first string selection transistor TS1 and the second string selection transistor TS2 of the first NAND string NS11. For example, the turn-on voltage can be the power supply voltage Vcc.

The first string selection transistor TS1 and the second string selection transistor TS2 of the second NAND string of the first column are also connected to the first selection line SSL1 and the second selection line SSL2, respectively. Therefore, the first string selection transistor TS1 and the second string selection transistor TS2 of the second NAND string of the first column are turned on.

The first NAND string NS21 and the second NAND string NS22 of the second column are prevented from being programmed. For example, the off voltage is supplied to the third string selection line SSL3 and the fourth string selection line SSL4. The turn-off voltage is a voltage for disconnecting the first string selection transistor TS1 and the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22. For example, the disconnect voltage is the ground voltage Vss.

The program voltage Vpgm and the transfer voltage Vpass are supplied to the word lines WL0-WLn. For example, the stylized voltage Vpgm is supplied to a word line connected to the selected memory cell. The transfer voltage Vpass is supplied to a word line connected to an unselected memory cell. The stylized voltage Vpgm and the transfer voltage Vpass are high voltages in this embodiment, such as 8 volts or more.

Channels are formed in the memory cells of the first NAND string NS21 and the second NAND string NS22 disposed in the second column by the high voltages (Vpgm and Vpass) applied to the word lines WL0-WLn. The voltage of the formed channel is boosted by high voltages (Vpgm and Vpass). At this time, the ground voltage Vss is applied to the gates of the second string selection transistors TS2 of the first NAND string NS21 and the second NAND string NS22 arranged in the second column. Therefore, between the gate voltage (eg, the ground voltage Vss) of the second string selection transistor TS2 of the first NAND string NS1 and the second NAND string NS22 and the gate voltage (eg, the boosted channel voltage) The voltage difference can cause gate induced drain leakage (GIDL).

Further, the ground voltage Vss is applied to the second bit line BL2 connected to the second NAND string NS22 arranged in the second column. Due to the voltage difference between the bit line voltage (e.g., ground voltage Vss) connected to the second NAND string NS22 and the boosted channel voltage, additional leakage in the second NAND string NS22 may be generated.

To address the above limitations, a method of controlling the voltage of a string selection line of a memory device in accordance with an embodiment of the inventive concept is provided. Therefore, the leakage current can be controlled.

4 is a table showing the results of a method of controlling voltage in accordance with an embodiment of the inventive concept. Referring to FIGS. 2 and 4, the third voltage V3 is supplied to the third string selection line SSL3. That is, the third voltage V3 is applied to the gates of the first string selection transistors TS1 of the first NAND string NS21 and the second NAND string NS22 arranged in the second column. For example, the third voltage V3 is a voltage for disconnecting the first string selection transistor TS1 of the first NAND string NS21 and the second NAND string NS22.

The fourth voltage V4 is supplied to the fourth string selection line SSL4. That is, the fourth voltage V4 is applied to the gates of the second string selection transistors TS2 of the first NAND string NS21 and the second NAND string NS22 arranged in the second column. For example, the fourth voltage V4 is a voltage for disconnecting the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22.

When the difference between the fourth voltage V4 of the first NAND string NS21 and the second NAND string NS22 and the boosted channel voltage is reduced, the second string is selected in the first NAND string NS21 and the second NAND string NS22 The gate induced drain leakage (GIDL) that can be generated in TS2 is reduced. The level of the fourth voltage V4 is set to prevent or reduce the GIDL generated in the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22. For example, the fourth voltage V4 may have a higher level than the ground voltage Vss. For example, the fourth voltage V4 may have a level between the ground voltage Vss and the threshold voltage of the second string selection transistor TS2.

The lower the level of the third voltage V3, the less the charge that leaks to the bit lines BL1, BL2 via the first string selection transistor TS1 of the first NAND string NS21 and the second NAND string NS22. The level of the third voltage V3 may be set to prevent or reduce leakage of the first string selection transistor TS1 via the first NAND string NS21 and the second NAND string NS22. For example, the third voltage V3 may have a level lower than the ground voltage Vss.

As described above, if the voltage is supplied to a string selection line (for example, SSL3, SSL4) of a NAND string (for example, NS21, NS22) arranged in a different column from the programmed NAND string (for example, NS11). Quasi-controlled prevents or reduces leakage that can occur in NAND strings (eg, NS21, NS22) that are configured in a different column than the programmed NAND string (eg, NS11). Therefore, the reliability of the memory element is enhanced.

Moreover, while maintaining the amount of leakage, i.e., maintaining the reliability of the memory elements, the level of the voltage supplied to the word lines adjacent to the string selection transistors TS1, TS2 can be raised. That is, the voltage window adjacent to the word lines of the string selection transistors TS1, TS2 can be enhanced while maintaining the reliability of the memory elements.

In FIG. 4, the fourth voltage V4 has been described as being the off voltage. However, the fourth voltage V4 may be a voltage for turning on the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22 disposed in the second column. For example, the fourth voltage V4 may have a higher level than the threshold voltage of the second string selection transistor TS2 of the first NAND string NS21 and the second NAND string NS22. For example, the fourth voltage V4 may have a lower level than the transfer voltage Vpass. The fourth voltage V4 may have a level equal to the transfer voltage Vpass. The fourth voltage V4 may have a higher level than the transfer voltage Vpass.

5 is a schematic cross-sectional view taken along the direction of a bit line of the non-volatile memory element of FIG. 2, in accordance with an embodiment of the inventive concept. Referring to FIG. 5, the string selection gate electrode 166 may be connected to the first string selection line SSL1 and the second string selection line SSL2 via a contact plug 174, respectively. The ground selection gate electrode 162 may be connected to the first ground selection line GSL1 and the second ground selection line GSL2 via the contact plug 170, respectively.

6 is a schematic cross-sectional view taken along the direction of a bit line of the non-volatile memory element of FIG. 2, in accordance with another embodiment of the inventive concept. For simplicity of description, the NAND string array portion is omitted. Referring to FIG. 6, the ground selection gate electrode 162 is connected to the first ground selection line GSL1 and the second ground selection line GSL2 via contact plugs 170, 171 at one side of the NAND string array, respectively. Moreover, the control gate electrode 164 is connected to the word lines WL0-WLn via the contact plugs 172 at one side of the NAND string array, respectively. The string selection gate electrode 166 is connected to the first string selection line SSL1 and the second string selection line SSL2 via the contact plugs 175 and 176, respectively.

As an example, the string selection lines SSL1, SSL2, the word lines WL0-WLn, and the ground selection lines GSL1, GSL2 may be formed on the same layer. For example, string select lines SSL1, SSL2, word lines WL0-WLn, and ground select lines GSL1, GSL2 may be formed in the metal layer. For example, the string selection lines SSL1, SSL2, the word lines WL0-WLn, and the ground selection lines GSL1, GSL2 may be formed in the metal 0 layer or the metal 1 layer.

Figure 7 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile memory element of Figure 2, in accordance with yet another embodiment of the inventive concept. Comparing the schematic cross-sectional view of FIG. 7 with the schematic cross-sectional view of FIG. 6, in FIG. 7, the first string selection line SSL1 and the second string selection line SSL2 are formed in different layers. As an example, the first string selection line SSL1 is formed in a layer above the layer in which the second string selection line SSL2 is formed. For example, the first string selection line SSL1 is formed on the metal 1 layer. The second string selection line SSL2 is formed on the metal 0 layer.

Figure 8 is a schematic cross-sectional view taken along the direction of the bit line of the non-volatile memory element of Figure 2, in accordance with another embodiment of the inventive concept. Comparing the schematic cross-sectional view of FIG. 8 with the schematic cross-sectional view of FIG. 7, in FIG. 8, the word lines WL0-WLn, the ground selection lines GSL1, GSL2, and the first string selection line SSL1 are formed in the same layer. For example, the word lines WL0-WLn, the ground selection lines GSL1, GSL2, and the first string selection line are formed in the metal 1 layer. The second string selection line SSL2 is formed in a layer below the first string selection line SSL1. For example, the second selection line SSL2 is formed in the metal 0 layer.

9 is a schematic cross-sectional view taken along the direction of a bit line of the non-volatile memory element of FIG. 2, in accordance with another embodiment of the inventive concept. Comparing the schematic cross-sectional view of FIG. 9 with the schematic cross-sectional view of FIG. 8, in FIG. 9, the ground selection gate electrode 162 is connected to a single ground selection line GSL. That is, the ground selection transistors TG1, TG2 are connected in common to the ground selection line GSL.

The first string selection line SSL1, the word lines WL0-WLn, and the ground selection line GSL are formed in the same layer. For example, the first string selection line SSL1, the word lines WL0-WLn, and the ground selection line GSL are formed in the metal 1 layer. The second string selection line SSL2 is formed in a layer below the first string selection line SSL1. For example, the second selection line SSL2 is formed in the metal 0 layer.

Figure 10 is a circuit diagram of a non-volatile memory element in accordance with another embodiment of the inventive concept. Compared to the memory device shown in FIG. 2, a charge storage layer is provided for the select transistors TS1, TS2, TG1, TG2 (similar to the memory cells) of the memory device shown in FIG. That is, the selection transistors TS1, TS2, TG1, TG2 and the memory cells have the same structure. As an example, the charge storage layer provided to the select transistors TS1, TS2, TG1, TG2 and the memory cell can be a charge trap layer.

11 is a circuit diagram illustrating a non-volatile memory element in accordance with still another embodiment of the inventive concept. In contrast to the non-volatile memory component of FIG. 10, the non-volatile memory component of FIG. 11 further includes a dummy word line DWL between the string selection lines SSL1 to SSL4 and the normal word lines WL0 to WLn. In an embodiment, a dummy transfer voltage can be applied to the dummy word line DWL during the stylization operation. For example, the level of the dummy transfer voltage can be lower than the level of the normal transfer voltage.

In an embodiment, two or more dummy word lines may be provided between the string selection lines SSL1 to SSL4 and the normal word lines WL0 to WLn.

Figure 12 is a circuit diagram illustrating a non-volatile memory element in accordance with still another embodiment of the inventive concept. In contrast to the non-volatile memory component of FIG. 10, the non-volatile memory component of FIG. 12 further includes dummy word lines DWL between ground select lines GSL1 through GSL4 and normal word lines WL0 through WLn. In an embodiment, a dummy transfer voltage can be applied to the dummy word line DWL during the stylization operation. For example, the level of the dummy word line DWL can be lower than the level of the normal transfer voltage.

In an embodiment, two or more dummy word lines may be provided between the ground select lines GSL1 through GSL4 and the normal word lines WL0 through WLn.

FIG. 13 is a circuit diagram illustrating a non-volatile memory element in accordance with another embodiment of the inventive concept. Compared with the non-volatile memory component of FIG. 10, the non-volatile memory component of FIG. 13 further includes a first dummy word line DWL1 between the string selection lines SSL1 to SSL4 and the normal word lines WL0 to WLn and is located at ground. The second dummy word line DWL2 between the lines GSL1 to GSL4 and the normal word lines WL0 to WLn is selected. In an embodiment, a dummy transfer voltage may be applied to the first dummy word line DWL1 and the second dummy word line DWL2 during the stylizing operation. For example, the level of the dummy transfer voltage can be lower than the level of the normal transfer voltage.

In an embodiment, two or more dummy word lines may be provided between the string selection lines SSL1 to SSL4 and the normal word lines WL0 to WLn. In an embodiment, two or more dummy word lines may be provided between the ground select lines GSL1 through GSL4 and the normal word lines WL0 through WLn.

14 is a schematic block diagram illustrating a memory component 200 including non-volatile memory components in accordance with another embodiment of the inventive concept. Referring to FIG. 14, the NAND cell array 250 can be coupled to the core circuit unit 270. For example, NAND cell array 250 can include the non-volatile memory elements described with reference to Figures 1-13. Core circuit unit 270 can include control logic 271, column decoder 272, row decoder 273, sense amplifier 274, and/or page buffer 275.

Control logic 271 can be in communication with column decoder 272, row decoder 273, and/or page decoder 275. Column decoder 272 can communicate with NAND cell array 250 having a stacked structure via string select line SSL, word line WL, and/or ground select line GSL. Row decoder 273 can communicate with NAND cell array 250 via bit line BL. The sense amplifier 274 can be coupled to the row decoder 273 when the signal is output from the NAND cell array 250, and can be not coupled to the row decoder 273 when the signal is transferred to the NAND cell array 250.

For example, control logic 271 can transmit the column address signal to column decoder 272, and column decoder 272 can decode the column address signal and via string select line SSL, word line WL, and ground select line GSL The decoded column address signals are passed to the NAND cell array 250. Control logic 271 can transmit the row address signal to row decoder 273 or page buffer 275, and row decoder 273 can decode the row address signal and transmit the decoded row address signal via bit line BL to NAND cell array 250.

Signals of NAND cell array 250 may be transmitted to sense amplifier 274 via row decoder 273 and amplified, and signals amplified in sense amplifier 274 may be transmitted to control logic 271 via page buffer 275.

Figure 15 is a schematic illustration of a memory card 400 in accordance with one embodiment of the inventive concept. Referring to FIG. 15, the memory card 400 can include a controller 410 and a memory 420 or the like formed or maintained in the housing 430. The controller 410 and the memory 420 can exchange electrical signals. For example, controller 410 can exchange data with memory 420 in accordance with commands from controller 410. Therefore, the memory card 400 can store data in the memory 420 or can output data from the memory 420.

For example, memory 420 can include non-volatile memory elements as described with reference to Figures 1-13. The memory card 400 can be used as a data storage medium for various portable components. For example, the memory card 400 can include a multimedia card (MMC) or a secure digital card (SD).

16 is a block diagram of an electronic system 500 in accordance with an embodiment of the inventive concept. Referring to FIG. 16, the electronic system can include a processor 510, a memory chip 520, and an input/output unit 530 that can perform data communication by using the bus 540. The processor 510 can execute programs and control the electronic system 500. The input/output unit 530 can be used to input or output data of the electronic system 500. The electronic system 500 can be connected to an external component (for example, a personal computer or a network) by using the input/output unit 530 to exchange data with external components. For example, memory 520 can include non-volatile memory elements as described with reference to Figures 1-13.

For example, electronic system 500 can constitute various electronic controllers that require memory 520 and can be used, for example, in mobile phones, MP3 players, navigation systems, solid state disks (SSDs), home appliances, or the like.

17 is a block diagram of a memory system 600 having a non-volatile memory device 620 that includes the non-volatile memory elements described with reference to FIGS. 1 through 13. Referring to FIG. 17, the memory system 600 includes a non-volatile memory component 620 and a controller 610.

Controller 610 is coupled to host and non-volatile memory component 620. In response to a request from the host, controller 610 is configured to access non-volatile memory element 620. For example, controller 610 is configured to control read, write, erase, and background operations of non-volatile memory component 620. Controller 610 is configured to provide an interface between non-volatile memory component 620 and the host. Controller 610 is configured to operate a firmware for controlling non-volatile memory component 620.

As an example, controller 610 further includes commonly known components, such as random access memory (RAM), processing unit, host interface, and memory interface. The RAM is used as an operational memory of the processing unit, a cache memory between the non-volatile memory element 620 and the host, and at least one of the buffer memory between the non-volatile memory element 620 and the host. The processing unit controls the overall operation of the controller 610.

The host interface includes a protocol for performing data exchange between the host and the controller 610. As an example, controller 610 is configured to communicate with external components (eg, a host) via at least one of various interface protocols, such as a Universal Serial Bust (USB) protocol, a multimedia card. (MMC) Protocol, Peripheral Component Interconnection (PCI) Protocol, Serial ATA Protocol, Parallel ATA Protocol, Small Computer Small Interface (SCSI) Protocol, Enhanced Small Disk Interface (Enhanced Small Disk Interface) , ESDI) agreement, integrated drive electronics (IDE) agreement, etc. The memory interface is interfaced with a non-volatile memory component 620. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 600 can be configured to further include error correction blocks. The error correction block can be configured to detect errors in the data read from the non-volatile memory element 620 and correct the error. As an example, an error correction block can be provided as a component of the controller 610.

Controller 610 and non-volatile memory component 620 can be integrated into a single semiconductor component. Illustratively, controller 610 and non-volatile memory component 620 can be integrated into a single semiconductor component to form a memory card as described with reference to FIG. For example, the controller 610 and the non-volatile memory component 620 can be integrated into a single semiconductor component to form a memory card, such as a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash card (compact flash card, CF), smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash storage component (universal flash storage, UFS) or the like.

The controller 610 and the non-volatile memory component 620 can be integrated into a single semiconductor component to form a solid state drive (SSD). The SSD includes a storage unit configured to store data in a semiconductor memory. In the case where the memory system 600 is used as an SSD, the operation speed of the host connected to the memory system 600 is remarkably improved.

As another example, memory system 600 can be provided as one of various components that make up electronic components, such as computers, portable computers, ultra mobile PCs (UMPCs), workstations, mini-notebooks, personal digital devices. Personal Digital Assistant (PDA), web tablet, wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console (Playstation Portable, PSP) , navigation components, black box, digital camera, digital multimedia broadcasting (DMB) player, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recording , a digital video player, an element capable of transmitting and/or receiving information in a wireless environment, one of various electronic components constituting a home network, an RFID component, one of various components constituting a computing system, or the like Things.

As an example, non-volatile memory component 610 or memory system 600 can be mounted in various types of packages. Examples of packages of non-volatile memory component 610 or memory system 600 may include package on package (PoP), ball grid array (BGA), chip scale packages, CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, crystal Circular die, chip on board (COB), ceramic dual in-line package (CERDIP), metric quad flat pack (MQFP), thin Thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (system) In package, SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP) )and many more.

18 is a block diagram showing an application example of the memory system of FIG. 17. Referring to FIG. 18, memory system 700 includes non-volatile memory component 720 and controller 710. The non-volatile memory component 720 includes a plurality of non-volatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each of the plurality of non-volatile memory chips is configured to communicate with controller 710 via a single common channel. FIG. 18 illustrates the plurality of non-volatile memory chips communicating with the controller 710 via channel 1 (CH1) to channel k (CHk). Each non-volatile memory wafer contains the non-volatile memory elements described with reference to Figures 1 through 13.

19 is a block diagram of a computing system 800 incorporating a memory system 700 as described with reference to FIG. Referring to FIG. 19, computing system 800 includes a central processing unit (CPU) 810, a random access memory (RAM) 820, a user interface 830, a power supply 840, and a memory system 700.

The memory system 700 is electrically coupled to the CPU 810, the RAM 820, the user interface 830, and the power source 840 via the system bus 850. Data provided via user interface 830 or processed by CPU 810 is stored in memory system 700. The memory system 700 includes a controller 710 and a non-volatile memory component 720.

While FIG. 19 illustrates non-volatile memory component 720 coupled to system bus 850 via controller 710, non-volatile memory component 720 can be configured to interface directly with system bus 850.

In Figure 19, the non-volatile memory component 700 has been described as comprising a plurality of non-volatile memory wafers. However, the non-volatile memory component 700 can comprise a non-volatile memory wafer. Moreover, non-volatile memory component 700 includes a plurality of non-volatile memory wafers each having an inherent channel in this embodiment.

According to the non-volatile memory element of the embodiment of the inventive concept, by designing the number of string selection transistors to be at least two, compared with the case where the number of string selection transistors is one, the string selection gate electrode can be compared The earth reduces its gate length so that the space between the interlayer dielectrics can be filled without any gaps. Moreover, by designing the number of string selection transistors to be at least two, the ground selection gate electrode can greatly reduce the gate length thereof compared to the case where the number of string selection transistors is one, so that the interlayer dielectric The space between them can be filled without any gaps. Furthermore, by adjusting the gate length of the string selection transistor, the memory cell and the ground selection transistor, and the spacing between the gate electrodes, the formation of voids can be further suppressed. Therefore, the reliability of the string selection transistor, the memory cell, and the ground selection transistor can be enhanced.

While the foregoing has described what is considered to be the best mode of the embodiments and the preferred embodiments of the invention, it is understood that various modifications can be made therein and the invention can be practiced in various forms and embodiments, and In the application of the application, only some of the applications are described herein. The following claims are intended to cover all modifications and variations within the scope of the claims.

162. . . Ground selection gate electrode

164. . . Control gate electrode

166. . . String selection gate electrode

170~172, 174~176. . . Contact plug

200. . . Memory component

250. . . NAND cell array

270. . . Core circuit unit

271. . . Control logic

272. . . Column decoder

273. . . Row decoder

274. . . Sense amplifier

275. . . Page buffer

400. . . Memory card

410. . . Controller

420. . . Memory

430. . . shell

500. . . electronic system

510. . . processor

520. . . Memory

530. . . Input/output unit

540. . . Busbar

600. . . Memory system

610. . . Controller

620. . . Non-volatile memory component

700. . . Memory system

710. . . Controller

720. . . Non-volatile memory component

800. . . Computing system

810. . . Central processing unit

820. . . Random access memory

830. . . User interface

840. . . power supply

850. . . System bus

BL. . . Bit line

BL1. . . First bit line

BL2. . . Second bit line

CSL. . . Common source line

DWL. . . Dummy word line

DWL1. . . First dummy word line

DWL2. . . Second dummy word line

GSL. . . Ground selection line

GSL1. . . First ground selection line

GSL2. . . Second ground selection line

GSL3. . . Third ground selection line

GSL4. . . Fourth ground selection line

MC. . . Memory unit

NS. . . NAND string

NS11, NS12, NS21, NS22. . . NAND string

SSL. . . String selection line

SSL1. . . First string selection line

SSL2. . . Second string selection line

SSL3. . . Third string selection line

SSL4. . . Fourth string selection line

TG1. . . First ground selection transistor

TG2. . . Second ground selection transistor

TS1. . . First string selection transistor

TS2. . . Second string selection transistor

WL. . . Word line

WL0,...,WLn. . . Word line

The exemplary embodiments of the present invention will be more clearly understood from the following detailed description,

1 is a first embodiment of a circuit diagram of a non-volatile memory component in accordance with aspects of the inventive concept.

2 is a fourth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept.

FIG. 3 illustrates voltage bias conditions when a stylization operation is performed in the memory device of FIG.

4 is a table showing an embodiment of a method of controlling voltage in accordance with aspects of the inventive concept.

5 is an embodiment of a schematic cross-sectional view of the non-volatile memory component of FIG. 2 taken from the direction of the bit line.

Figure 6 is another embodiment of a schematic cross-sectional view of the non-volatile memory component of Figure 2 taken from the direction of the bit line.

7 is a further embodiment of a schematic cross-sectional view of the non-volatile memory component of FIG. 2 taken from the direction of the bit line.

Figure 8 is a further embodiment of a schematic cross-sectional view of the non-volatile memory component of Figure 2 taken in the direction of the bit line.

Figure 9 is a further embodiment of a schematic cross-sectional view of the non-volatile memory element of Figure 2 taken in the direction of the bit line.

Figure 10 is a fifth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept.

Figure 11 is a sixth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept.

Figure 12 is a seventh embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept.

Figure 13 is an eighth embodiment of a circuit diagram of a non-volatile memory element in accordance with aspects of the inventive concept.

14 is a block diagram of another embodiment of a non-volatile memory component in accordance with aspects of the inventive concept.

Figure 15 is a schematic illustration of an embodiment of a memory card in accordance with aspects of the inventive concept.

16 is a block diagram of an embodiment of an electronic system in accordance with aspects of the inventive concept.

17 is a block diagram of an embodiment of a memory system having a non-volatile memory device including the non-volatile memory elements described with reference to FIGS. 1 through 13.

FIG. 18 is a block diagram showing an embodiment of an application example of the memory system of FIG. 17.

19 is a block diagram of an embodiment of a computing system including the memory system described with reference to FIG.

BL. . . Bit line

CSL. . . Common source line

GSL1. . . First ground selection line

GSL2. . . Second ground selection line

MC. . . Memory unit

NS. . . NAND string

SSL1. . . First string selection line

SSL2. . . Second string selection line

TG1. . . First ground selection transistor

TG2. . . Second ground selection transistor

TS1. . . First string selection transistor

TS2. . . Second string selection transistor

WL0,...,WLn. . . Word line

Claims (10)

A method of operating a non-volatile memory component, comprising: applying a turn-on voltage to each of a first string of select transistors and a second string of select transistors of a first NAND string via a first string of select lines, wherein The first string selection transistor and the second string selection transistor have the same structure; applying a first voltage and a second voltage to the second NAND via a second string selection line different from the first string selection line a third string selection transistor and a fourth string selection transistor, wherein the third string selection transistor and the fourth string selection transistor have the same structure; and applying a high voltage to the first NAND The word line connecting the string and the memory unit of the second NAND string. The method of operating a non-volatile memory component according to claim 1, wherein the second voltage has a higher level than the first voltage. The method of operating a non-volatile memory component according to claim 1, wherein the first voltage has a level lower than a ground voltage. A method of operating a non-volatile memory component as recited in claim 1, wherein the second voltage has a lower level than a threshold voltage of the fourth string of selected transistors. The method of operating a non-volatile memory element according to claim 1, wherein the third string selection transistor is coupled to the fourth string selection transistor and to a bit corresponding to the second NAND string Yuan line between. The method of operating a non-volatile memory element according to claim 1, further comprising: applying a second high voltage between the first to fourth string selection transistors and the memory unit A dummy cell, wherein the second high voltage has a level lower than the high voltage. A non-volatile memory component, comprising: a memory cell array; and peripheral circuitry configured to access the memory cell array, wherein the memory cell array comprises a substrate; a plurality of memory cell groups, Arranging on the substrate in columns and rows, each memory cell group includes a plurality of memory cells stacked in a direction crossing the substrate; a plurality of first selected transistor groups respectively provided in the a substrate and the plurality of memory cell groups; and a plurality of second selected transistor groups respectively provided on the plurality of memory cell groups, wherein the peripheral circuits are configured to be programmed And driving, by the first string selection line, a second selection transistor of the second selection transistor group corresponding to the unselected memory cell group of the plurality of memory cell groups, wherein the plurality of first selection electrodes are independently driven Each of the groups of crystals has the same structure as each of the plurality of second selected groups of transistors, Wherein the peripheral circuitry is configured to drive a selected memory cell group corresponding to the plurality of memory cell groups via a second string selection line different from the first string selection line during the stylizing operation The second selects the second selected transistor of the group of transistors. The non-volatile memory component of claim 7, wherein the peripheral circuitry is further configured to drive the second selection of the second selected transistor population at different voltages during a stylizing operation Transistor. The non-volatile memory component of claim 7, wherein during the stylizing operation, the specific second selected transistor of the second selected transistor group is driven by the first voltage, and the Another second selection transistor provided between the particular second selection transistor and the unselected memory cell group is driven by a second voltage that is higher than the first voltage. A memory system comprising: a non-volatile memory component; and a controller configured to control the non-volatile memory component, wherein the non-volatile memory component comprises a memory cell array and a group To access peripheral circuits of the memory cell array, wherein the memory cell array comprises a plurality of memory cell strings having a 3-dimensional structure, each memory cell string comprising at least two of the first ones provided on one side Selecting a transistor and at least two second selection transistors provided on the other side, wherein each of the at least two first selection transistors has the same structure, and the at least two Second choice of electro-crystal Each of the second selection transistors in the body has the same structure, wherein the peripheral circuitry is configured to drive unselected memories of the plurality of memory cell strings at different voltages via the first string of select lines during the stylizing operation The at least two second selection transistors of the body cell string, wherein the peripheral circuit is configured to drive selected memory of the plurality of memory cell strings via the second string selection line during the stylizing operation The at least two second selection transistors of the string of cells.