TWI518474B - Adaptive charge pump, controlling method thereof, and electronic device - Google Patents

Description

Adaptive charging pump and control method thereof, electronic device

The present invention relates to an adaptive charge pump.

Related application cross-reference

The application claims the benefit of U.S. Provisional Application Serial No. 61/479,733, filed on Apr. 27, 2011, which is hereby incorporated by reference in its entirety in its entirety in its entirety.

It is generally desirable to operate a complementary MOSFET integrated circuit over a wide range of power supply voltages. For example, a complementary MOS wafer can receive a supply voltage ranging from a minimum level of 1.8 volts to a maximum or limiting voltage of 5.5 volts, wherein the upper voltage range (eg, 5.5 volts) is used to fabricate the The voltage limit of the process of the integrated circuit is determined. It is also common that at a lower level of the source voltage range, an operating voltage range that is greater than the supply of the input supply voltage is desirable. When a voltage level or voltage range greater than the supplied source voltage is desired, a charge pump or the like is incorporated into the design of the integrated circuit to increase the overall available supply voltage.

An increase in the supply voltage range is implemented, for example, where it is desired to increase the dynamic operating range of an element, such as an amplifier or the like. A charge pump system can be used to charge a positive voltage rail to a voltage level higher than the positive supply voltage. This is also done, for example, where a single positive supply rail is provided below the grounded operating system, in which case the charge pump produces a negative supply rail. The negative supply rail is typically tied to ground potential and is slightly smaller than the rail voltage supplied.

With the commonly used charge pump configuration, the positive/negative rail voltages become larger positive/negative values at the same rate of increase in the supplied rail voltage. This is the actual limit when the overall voltage range between the internally generated rail voltage and the externally supplied ground or reference level reaches the maximum allowed by the process. Alternatively or additionally, the actual limit is generated when the overall voltage range between the internally generated negative rail voltage and the externally supplied positive rail voltage reaches the maximum allowed by the process.

Thus, conventional charge pump configurations limit the supply of source voltage to a maximum level that is lower than the overall voltage limit of the process used to fabricate the integrated circuit. If the source voltage exceeds the maximum level, even if it is still below the overall voltage limit of the integrated circuit, the integrated circuit may malfunction, may be damaged, or may even be subject to a disaster.

One aspect of the present invention relates to an adaptive charge pump including first and second nodes, a first capacitor, a second capacitor, a third capacitor, and a first electric having a first conductivity type A crystal, a second transistor having a first conductivity type, a third transistor having a second conductivity pattern, a fourth transistor having a second conductivity pattern, and a controller. The first and second nodes are in a reverse state between the first and second supply voltages. The first capacitor is connected between the first node and a third node. The second capacitor is connected between the second node and a fourth node. The third capacitor is connected between an output node and the second supply voltage. The first electro-crystalline system having the first conductivity pattern has a first current terminal connected to a control node, a second current terminal connected to the third node, and a control terminal connected to the fourth node. A second electro-crystalline system having a first conductivity pattern has a first current terminal coupled to the control node, a second current terminal coupled to the fourth node, and a control terminal coupled to the third node. A third transistor having a second conductivity pattern has a first current terminal coupled to the third node, a second current terminal coupled to the output node, and a control terminal coupled to the fourth node. A fourth transistor having a second conductivity pattern has a first current terminal coupled to the fourth node, a second current terminal coupled to the output node, and a control terminal coupled to the third node. When the voltage difference between the output node and the second supply voltage does not exceed a limit voltage, the controller controls the control node to be at the same voltage level as the first supply voltage, otherwise the controller controls the The voltage of the node is controlled to prevent the voltage difference from exceeding the limit voltage.

Another aspect of the invention relates to an electronic device comprising: a supply input, a reference input, a voltage rail, and a charge pump. The supply input receives an adjustment voltage. The reference input receives a reference voltage. The charge pump is coupled between the supply input and the reference input and has an output terminal coupled to the voltage rail. The charge pump drives the voltage rail to become twice the voltage level of the regulated voltage to a limit voltage level. The charging pump includes first and second nodes, a first capacitor, a second capacitor, a third capacitor, a first N-type transistor, a second N-type transistor, and a first P-type transistor. , a second P-type transistor and a controller. The first and second nodes are in a reverse state between the adjusted voltage and the reference voltage. The first capacitor is connected between the first node and a third node. The second capacitor is connected between the second node and a fourth node. The third capacitor is connected between the second node and the output terminal. The first N-type electro-emissive system has a current terminal connected between a control node and the third node, and has a control terminal connected to the fourth node. The second N-type electro-emissive system has a current terminal connected between the control node and the fourth node, and has a control terminal connected to the third node. The first P-type electro-emissive system has a current terminal connected between the third node and the output terminal, and has a control terminal connected to the fourth node. The second P-type electro-emissive system has a current terminal connected between the fourth node and the output terminal, and has a control terminal connected to the third node. When the voltage difference between the output terminal and the reference voltage does not exceed the limit voltage level, the controller controls the control node to be at the same voltage level as the adjustment voltage; otherwise, the controller controls the control node The voltage is to prevent the voltage difference from exceeding the limit voltage level.

Another aspect of the invention relates to an electronic device comprising: a supply input, a reference input, a voltage rail, and a charge pump. The supply input receives an adjustment voltage. The reference input receives a reference voltage. The charge pump is coupled between the supply input and the reference input and has an output terminal coupled to the voltage rail. The charge pump drives the voltage rail to be about the same voltage level as the regulated voltage and has the opposite polarity to reach a threshold voltage level. The charging pump includes first and second nodes, a first capacitor, a second capacitor, a third capacitor, a first P-type transistor, a second P-type transistor, and a first N-type transistor. , a second N-type transistor and a controller. The first and second nodes are in a reverse state between the adjusted voltage and the reference voltage. The first capacitor is connected between the first node and a third node. The second capacitor is connected between the second node and a fourth node. The third capacitor is connected between the second node and the output terminal. The first P-type electro-emissive system has a current terminal connected between a control node and the third node, and has a control terminal connected to the fourth node. The second P-type electro-emissive system has a current terminal connected between the control node and the fourth node, and has a control terminal connected to the third node. The first N-type electro-emissive system has a current terminal connected between the third node and the output terminal, and has a control terminal connected to the fourth node. The second N-type transistor system has a current terminal connected between the fourth node and the output terminal, and has a control terminal connected to the third node. When the voltage difference between the output terminal and the adjustment voltage does not exceed twice the threshold voltage level, the controller controls the control node to be at the same voltage level as the reference voltage. Otherwise, the controller The voltage of the control node is controlled to prevent the voltage difference from exceeding twice the threshold voltage level.

One aspect of the present invention relates to a method for adaptively controlling a charge pump, comprising: connecting the charge pump to a control node; and switching a clock of the charge pump to a supply voltage level To charge the output of the charge pump; monitor the output of the charge pump; maintain the control node at a supply voltage level when the magnitude of the supply voltage is less than or equal to a threshold level; and when the magnitude of the supply voltage exceeds the When the limit is set, the control node is adjusted to maintain the output of the charge pump at a limit level.

The following description is presented to enable a person of ordinary skill in the art to make and use the invention as claimed. However, various modifications to the preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the details of the particular embodiments described herein, but the scope of the invention disclosed herein.

It is desirable to reduce the magnitude of the voltage generated by the charge pump at the same rate as the external applied voltage at the process limit point to ensure an internal supply voltage rail and a total supply voltage between one of the two supply voltages. The range does not exceed the process limit. One means for modifying an existing charge pump circuit to accomplish this is the subject of this disclosure.

1 is a block diagram of an electronic device 100 including a DC-to-DC switching voltage regulator 107 (otherwise referred to as a converter or power supply or the like) that provides an adjusted output voltage VOUT. The electronic device 100 is shown to include a battery 101 that provides a battery voltage VBAT to an input of a voltage selection (VSEL) circuit 105. The other input of voltage selection circuit 105 receives a DC voltage (VDC) from a power adapter 103. The power adapter 103 receives an AC or DC voltage from an external power source, such as an AC source (not shown), and converts the received voltage to a VDC voltage. If the battery 101 is rechargeable, the power adapter 103 can include a battery charger for charging the battery 101, or a separate battery charger (not shown) can be included. VSEL circuit 105 provides an input voltage VIN to an input of voltage regulator 107. The voltage regulator 107 has an output that provides an output voltage VOUT that is used to provide a source voltage to a load LD.

The load LD typically includes circuitry of the electronic device 100 that receives a load current ILOAD. As shown, the load LD can include a number of devices, such as a processor 109, a memory 111, and one or more connected through a suitable interface 114 for a non-exhaustive list of possible devices. For other support devices 113, the appropriate interface 114 is such as a bus bar or the like. Each device receives a supply voltage (e.g., VOUT) from regulator 107 with respect to a reference voltage level, such as ground. Other types of electronic devices that do not have a processor or memory are also contemplated.

The electronic device 100 can be any form of electronic device, including a mobile, portable or handheld device such as, for example, any form of personal digital assistant, personal computer, portable computer, laptop, etc., action Telephone, personal media device, etc. In an alternate embodiment, the electronic device 100 is non-battery powered and powered by an AC source or other power source. In general, voltage regulator 107 is constructed as a voltage regulator for computer, industrial, consumer, etc. and/or battery powered applications.

The primary function of the electronic device 100 is implemented by the load LD, which is the device circuitry within the depicted configuration. In one embodiment, while a non-rechargeable battery is contemplated, battery 101 can be any suitable form of rechargeable battery. In various embodiments, for a boost configuration, the voltage of VIN is lower than VOUT. For a buck configuration, the voltage of VIN is higher than VOUT, or the range of VIN relative to VOUT can be various other groups. At any point between the states, various other configurations are, for example, a single-ended, primary-inductor converter (SEPIC) or step-up voltage converter or the like.

Power consumption and efficiency are most important in portable and/or battery powered applications. It is desirable that, for example, the load LD be constructed to be as efficient as possible to minimize ILOAD (and corresponding power consumption) while maintaining proper operation for the desired operational parameters or modes. VOUT and/or other supply voltages may have a specified value that is limited to achieve the desired power efficiency. Even so, it is desirable to operate any one or more of the devices within load LD, such as processor 109 and one or more support devices 113, within a range of voltages that are greater than VOUT and ground. A charge pump or the like is typically provided within an integrated circuit to achieve the desired voltage range.

In some electronic devices, the voltage of VOUT relative to ground is sufficiently low that a device within the load LD can operate over an extended voltage range without violating voltage process limitations. In this case, it is desirable for the charge pump to drive an internal voltage rail to a desired increased voltage level. In other electronic devices, although the voltage range between VOUT and ground can be within the voltage process limits of the device carrying the LD, the internal extended voltage range can exceed the voltage process limit for the device. In this case, it is desirable that the voltage generated by any internally provided charge pump is reduced in magnitude according to the external supply voltage such that the overall supply voltage range does not exceed the process limit.

In other words, it is desirable for an integrated circuit device to produce a maximum allowable internal voltage level without exceeding the process limits of the device. An adaptive control charge pump as described herein provides this useful function.

2 is a simplified block diagram of an integrated circuit 200 including a positive adaptive charge pump 201 implemented in accordance with one embodiment. The integrated circuit 200 includes power supply pins V+ and V-, which are respectively connected to the supply voltage VOUT and ground. The voltage applied to the supply input pin V+ (eg, VOUT) is internally wound through the conductive path 203 as a positive voltage VP to the positive input of the charge pump 201. The voltage applied to the supply input pin V- (eg, ground) is internally wound through the conductive path 205 as a negative (or reference) voltage VN to the negative input of the charge pump 201. A clock signal CK is shown as being supplied to the other input of the adaptive charge pump 201 by a clock circuit 211. In one embodiment, the clock circuit 211 is an oscillator circuit or the like for generating a CK at the integrated circuit 200. Alternatively, the clock circuit 211 distributes or otherwise develops CK from an external clock source, such as an external clock signal CLK received from a clock pin CL or the like. The integrated circuit 200 includes at least one device operating at an extended voltage range that is greater than the difference between ground and VOUT without violating the process limitations of the integrated circuit 200. As shown, for example, the integrated circuit 200 includes an amplifier 209 having positive (V+) and negative (V-) supply voltage terminals that are intended to operate as large as possible within a dynamic voltage range. . The adaptive charge pump 201 receives VP and VN and provides an output voltage VO having a magnitude that can be approximately twice (2 VP) of VP. The output of the adaptive charge pump 201 is coupled to a positive voltage rail 207. In this case, the VN is provided to the V-supply terminal of amplifier 209, and the positive voltage rail 207 is coupled to the V+ supply terminal of amplifier 209.

When the voltage supply range between VOUT and ground is sufficiently small, the adaptive charge pump 201 operates to increase the dynamic operating voltage range of the amplifier 209 by, for example, increasing the voltage level of VO to a voltage level of approximately VP. Double or 2VP while reaching. The CK signal is toggled at a suitable frequency to drive the operation of the adaptive charge pump 201, as further described below. If the voltage supply range is increased above a threshold level (VTH), which can cause the difference between 2VP and VN (or ground) to exceed the process limit, then the adaptive charge pump 201 limits the voltage level of the VO accordingly. Bit. In one embodiment, the process voltage limit relative to VN is VLIM. As shown, the VO has a voltage of approximately 2 VP, which is limited by the VLIM such that VO-VN ≦ VLIM. Assuming that the VN is about 0 volts (0 V) and the VTH is about half of the VLIM, the VO system is 2 VP when the VP system is below VTH, and the VO system is VLIM when the VP is at or above VTH. Therefore, the adaptive charge pump 201 is a positive adaptable voltage pump that increases the voltage level of the positive voltage rail 207 as much as possible without exceeding the process limits of the integrated circuit 200.

3 is a simplified block diagram of an integrated circuit 300 including a negatively adaptive charge pump 301 implemented in accordance with one embodiment. The integrated circuit 300 also includes power supply pins V+ and V- that receive the supply voltage VOUT and ground, respectively. The voltage applied to the supply input pin V+ (eg, VOUT) is internally wound through the conductive path 203 as a positive voltage VP to the positive input of the charge pump 301. The voltage applied to the supply input pin V- (eg, ground) is internally wound through the conductive path 205 as a negative (or reference) voltage VN to the negative input of the charge pump 301. The clock signal CK is shown as being supplied to the other input of the adaptive charge pump 201 by a clock circuit 211. Again, the clock circuit 211 can be an oscillator circuit or the like for generating the CK at the integrated circuit 300, or can be based on an external clock source in a similar manner as previously described for the integrated circuit 200. Only develop or assign CK. The integrated circuit 300 includes at least one device operating at an extended voltage range that is greater than the difference between ground and VOUT without violating the process limitations of the integrated circuit 300. As shown, for example, the integrated circuit 300 includes an amplifier 209 having positive (V+) and negative (V-) supply voltage terminals that are intended to operate as large as possible within a dynamic voltage range.

The adaptive charge pump 301 receives VP and VN and provides an output voltage VO. In this case, the voltage level of VO has a size approximately the same as VP, such that when VP is less than or equal to the threshold voltage level VTH (half of VLIM), VO is equal to -VP. When VP is at or above VTH, the sum of the amplitudes of VP plus VO is maintained at VLIM, or VP+∣VO∣≦VLIM. The output of the adaptive charge pump 301 providing VO is coupled to a negative voltage rail 307. In this case, the VP is provided to the V+ supply terminal of amplifier 209, and the negative voltage rail 307 is coupled to the V-supply terminal of amplifier 209.

When the voltage supply range between VOUT and ground is sufficiently small, the adaptive charge pump 301 operates to increase the dynamic operating voltage range of the amplifier 209 by, for example, increasing the amplitude of the VO to produce an amplitude of VP (eg, - VP), so that the difference between VP and VO is twice the voltage supply range between VOUT and ground (VP-[-VP]=2VP). The CK signal is toggled at a suitable frequency in a similar manner as for the adaptive charge pump 201 to drive operation of the adaptive charge pump 301. If the voltage supply range is increased above a threshold level (VTH) which can cause the difference between VP and VO to exceed the process limit represented by VLIM, then the adaptive charge pump 301 controls the amplitude of VO accordingly. To maintain the voltage difference between VP and VO to VLIM. Thus, the adaptive charge pump 301 is a negatively adaptable voltage pump that increases the amplitude of the negative voltage rail 307 as much as possible without exceeding the process limits of the integrated circuit 300.

4 is a schematic and block diagram of a positive adaptive charge pump 201 in accordance with one embodiment. Node A is connected to a P-channel transistor P1 and a gate of an N-channel transistor N1. The P-channel transistor P1 and the N-channel transistor N 1 are shown as metal oxide semiconductor (MOS) transistors or field effect transistors (FETs) or analogs according to CMOS technology. Alternative transistor types can be used depending on the particular implementation of the process. The source of P1 and the system are connected to the positive supply voltage VP, and the drain of the system is connected to a node C, which is further connected to the drain of N1. The source of N1 and the system are connected to a negative supply voltage VN. Node A is coupled to the input of an inverter 403 having an output coupled to a Node B. Node B is connected to the gate of another P-channel transistor P4 and the gate of another N-channel transistor N4. The source of P4 and the system are connected to the positive supply voltage VP, and the drain of the system is connected to a node D, which is further connected to the drain of N4. The source of N4 and the system are connected to VN.

The drain and body or contact of each of a pair of N-channel transistors N2 and N3 are connected to a control node VCTL. The source of N2 is connected to a node E which is further connected to the source of the P-channel transistor P2 and one of the ends of a capacitor C1. The source of N3 is connected to a node F which is further connected to the source of the P-channel transistor P3 and one of the other capacitors C2. The gate of N2 and the gate of P2 are all connected to node F, and the gate of N3 and the gate of P3 are connected to node E. The other end of C1 is connected to node C, and the other end of C2 is connected to node D. The drains of each of P2 and P3 and the system are connected together at one output node VO, and the output node VO is further connected to one of the other capacitors C3. The other end of C3 is connected to the VN. A controller 401 is connected between the VN and the VP, and is further connected to the VCTL and the VO. The CK signal is shown as driving node A, where CK is toggled between the voltage levels of VN and VP. The VO is the output of the positive adaptive charge pump 201.

5 is a timing diagram of voltage versus time for nodes A, B, C, D, E, F, and VO for displaying the operation of the adaptive charge pump 201. The supply voltage range between VP and VN is sufficiently low below the process voltage limit to allow for an extended voltage range and the output VO is unloaded. In this case, normal operation means that the controller 401 maintains the VCTL at approximately the same level as the VP. The CK signal is between the VN and VP as described previously for the two-state thixotropic node A. At start time t0, node A is driven high by CK to VP, turning N1 on and P1 off, causing node C to pull low to VN. At time t0, inverter 403 drives node B to a low level to become VN, turning P4 on and N4 off, causing node D to pull up to VP. P1 and N1 collectively form an inverter, so that under the small timing delay between node A and node C, node C is toggled between VN and VP, and becomes opposite to the state of node A. . Similarly, P4 and N4 collectively form an inverter such that under the small timing delay between node B and node D, node D is toggled between VN and VP, and becomes node B state. The opposite state. Therefore, as shown in the figure, when A becomes a low level at time t1, both B and C become a high level, and D becomes a low level; when A changes back to a high level at time t2, B and C Both become low level, and D becomes high level; and when A changes back to low level at time t3, both B and C become high level, and D becomes low level. When CK is toggled at node A, the operation repeats in this manner.

After time t0, capacitor C1 is charged to a voltage of approximately VP (shown as ~VP, in this case slightly less than VP) through the body-source junction of N2 and the drain-source path of N1, as The voltage of node E is reflected. The voltage at node F is indeterminate, and VO is at a low voltage level, which indicates that capacitor C3 is initially charged. At the subsequent time t1, the node A-D changes state, in which the node C becomes the high level to become the VP. The charging of C1 briefly drives node E above VP to approximately twice VP, shown as ~2 VP. Since node B becomes a high level to become a VP, which causes P4 to be turned off and N4 to be turned on, node F is driven to be approximately VP, which is shown as ~VP. Since D is tied to VN, capacitor C2 is charged to approximately VP, or ~VP. The combination of the voltages at nodes E and F turns P2 on, causing the C1 portion to discharge to C3. C3 is charged between t1 and t2 to a voltage V01 which is approximately one-half (VP/2) of VP.

At time t2, each of the nodes AD changes state again (eg, in response to the CK signal), causing D to become a high level to become approximately VP, and the charge on C2 increases node F to approximately 2 times VP, or ~2VP . N2 is turned on immediately, which fully charges C1 into VP. P3 is turned on, and C2 is partially charged to C3, and the output node VO is raised to a higher voltage level, which is displayed as V02. As node A-D changes state, this routine continues in response to CK until output VO is charged to voltage V03, etc., reaching a maximum level of approximately 2 VP.

This situation typically occurs in a circuit or integrated circuit such as integrated circuit 200 and/or 300 that is applied to various environments and has different VOUT values. For example, a given actual integrated circuit can be exposed to a supply voltage range within a given electronic device, such as for different operating modes, where VOUT is at a minimum for different operating modes. Adjust between the maximum values. Alternatively, the first integrated circuit according to a given design can be placed in a first device using a low voltage level for VOUT, and a second integrated circuit implemented according to the same design can be placed in a Use a second device for the higher voltage level of VOUT. Both of the integrated circuits 200 and 300 have a process breakdown limit that limits the voltage difference applied to the integrated circuit or any component within the integrated circuit. If the voltage difference exceeds the process crash limit, the integrated circuit may be damaged or may not operate properly. Since each of the integrated circuits 200 and 300 generates an internal voltage which causes a voltage difference of approximately two times the source voltage difference between VOUT and ground, if VOUT exceeds approximately half of the process collapse limit, then 2VP The amplitude of the internally generated voltage of the VO (either the adaptive charge pump 201) or the -VP (negative adaptive charge pump 301) is reduced or limited to avoid violating the process collapse limit.

Consider, for example, a particular case where the VOUT is expected to range between approximately 1.8 volts and 5.5 volts, wherein the process collapse limit or VLIM system is only above approximately 5.5 volts. The positive adaptive charge pump 201 or the negative adaptive charge pump 301 can operate to drive the voltage rail 207 or the voltage rail 307 when VOUT is at or below a threshold voltage level of approximately half of the VLIM (or approximately 2.75 volts). Become the maximum voltage level, or become approximately 2VP or -VP. However, when VOUT is above VTH, the voltage level of voltage rail 207 or voltage rail 307 is limited or otherwise reduced to avoid voltage differences greater than VLIM (eg, VO-VN > VLIM). When VOUT is 5.5 volts, the VO system in integrated circuit 200 is driven to approximately 2*5.5V=11V. Similarly, when VOUT is 5.5 volts (and VP is 5.5V), the VO system is driven to approximately -5.5V such that the difference between VP and VO(-VP) is approximately 11V.

The controller 401 of the positive adaptive charge pump 201 of the integrated circuit 200 is constructed to limit the voltage level of the output VO of the voltage level of the positive voltage rail 207 by controlling the voltage level of the VCTL, thereby avoiding this The situation you want. In particular, when the difference between VP and VN is less than or equal to VTH, controller 401 effectively clamps the VCTL to VP such that the VO system is charged to a voltage level that is approximately twice VP. However, when the difference between VP and VN is higher than VTH, controller 401 controls VCTL to limit the voltage level of VO such that the difference between VO and VN has a maximum level of approximately VLIM.

The negative adaptive charge pump 301 of the integrated circuit 300 operates in a similar manner by controlling the voltage level of the VCTL to limit the voltage level of the output VO that drives the voltage level of the negative voltage rail 307. In this case, when the VP is at or below VTH, the VO is driven into a negative version of VP, which has the opposite amplitude, or -VP. When the VP system is above VTH, the amplitude of VO is reduced, so that the difference between VP and VO is maintained at approximately VLIM to avoid violating the maximum process limit.

Figure 6 is a schematic illustration of a controller 401 in accordance with one embodiment. A Zener diode Z1 has its cathode connected to VO and its anode connected to a node 606. Each of the pair of P-channel electrical bodies P5 and P6 has its body and source connected to the VP. P6 is diode-connected, its gate is connected to its drain at one node 602, and node 602 is further connected to the gate of P5. The drain of P5 is connected to the VCTL, and a smoothing capacitor C4 is connected between the VP and the VCTL. A current source 601 has a first terminal coupled to the VP and a second terminal coupled to a node 604, wherein the current source 601 develops a bias current IB from the VP to the node 604. An N-channel transistor N5 has its drain connected to node 602, its gate connected to node 604, and its body and source connected together at node 606. A resistor R is coupled between node 604 and a node 608. An N-channel transistor N6 has its body and source connected to VN and its drain connected to node 606. Another N-channel transistor N7 has its body and source connected to VN and its drain connected to node 608. The gates of N6 and N7 are connected together at node 608 such that the N7 system is actually diode connected. A current IM flows from the drain of N5 to node 602. A current IZ flows from node 606 through Z1 to VO.

The Z1 system constitutes a breakdown voltage with VLIM. The IB level and the value of R are collectively constructed to form a voltage at node 604 to operate N5 such that the drain-source voltage of N6 exceeds its pinch-off voltage. In this way, the N6 operates in its saturation mode. N6 and N7 are collectively constructed as a current mirror, so that the current flowing through R, which is mainly controlled by IB, controls the level of the current flowing through the drain of the N6. The relative sizes of N6 and N7 determine the amount of gain of the N6 drain-source current relative to IB. In one embodiment, the N6 and N7 series are approximately equal in size such that the drain-source current of N6 is approximately the same as IB. In an alternate embodiment, the relative sizes of N6 and N7 can be adjusted to adjust the drain-source current of N6 relative to IB. Current source 601 and R1, N5, N6, and N7 collectively operate as a current controlled current source that actually reproduces a fixed multiple of IB, or IB, as the drain-source current for N6. The P5 system is constructed to be considerably larger than the P6. In one embodiment, the P5 is about 20 times the size of P6.

The configuration of the current controlled current source causes the sum of the currents IZ and IM to be approximately equal to IB. When Z1 is off, IZ is zero or negligible, making the IM system approximately equal to IB. When Z1 is turned on, IZ increases and IM decreases to maintain the sum of IZ and IM to approximately IB, or IM+IZ IB.

Figure 7 is a simplified diagram of voltage versus time for VP, G, and VCTL, which is drawn in the following cases: VP is increased by a minimum level VMIN below VTH to the maximum level VLIM for display use. The controller 401 of 6 is adaptive to the operation of the charge pump. This diagram is simplified in that small differences or transition changes are ignored. The VN is a reference supply voltage that is assumed to be grounded or approximately 0 volts. Before reaching a start time t0, the voltage of VP is VMIN, as shown at 701. The voltage of VO is approximately twice the VP, or approximately 2 VP, as shown at 703. Z1 is off in this case, making IZ zero. The current flowing through P6 establishes a gate-source voltage, which is reflected as the gate-source voltage of P5. The P5 architecture constitutes an average of the currents directed by capacitors C1 and C2, which have only a relatively small source-drain voltage, such that when Z1 is off, the VCTL is actually connected to the VP. As shown, the VCTL has a voltage of approximately VMIN, as shown at 702. In this manner, controller 401 has minimal impact such that adaptive charge pump 201 operates in a normal manner with reference to the timing diagram of FIG. 5 as previously described.

The VP line increases linearly as shown at 705 towards the VTH. When the VP is VTH or lower than VTH, the voltage of VO rises at approximately twice the rate of VP to maintain its voltage at approximately 2 VP, as shown at 707. The voltage of the VCTL rises at approximately the same rate as VP, as shown at 706. At time t1, VP reaches VTH, so that VO reaches VLIM, and the VCTL system is still about the same as VP, which is VTH.

When the voltage of VP exceeds VTH after time t1, as shown at 709, the voltage of VO tends to exceed VLIM, and Z1 provides a non-zero current IZ to node 606, since the drain-source current of N6 is due to the current mirror. The fact that the configuration is fixed, thereby reducing the level of IM. The gate-to-source voltage of P6 is reduced, thus reducing the gate-to-source voltage of P5, so that during charge pump operation, P5 draws less current from its drain to VCTL, which is used to supply current to C1. And C2, and thus eventually to C3. When VP linearly increases, the voltage level of the VCTL decreases linearly, as shown at 710, such that as VP increases, the voltage of VO remains limited to approximately VLIM. At time t2, VP reaches VLIM and is then held at VLIM. The VO is maintained fairly stable at approximately VLIM, while the VCTL is ultimately settled to a minimum level.

The switching action of nodes A-D can be reflected on the VCTL, where capacitor C4 operates to smooth the voltage level of the VCTL during operation.

Figure 8 is a schematic and block diagram of a negatively adaptable charge pump 301 in accordance with one embodiment. The negatively adaptable charge pump 301 is constructed in a similar manner as the adaptive charge pump 201, wherein like elements are labeled with the same elements. N1, N4, P1, P4 and inverter 403 are constructed and connected in substantially the same manner between VP and VN, which form nodes A, B, C and D in substantially the same manner. The CK signal is shown as driving node A, where CK is toggled between the voltage levels of VN and VP in the same manner. Further, capacitor C1 is connected between nodes C and E, and capacitor C2 is connected between nodes D and F in a similar manner.

For the negative adaptive charge pump 301, the P-channel transistors P2 and P3 are replaced by corresponding N-channel transistors N2 and N3, respectively. Node E is connected to the source of N12, to the gate of N13, to the source of P12 and to the gate of P13. Node F is connected to the source of N13, to the gate of N12, to the source of P13 and to the gate of P12. The drains of N12 and N13 and the system are connected together at the output node VO, and the output node VO is further connected to one end of C3. The other end of C3 is connected to the VN. The drain and source of P12 and P13 are connected to the VCTL.

Controller 401 is replaced by a controller 801 that is coupled between VN and VP and is further coupled to VCTL and VO. For the controller 801, the P-channel transistors P5 and P6 of the controller 401 are respectively replaced by corresponding N-channel transistors N15 and N16, and the N-channel transistors N5-N7 of the controller 401 are respectively corresponding to P. Channel transistors P15, P16 and P17 are substituted. This configuration is actually a flip between VP and VN, where Z1 is reversed and its anode is connected to VO and its cathode is connected to a node 806 (which corresponds to node 606). A current source 803 replaces current source 601 and provides current IB from VN to a node 804. A resistor R is coupled between a node 804 (which corresponds to node 604) and a node 808 (which corresponds to node 608). P15 and P16 have their source and body connected to the VP and their gates are connected together at node 808. The gate of P17 is connected to its drain at node 808. The drain of P16 is coupled to node 806, which is further coupled to the gate and body of P15. The gate of P15 is coupled to node 804 and its drain is coupled to node 802 (which corresponds to node 602). The source and body of N15 and N16 are connected to VN. The drain of N15 is connected to the VCTL and connected to one of the terminals of C4. The gates of N15 and N16 and the gates of N16 are connected together at node 802. The other end of C4 is connected to the VN. Current IM is shown as flowing from node 802 to the drain of P15, and current IZ is shown flowing out of node 806, passing through Z1 to VO.

The configuration and operation of the controller 801 is similar to the controller 401 of the adaptive charge pump 201 for the negative adaptive charge pump 301. The Z1 system constitutes a breakdown voltage with VLIM. The level of IB and the value of R are collectively constructed to form the voltage at node 804 to operate P15 such that the drain-source voltage of P16 exceeds its pinch-off voltage. In this way, P16 operates in its saturation mode. P16 and P17 are collectively constructed as a current mirror, so that the current flowing through R, which is mainly controlled by IB, controls the level of the current flowing through the drain-source of P16. The relative size of P16 and P17 determines the amount of gain of the drain-source current of P16 relative to IB. In one embodiment, the P16 and P17 systems are approximately equal in size such that the drain-source current of P16 is approximately the same as IB. In an alternate embodiment, the relative sizes of P16 and P17 can be adjusted to adjust the drain-source current of P16 relative to IB. Current source 801 and R1, P15, P16, and P17 collectively operate as a current controlled current source that actually reproduces a fixed multiple of IB, or IB, as the drain-source current of P16. The N15 is constructed to be considerably larger than the N6. In one embodiment, N15 is about 20 times the size of N16.

The configuration of the current controlled current source causes the sum of the currents IZ and IM to be approximately equal to IB. When Z1 is off, IZ is zero or negligible, making the IM system approximately equal to IB. When Z1 is turned on, IZ increases and IM decreases to maintain the sum of IZ and IM to approximately IB, or IM+IZ IB.

The operation of the negative adaptive charge pump 301 is similar except that when the VP system is equal to or less than VTH, the node G is charged to the same amplitude as VP and has opposite polarities. When the VP system is above VTH, the amplitude of node G is reduced such that the difference between VP and node G is maintained at a maximum voltage difference of approximately VLIM. It should be noted that if the VP system is approximately VLIM, then the node G becomes approximately 0 volts.

Figure 9 is a simplified diagram of VP, VO, and VCTL versus time, which is drawn in the following cases: VP is increased by a minimum level VMIN below VTH to the maximum level VLIM for display use as shown in Figure 8. The negative of the controller 801 can accommodate the operation of the charge pump 301. This diagram is simplified in that small differences or transition changes are ignored. The VN is a reference supply voltage that is assumed to be grounded or approximately 0 volts. Before reaching a start time t0, the voltage of VP is VMIN, as shown at 701. The voltage of VO is approximately the same amplitude but opposite polarity of VP, or approximately -VLIM, as shown in 901. Z1 is off in this case, making IZ zero. The current flowing through N16 establishes a gate-source voltage, which is reflected as the gate-source voltage of N15. The N15 architecture constitutes an average of the currents directed by capacitors C1 and C2, which have only a relatively small source-drain voltage, such that when Z1 is off, the VCTL is actually connected to VN. As shown, the VCTL has a voltage of approximately zero, as shown as 903. In this manner, the controller 801 has minimal impact such that the negative adaptive charge pump 301 operates in a normal manner such that the VO system is approximately - VP.

The VP line increases linearly as shown at 705 towards the VTH. When VP is VTH or lower than VTH, the voltage of VO drops at approximately the same rate as VP rises to maintain its voltage at the same amplitude as VP but with the opposite polarity (-VP), as shown at 905. The voltage of the VCTL is maintained at approximately zero, as shown at 903. At time t1, VP reaches VTH such that VO reaches -VTH, which has approximately the same amplitude and opposite polarity as VP.

When the voltage of VP exceeds VTH after time t1, as shown at 709, the voltage between VP and VO tends to exceed VLIM, and Z1 provides a non-zero current IZ from node 806, due to the drain-source current of P16. The fact that it is fixed due to the configuration of the current mirror, thereby reducing the level of IM. The gate-to-source voltage of N16 is reduced, thus reducing the gate-source voltage of N15, so that during charge pump operation, N15 draws less current from its drain to VCTL, which is used to supply current to C1. And C2, and thus eventually to C3. The voltage level of the VCTL increases linearly, as shown at 909, which is approximately twice the amount of VP over VTH, such that the voltage of VO increases by approximately the same amount as VP, as shown at 907, to maintain the relationship between VP and VO. The difference is approximately VLIM. At time t2, VP reaches VLIM and is then held at VLIM. After time t2, when VP is VLIM, VO is maintained fairly stable at approximately 0, while VCTL is ultimately settled at approximately VLIM.

Although the present invention has been described in considerable detail with reference to certain preferred embodiments thereof, other aspects and variations are possible and contemplated. It should be understood by those of ordinary skill that the present invention can be readily utilized as a basis for designing or modifying other structures without departing from the spirit and scope of the invention as defined by the appended claims. For the same purpose of providing the present invention.

100. . . Electronic device

101. . . battery

103. . . Power adapter

105. . . Voltage selection (VSEL) circuit

107. . . DC to DC switching voltage regulator

109. . . processor

111. . . Memory

113. . . Support device

114. . . Appropriate interface

200. . . Integrated circuit

201. . . Positive adaptable charge pump

203. . . Conductive path

205. . . Conductive path

207. . . Positive voltage rail

209. . . Amplifier

211. . . Clock circuit

300. . . Integrated circuit

301. . . Negative adaptive charge pump

307. . . Negative voltage rail

401. . . Controller

403. . . inverter

601. . . Battery

602. . . node

604. . . node

606. . . node

608. . . node

701. . . VMIN

703. . . 2VMIN

705. . . VP increase

706. . . Increase in VCTL

707. . . VO increase

709. . . VP increase

710. . . Reduction of VCTL

801. . . Controller

803. . . Battery

802. . . node

804. . . node

806. . . node

808. . . node

901. . . -VMIN

903. . . VN(0)

905. . . VO reduction

907. . . VO increase

909. . . Increase in VCTL

With reference to the above description and the following figures, the benefits, features and advantages of the present invention will become easier to understand, among which:

1 is a block diagram of an electronic device including a DC-to-DC switching voltage regulator that provides an output voltage adjustment to a load;

2 is a simplified block diagram of an integrated circuit including a positively adaptable charge pump implemented in accordance with one embodiment;

3 is a simplified block diagram of an integrated circuit including a negatively adaptable charge pump implemented in accordance with one embodiment;

Figure 4 is a schematic and block diagram of the positive adaptable charge pump of Figure 2 in accordance with one embodiment;

Figure 5 is a timing diagram of voltage versus time for various nodes for displaying the operation of the positive adaptive charge pump of Figure 4;

Figure 6 is a schematic illustration of the controller of Figure 4 in accordance with one embodiment;

Figure 7 is a plot of VP, G, and VCTL versus time, which is plotted in the following cases: VP is increased by a minimum level VMIN below VTH to the maximum level VLIM to display the control shown in Figure 6. The operation of the positive adaptive charge pump of Figure 4;

Figure 8 is a schematic and block diagram of the negative adaptive charge pump of Figure 3 in accordance with one embodiment;

Figure 9 is a plot of VP, VO, and VCTL versus time, which is plotted in the following cases: VP is increased by a minimum level VMIN below VTH to the maximum level VLIM to show the negative adaptability of Figure 8. Charge pump operation.

201. . . Positive adaptable charge pump

401. . . Controller

403. . . inverter

Claims (20)

An adaptive charge pump, comprising: first and second nodes, which are in a state of opposite state between the first and second supply voltages; and a first capacitor connected to the first node And a third capacitor between the second node and the fourth node, the third capacitor is connected between an output node and the second supply voltage; a first type of transistor having a conductivity type, having a first current terminal connected to a control node, having a second current terminal connected to the third node and having a control terminal connected to the fourth node; a second transistor having the first conductivity type having a first current terminal connected to the control node, having a second current terminal connected to the fourth node and having a connection to the third node a control terminal; a third transistor having a second conductivity type having a first current terminal connected to the third node, having a second current connected to the output node And a control terminal connected to the fourth node; a fourth transistor having the second conductivity type having a first current terminal connected to the fourth node, having a first connection to the output node a second current terminal having a control terminal connected to the third node; and a controller, when the voltage difference between the output node and the second supply voltage does not exceed a limit voltage, the controller controls the control node to become A voltage level that is approximately the same as the first supply voltage. Otherwise, the controller controls the voltage of the control node to prevent the voltage difference from exceeding the limit voltage. The adaptive charge pump of claim 1, wherein: the second supply voltage has a reference voltage level, and wherein the first supply voltage has a positive supply voltage level; wherein the first conductive type Is N-type, and wherein the second conductivity type is P-type; and wherein the output node has a voltage level twice the voltage level of the first supply voltage, reaching the limit voltage, and wherein When the first supply voltage is greater than one half of the limit voltage, the output node is maintained at the limit voltage. The adaptive charging pump of claim 1, wherein: the first supply voltage has a reference voltage level, and wherein the second supply voltage has a positive supply voltage level; wherein the first conductive type Is a P-type, and wherein the second conductivity type is an N-type; wherein, when the second supply voltage is less than or equal to one-half of the limit voltage, the output node and the second supply voltage have the same The amplitude has an opposite polarity, wherein when the second supply voltage is greater than one half of the limit voltage, the output node has the second supply voltage minus the voltage level of the limit voltage. The adaptive charge pump of claim 1, wherein the controller comprises: a fifth transistor having the second conductivity type, having a first current terminal receiving the first supply voltage, having a connection a control terminal to a fifth node, and a second current terminal connected to the control node; a sixth transistor having the second conductivity type, having a first current terminal receiving the first supply voltage, And a second current terminal and a control terminal connected to the fifth node; a current device connected between the first supply voltage and a sixth node; having the seventh conductivity type a transistor having a first current terminal connected to the fifth node, having a control terminal connected to the sixth node, and having a second current terminal connected to a seventh node; having the first conductive An eighth type of transistor having a first current terminal connected to the seventh node and having a control terminal connected to an eighth node, And having a second current terminal receiving the second supply voltage; a ninth transistor having the first conductivity type, having a first current terminal and a control node connected together at the eighth node, and having a a second current terminal receiving the second supply voltage; a resistor connected between the sixth node and the eighth node; and a Zener diode connected to the output node and the seventh node between. An adaptable charge pump according to claim 4, further comprising a smoothing capacitor connected between the first supply voltage and the control node. The adaptive charge pump of claim 4, wherein the fifth electro-crystal system is significantly larger than the sixth transistor, wherein the current device and the resistor are configured to operate the seventh transistor under saturation, And wherein the eighth and ninth electro-crystal systems are in a current mirror configuration. The adaptive charging pump of claim 4, wherein: the second supply voltage has a reference voltage level, and wherein the first supply voltage has a positive supply voltage level; wherein the first conductive pattern Is N-type, and wherein the second conductivity type is P-type; wherein the Zener diode has an anode connected to the seventh node and a cathode connected to the output node; and wherein The current device supplies current to the sixth node. The adaptive charging pump of claim 4, wherein: the first supply voltage has a reference voltage level, and wherein the second supply voltage has a positive supply voltage level; wherein the first conductive type Is a P-type, and wherein the second conductivity type is an N-type; wherein the Zener diode has an anode connected to the output node and a cathode connected to the seventh node; and wherein The current device draws current from the sixth node. An electronic device comprising: a supply input receiving an adjustment voltage, and a reference input receiving a reference voltage; a voltage rail; and a charge pump coupled to the supply input and the reference input And having an output terminal connected to the voltage rail, wherein the charging pump drives the voltage rail to become twice the voltage level of the adjustment voltage to reach a limiting voltage level, wherein the charging pump system The first and second nodes are connected to the opposite state between the adjustment voltage and the reference voltage; the first capacitor is connected between the first node and a third node; a capacitor connected between the second node and a fourth node; a third capacitor connected between the second node and the output terminal; a first N-type transistor having a connection a current terminal between the control node and the third node, and having a control terminal connected to the fourth node; a second N-type transistor having a connection to the control section And a current terminal between the fourth node, and having a control terminal connected to the third node; a first P-type transistor having a current terminal connected between the third node and the output terminal, And having a control terminal connected to the fourth node; the second P-type electro-optic system has a current terminal connected between the fourth node and the output terminal, and has a control terminal connected to the third node; And a controller, when the voltage difference between the output terminal and the reference voltage does not exceed the limit voltage level, the controller controls the control node to be at the same voltage level as the adjustment voltage; otherwise, the controller The voltage of the control node is controlled to prevent the voltage difference from exceeding the limit voltage level. The electronic device of claim 9, further comprising: an adjuster that provides the adjusted voltage with respect to the reference voltage; wherein the voltage rail, the clock node, and the charge pump system are integrated into one And a memory and a memory, the processor and the memory system are coupled together through an interface and receive the adjustment voltage and the reference voltage from the regulator. The electronic device of claim 9, wherein the controller comprises: a third P-type transistor having a current terminal connected between the supply input and the control node and having a connection to a fifth node a control terminal; a fourth P-type transistor having a current terminal connected between the supply input and the fifth node and having a control terminal connected to the fifth node; a current device from the supply Input current is supplied to a sixth node; a third N-type transistor having a current terminal connected between the fifth node and a seventh node and having a control terminal connected to the sixth node; fourth An N-type transistor having a current terminal connected between the seventh node and the reference input and a control terminal connected to an eighth node; a fifth N-type transistor having a connection to the first a current terminal between the eight nodes and the reference input and having a control terminal connected to the eighth node; a resistor connected between the sixth and eighth nodes; a fourth capacitor , Which is connected between the supply line and the control input node; and zener diode having an anode connected to the seventh node and having the cathode connected to the output terminal of. The electronic device of claim 11, wherein the third P-type electro-crystal system is significantly larger than the fourth P-type transistor, wherein the current device and the resistor are configured to operate the third N-type transistor Under saturation, and wherein the fourth and fifth N-type electro-crystalline systems are in a current mirror configuration. An electronic device comprising: a supply input receiving an adjustment voltage, and a reference input, the reference input receiving a reference voltage; a voltage rail; and a charge pump coupled between the supply input and the reference input And having an output terminal connected to the voltage rail, wherein the charging pump drives the voltage rail to be about the same voltage level as the adjustment voltage and has opposite polarity to reach a threshold voltage level, wherein The charging pump includes: first and second nodes connected to the opposite state between the adjustment voltage and the reference voltage; the first capacitor is connected to the first node and a third node a second capacitor connected between the second node and a fourth node; and a third capacitor connected between the second node and the output terminal; a first P-type transistor, a current terminal connected between a control node and the third node, and having a control terminal connected to the fourth node; a second P-type transistor having a current terminal connected between the control node and the fourth node, and having a control terminal connected to the third node; a first N-type transistor having a connection to the third node and the output terminal a current terminal, and having a control terminal connected to the fourth node; a second N-type transistor having a current terminal connected between the fourth node and the output terminal, and having a connection to the a control terminal of the third node; the controller, when the voltage difference between the output terminal and the adjustment voltage does not exceed twice the threshold voltage level, the controller controls the control node to be approximately the same as the reference voltage The voltage level, otherwise, the controller controls the voltage of the control node to prevent the voltage difference from exceeding twice the threshold voltage level. The electronic device of claim 13, further comprising: an adjuster that provides the adjusted voltage with respect to the reference voltage; wherein the voltage rail, the clock node, and the charge pump system are integrated into one And a memory and a memory, the processor and the memory system are coupled together through an interface and receive the adjustment voltage and the reference voltage from the regulator. The electronic device of claim 13, wherein the controller comprises: a third N-type transistor having a current terminal connected between the reference input and the control node and having a connection to a fifth node a control terminal; a fourth N-type transistor having a current terminal connected between the reference input and the fifth node and having a control terminal connected to the fifth node; a current device, which is a a six-node providing current to the reference input; a third P-type transistor having a current terminal connected between the fifth node and a seventh node and having a control terminal connected to the sixth node; fourth a P-type transistor having a current terminal connected between the seventh node and the supply input and having a control terminal connected to an eighth node; a fifth P-type transistor having a connection to the first a current terminal between the eight nodes and the supply input and a control terminal connected to the eighth node; a resistor connected between the sixth and eighth nodes; a fourth capacitor And a Zener diode having a cathode connected to the seventh node and having an anode connected to the output terminal. The electronic device of claim 15, wherein the third N-type electro-crystal system is significantly larger than the fourth N-type transistor, wherein the current device and the resistor are configured to operate the third P-type transistor in saturation Below, and wherein the fourth and fifth P-type electro-crystalline systems are in a current mirror configuration. A method for adaptively controlling a charge pump, comprising: connecting the charge pump to a control node; and switching a clock of the charge pump to a supply voltage level to charge the output of the charge pump Monitoring the output of the charge pump; maintaining the control node at a supply voltage level when the magnitude of the supply voltage is less than or equal to a threshold level; and adjusting the control when the magnitude of the supply voltage exceeds the threshold level Node to maintain the output of the charge pump at a limit level. The method of claim 17, wherein: the toggle input of the charge pump comprises charging the output of the charge pump to be twice the supply voltage level; and wherein adjusting the control node comprises reducing the charge The amplitude of the node is approximately the same amount as the supply voltage amplitude exceeds the threshold level. The method of claim 17, wherein: the toggle input of the charge pump comprises: charging the output of the charge pump to have the same amplitude as the supply voltage level and having an opposite polarity; and wherein adjusting the The control node includes increasing the amplitude of the charging node by approximately twice the amount of the supply voltage amplitude exceeding the threshold level. The method of claim 17, further comprising: developing a control current through a control device connected between a supply voltage node and the control node; when the magnitude of the supply voltage is less than or equal to the threshold level Maintaining the control current at a fixed level; and adjusting the control current to adjust the control node when the magnitude of the supply voltage exceeds the threshold level.