TWI517753B - Light-emitting diode driver with single-ended single-ended main inductor conversion architecture with power correction - Google Patents

Description

Light-emitting diode driver with single-stage single-ended main inductance conversion architecture with power correction function

The invention relates to a solid-state lighting driver, in particular to a single-stage SEPIC LED with PFC (Power Factor Correction) function (Single-Ended Primary Inductance Converter Light-Emitting Diode) Diode) driver.

Electricity is the primary issue for humanity to continue to move toward civilization. As environmental protection and sustainable development have become global consensus, and primary energy prices continue to soar, how to use existing energy more efficiently and actively develop new alternative energy sources, It is the primary task of the engineering and technology community. Lighting is closely related to people's lives. With the continuous improvement of living standards and the popularity of household appliances, the power consumption is constantly rising. The power consumption of lighting equipment is constantly improving. Therefore, how to improve lighting efficiency and reduce lighting power consumption is a must. The problem. Global lighting power consumption has accounted for more than 20% of total annual electricity consumption. China's annual electricity consumption is about 26 billion kWh. It is estimated that if you use Light-Emitting Diode (LED) lighting, you can save about With 10.7 billion kWh of electricity, the power saving is about 41%. At present, LED has gradually replaced existing incandescent lamps. It is estimated that it will replace fluorescent lamps in 2012, and LEDs will officially enter the mainstream market for general lighting applications. Under the continuous fermentation of energy conservation and environmental protection issues, the United States, Britain, Japan and the European Union have announced that they will completely ban and ban the production of incandescent lamps from 2014, and actively promote the use of LED lighting projects. The EU plans to set energy efficiency standards. Step by step Eliminating incandescent lamps, and Australia's announcement that it will completely ban incandescent lamps from 2010 will accelerate the growth of the global solid-state lighting (SSL) industry.

The main issues of LEDs used in lighting systems are: heat dissipation (lighting efficiency drops as the temperature of the wafer rises), high-efficiency lighting drivers, and LED luminaire designs. Although the main operating parameters of LED are simple, the forward voltage drop (V _FD ) is a negative temperature coefficient, which will decrease with the increase of temperature, which will increase the current and exacerbate the problem of heat dissipation and overcurrent fault. Therefore, in order to work optimally Efficiency levels and reduced light decay maintain a constant light output, requiring precise control of the LED current. In addition, since the life of the LED is very long, the control circuit needs to be simplified and strong, so as to shorten the working life of the entire LED module due to the premature failure of the control circuit.

It is an object of the present invention to disclose a single-stage SEPIC LED driver with PFC functionality, which has a single-stage SEPIC architecture that achieves high power efficiency and high efficiency at low cost.

Another object of the present invention is to disclose a PFC-enabled single-stage SEPIC LED driver having a single-stage SEPIC architecture that provides a buck or boost output voltage.

Another object of the present invention is to disclose a PFC-enabled single-stage SEPIC LED driver with a single-stage SEPIC architecture that allows for a wide range of input voltages.

Another object of the present invention is to disclose a PFC-enabled single-stage SEPIC LED driver with a single-stage SEPIC architecture that minimizes input current ripple to minimize input filter requirements.

Another object of the present invention is to disclose a PFC-enabled single-stage SEPIC LED driver with a single-stage SEPIC architecture centered on a digital controller to meet the needs of power management (smart grid) and in a more flexible manner. Develop high power density and cost effective power supplies.

For the above purposes, a PFC-enabled single-stage SEPIC LED driver is proposed having a voltage dividing circuit for dividing a full-wave rectified voltage to generate a first current upper limit signal; a SEPIC circuit having a first inductor, a second inductor, a power conversion capacitor, a diode, an output capacitor, a power switch, a current sense resistor, and a third inductor, wherein the first The inductor, the second inductor, the power conversion capacitor, the diode, the output capacitor, and the power-on relationship are used to provide a critical conduction energy conversion mode, wherein the current sensing resistor is used to Converting a current flowing through the power switch into a current sensing signal; and the third inductor is configured to generate a zero current detection signal; a PFC PWM (Power Factor Correction Pulse Width Modulation) a modulation controller for generating a first PWM according to the first current upper limit signal, the current sensing signal, the zero current detection signal, and a voltage feedback signal (Pulse Width Modula) a pulse width modulation signal to drive the power switch to perform the critical conduction energy conversion mode, wherein the PFC PWM controller is responsive to the voltage feedback signal and a voltage of one of its internal reference voltages The difference generates an error signal, and generates a second current upper limit signal according to the product of the error signal and the first current upper limit signal; the PFC PWM controller determines the first PWM according to the zero current detection signal a PFC PWM controller determines a point at which the conduction level of the first PWM signal ends when the current sensing signal climbs up to a level of the second current upper limit signal; a first resistor, one end of which is coupled to an output voltage, and a second resistor coupled to the other end of the first resistor to provide The voltage feedback signal, and the other end of the signal is coupled to a reference ground; a third resistor has one end coupled to the first resistor and the second resistor, and the other end coupled to the first resistor Adjusting a voltage; an LED module connected in series with a constant current regulating circuit to form a load of the output voltage, wherein the constant current adjusting circuit has a plurality of NMOSs (N-Mental-Oxide-Semiconductor; N-type metal-oxide layer a semiconductor, each of the NMOS transistors having a drain, a gate, and a source, the drain being coupled to a cathode of one of the LED modules to provide a plurality of drains One of the voltage signals, the gate system and one of the plurality of gate drive signals are coupled, and the source is coupled to the reference ground via a resistor to provide a plurality of source voltages a signal in the signal; a microcontroller for generating the adjustment voltage according to the plurality of gate voltage signals, and a plurality of voltage differences between the brightness adjustment signal and the plurality of source voltage signals The value generates a plurality of second PWM signals, wherein The duty cycle of the second PWM signal is proportional to the voltage difference; and when the level of the plurality of drain voltage signals rises/falls due to a change in the voltage across the LED module, The microcontroller increases/decreases the voltage value of the adjustment voltage; a fourth resistor has one end coupled to the DC voltage; and a fifth resistor is a variable resistor, one end of which is coupled to the fourth resistor The other end is coupled to provide the brightness adjustment signal, and the other end is coupled to the reference ground; and a gate driving circuit is configured to generate the complex number according to the plurality of second PWM signals One gate drive signal.

The detailed description of the drawings and the preferred embodiments are set forth in the accompanying drawings.

10‧‧‧Bridge rectifier

20‧‧‧voltage circuit

30‧‧‧SEPIC circuit

31‧‧‧First inductance

32‧‧‧second inductance

33‧‧‧Power Conversion Capacitor

34‧‧‧ diode

35‧‧‧ output capacitor

36‧‧‧Power switch

37‧‧‧ Current sense resistor

38‧‧‧ Third inductance

40‧‧‧PFC PWM controller

41‧‧‧First resistance

42‧‧‧second resistance

43‧‧‧ Third resistor

50‧‧‧LED module

60‧‧‧Constant current regulation circuit

70‧‧‧Microcontroller

71‧‧‧fourth resistor

72‧‧‧ fifth resistor

73‧‧‧ gate drive circuit

1 is a system circuit diagram of an embodiment of a PFC-enabled single-stage SEPIC LED driver of the present invention.

Figure 2 shows a single-stage SEPIC circuit diagram with PFC functionality.

Figure 3 is a timing diagram of the theoretical voltage and current waveform operation for a single-stage SEPIC.

Figure 4 is an equivalent circuit diagram of mode one for a single-stage SEPIC.

Figure 5 is an equivalent circuit diagram of mode 2 of a single-stage SEPIC.

Figure 6 is an equivalent circuit diagram of mode three for a single-stage SEPIC.

Figure 7 is an equivalent circuit diagram of a single-stage SEPIC coupled inductor.

FIG. 8 is a circuit diagram of a single-stage SEPIC with a PFC function controlled by a digital bit according to the present invention.

9 is a sine wave enveloping line of the ( i _{L 1} + i _{L 2} ) current waveform and its peak value when the SEPIC with PFC function of the present invention corresponds to the switch on/off operation.

FIG. 10 is a schematic diagram of a feedback loop of a power supply voltage dynamic adjustment control mechanism for an LED string according to the present invention.

FIG. 11 is a schematic diagram of an intelligent LED string supply voltage dynamic adjustment control operation program according to the present invention.

Fig. 12 (a) is a diagram showing an LED constant current driving amplifier and a dimming control circuit according to the present invention.

Figure 12 (b) is a schematic diagram of a dimming linear range provided by the circuit of Figure 12 (a).

FIG. 13 is a block diagram of a digital fault detection and protection mechanism used in the present invention.

FIG. 14 is a schematic diagram of an operation procedure of LED short circuit and open circuit fault discrimination and DVC control mechanism adopted in the present invention.

1 is a system circuit diagram of an embodiment of a PFC-enabled single-stage SEPIC LED driver of the present invention. As shown in FIG. 1 , the LED driver of the present invention has a bridge rectifier 10 , a voltage dividing circuit 20 , a SEPIC circuit 30 , a PFC PWM controller 40 , a first resistor 41 , a second resistor 42 , and a first The three resistors 43, the LED module 50, the constant current adjusting circuit 60, a microcontroller 70, a fourth resistor 71, a fifth resistor 72, and a gate driving circuit 73.

The bridge rectifier 10 is configured to generate a full-wave rectified voltage V _IN according to an alternating voltage V _AC .

The voltage dividing circuit 20 is configured to divide the full-wave rectified voltage V _IN to generate a first current upper limit signal V _T1 .

The SEPIC circuit 30 has a first inductor 31, a second inductor 32, a power conversion capacitor 33, a diode 34, an output capacitor 35, a power switch 36, a current sense resistor 37, and a third inductor. 38.

The first inductor 31, the second inductor 32, the power conversion capacitor 33, the diode 34, the output capacitor 35, and the power switch 36 are used to provide a critical conduction energy conversion mode; the current sensing resistor 37 is used to flow through The current of the power switch 36 is converted into a current sensing signal V _CS ; and the third inductor 38 is used to generate a zero current detecting signal V _ZCD . The detailed operation of the SEPIC circuit 30 will be described later.

The PFC PWM controller 40 can be implemented by a microcontroller and a gate driving circuit for using the first current upper limit signal V _T1 , the current sensing signal V _CS , the zero current detecting signal V _ZCD , and a voltage back The signal V _FB generates a first PWM (pulse width modulation) signal V _PWM to drive the power switch 36 to perform the critical conduction energy conversion mode, wherein the PFC PWM controller 40 is voltage-dependent. The voltage difference between the signal V _FB and one of its internal reference voltages generates an error signal, and a second current upper limit signal is generated according to the product of the error signal and the first current upper limit signal V _T1 ; the PFC PWM controller 40 Determining the on-time of the first PWM signal V _PWM according to the zero current detection signal V _ZCD ; and the PFC PWM controller 40 is when the current sensing signal V _CS climbs up to the level of the second current upper limit signal The point at which the conduction level of the first PWM signal _VPWM ends is determined.

Due to the negative feedback, the voltage feedback signal V _FB will eventually approach the reference voltage, and the envelope shape of the current sensing signal V _CS will approach the envelope shape of the first current upper limit signal V _T1 . Accordingly, a PFC (power factor correction) function and a rated output voltage V _LED can be simultaneously provided.

The first resistor 41, the second resistor 42, and the third resistor 43 are configured to generate a voltage feedback signal V _FB according to the output voltage V _LED and an adjustment voltage V _X , wherein one end of the first resistor 41 is coupled to the output voltage V _LED , and the other end is coupled to the second resistor 42 and the third resistor 43 to provide a voltage feedback signal V _FB ; one end of the second resistor 42 is coupled to the first resistor 41 and the other end is coupled to the other end The first resistor 41 is coupled to the first resistor 41 and the second resistor 42 , and the other end is coupled to the adjustment voltage V _X . The level of the voltage feedback signal V _FB rises/falls due to the increase/decrease of the output voltage V _LED or the adjustment voltage V _X .

The LED module 50 is connected in series with the constant current regulating circuit 60 to form a load of the output voltage V _LED . The constant current adjusting circuit 60 has a plurality of NMOS transistors, each of the NMOS transistors has a drain, a gate, and a source, and the drain is coupled to the cathode of one of the LED modules 50. Providing one of a plurality of gate voltage signals V _D1 -V _Dn , the gate system is coupled to one of the plurality of gate drive signals V _G1 -V _Gn , and the source is coupled via a signal A resistor is coupled to the reference ground to provide one of a plurality of source voltage signals V _S1 -V _Sn .

The microcontroller 70 is configured to generate the adjustment voltage V _X according to the plurality of gate voltage signals V _D1 - V _Dn , and the brightness adjustment signal V _DIM and the plurality of source voltage signals V _S1 - The plurality of voltage differences between V _Sn generates a plurality of second PWM signals V _PWM1 - V _PWMn , wherein an individual duty ratio of the plurality of second PWM signals V _PWM1 - V _PWMn is The voltage difference is proportional; and when the level of the plurality of gate voltage signals V _D1 -V _Dn rises/falls due to the voltage variation of the LED module 50, the microcontroller 70 increases/decreases the adjustment voltage. The voltage value of V _X .

One end of the fourth resistor 71 is coupled to the DC voltage V _CC , and the other end is coupled to the fifth resistor 72 to provide the brightness adjustment signal V _DIM . The fifth resistor 72 is a variable resistor having one end coupled to the fourth resistor 71 and the other end coupled to the reference ground.

The gate driving circuit 73 is configured to generate the plurality of gate driving signals V _G1 -V _Gn according to the plurality of second PWM signals V _PWM1 -V _PWMn .

Due to the effect of the negative feedback, the levels of the plurality of source voltage signals V _S1 -V _Sn will eventually approach the level of the brightness adjustment signal V _DIM , so that the LED module 50 provides the user's desired Lighting brightness.

The working principle of the present invention will be further explained below by equation derivation.

A. Single-stage SEPIC operating principle with PFC function:

Figure 2 shows a single-stage SEPIC circuit architecture with PFC function. The circuit is mainly composed of coupled inductors L ₁ and L ₂ , power conversion capacitor C ₁ and output capacitor C ₂ , diode D ₁ and power switch Q ₁ . Wherein the number of turns of the coupled inductor L ₁ is greater than L ₂ . Figure 3 shows the theoretical timing diagram of voltage and current waveforms for a single-stage SEPIC. A switching cycle can be divided into three operating modes, which are discussed below.

Mode 1 (t ₀ ~ t ₁ ) : As shown in Figure 4, the single-stage SEPIC is the equivalent circuit of mode 1. The starting condition of this mode is that the power switch Q _{1 is} turned on, and the switch Q _{1 is} turned on at time t ₀ , C _discharging the storage inductor L ₂ is coupled to the charging energy, the inductor L ₂ is coupled to a positive voltage RBI, i _L2 current ramps up. Since the number of coupled inductors L _{1 is} greater than the number of coupled inductors L ₂ , the coupled inductor L _{1 has} a primary induced voltage of (N ₁ /N ₂ )V _in , where the N ₁ voltage is greater than V _in and the coupled inductor L ₁ is one. In the release state, the current of the coupled inductor L ₁ decreases linearly. At this time, the diode D _{1 is} turned off, and the load energy is separately supplied from the output capacitor C ₂ . The coupling voltages L ₁ , L ₂ , and the voltage across the diode D ₁ are as follows: v _{L 2} ( t )= v _in ( t ) (1)

v _{D 1} ( t )= V _o + v _in ( t ) (3)

Where v _in ( t )= V _m |sin( ωt )|, ω =2 πf , V _m (= V _rms ) is the maximum line voltage, f is the line voltage frequency, which is the voltage twice the line frequency after full-wave rectification, and n is the coupled inductor turns ratio (N ₂ /N ₁ ).

_{Mode 2 (t 1 ~ t 2} ): As shown in FIG. 5 is an equivalent circuit two modes of operation, the initial condition of this mode is the power switch Q ₁ t ₁ is turned off at the time, diode D ₁ is turned on, and V _in provides energy to the load via the coupled inductor L ₁ , the capacitor C ₁ and the diode D ₁ . At this time, the coupled inductor L ₁ is in an energy storage state, and the inductor current i _L1 linearly rises; the coupled inductor L ₂ releases energy, i _L2 The current decreases linearly; the voltage V _ds1 across the power switch begins to increase. When the voltage of v _{ds 1} reaches V _o +V _in , the diode D _{1 is} turned off, and the voltage stress at both ends of Q ₁ is: v _{ds 1} = V _o + v _in ( t ) (4)

Mode 3 (t ₂ ~ t ₃ ) : As shown in Figure 6, the equivalent circuit of mode three operation, the starting condition of this mode is that the coupled inductor L ₂ current i _L2 linearly drops to 0 at time t ₂ , at this time power When the switch Q ₁ is turned off, the coupled inductor L ₁ current i _L1 continues to rise linearly, and the coupled inductor L ₂ current i _L2 drops to a negative value, and the diode D ₁ is turned on until the coupled inductor current i _L1 and i _L2 are added. When it is zero, the diode D ₁ is turned off, and the circuit action returns to mode one. The operation of the power switch Q ₁ and the diode D ₁ also achieves zero current switching (ZCS) operation.

B. Coupling inductance model establishment:

If the SEPIC two inductors are co-wound on the same core, a coupling inductor is formed. The coupled inductor can save one core and reduce the circuit size. If the correct turns ratio is designed, the input current can theoretically be zero. Save input filter usage. Figure 7 shows the equivalent circuit diagram of a single-stage SEPIC coupled inductor. In the figure, L _{l 1} and L _{l 2} are the leakage inductance of the primary side and the secondary side of the coupled inductor, respectively. L _m is the magnetizing inductance (magnetizing inductance). ), n is the turns ratio, and the relationship between the terminal voltage and current can be described as:

If the voltage across the coupled inductor is equal ( v ₁ = v ₂ ), then (7) is substituted into equations (5) and (6), which can be simplified:

Let di ₁ ( t ) / dt and di ₂ ( t ) / dt current be 0, then we can derive the following equation: L _{l 2} = n (1- n ). L _m (9)

L _{l 1} =( n -1). L _m (10)

Substituting (9) and (10) into (5) and (6) respectively, the following program can be obtained:

Where L _eq1 and L _eq2 are derived separately, which can be obtained as

From Figure 7, if the secondary side current i ₂ is zero, then = v ₂ , the ratio of the terminal voltage can be written by the ratio conversion

(15) If the voltage across the coupled inductor is equal [ v ₂ ( t )= v ₁ ( t )], then

The (16) are substituted into the formula (13) and (14), to obtain _{L eq 1 = L m + L} l 1 (17)

L _{eq 2} =∞ (18)

From the above derivation, for a SEPIC PFC converter using a coupled inductor, if the 匝 ratio of the coupled inductor can meet the condition of (16), the theoretical chopper control requirement is met, and the voltage across the secondary side leakage inductor Zero, no secondary current, the inductance of the input can be regarded as infinite, in theory, it can have the characteristics of input currentless chopping. However, it is difficult to satisfy the equation (16) when the actual inductor is wound, and because the chopper voltage exists on C ₁ , the voltage on the two inductors will not be exactly equal, so the inductance at the input end will be quite large, and the large input inductor will be large. Helps eliminate the switching frequency chopping component of the input current.

C. Circuit operation derivation:

Figure 8 shows a single-stage SEPIC circuit diagram with digital control of the PFC function, and a design specification sheet for one of the single-stage SEPIC circuits is shown below.

Similar to the analog CRM (critical conduction mode) PFC PWM IC, the digitally controlled PFC must be used for input sine wave voltage, switching current, zero current detection, and output voltage sampling, but these sampled signals must be made first. Analog digital conversion, the resulting digital sensing signal is passed through a digital filter and sent to a digital PID (proportional integral derivative) to complete the closed loop digital control mechanism. In Figure 8, the input mains voltage is pure sine wave and the bridge rectifier is ideal, then the double-line sine wave after bridge rectification can be expressed as

Where V _m is the maximum value of the sine wave V _rms , f is the mains frequency 50/60Hz. If the switching frequency f _{s is} much larger than f , θ can be regarded as a constant value during one switching cycle. When the current of the switch Q ₁ increases to be equal to the sensed sinusoidal voltage value, the switch will be turned off, and the peak current of the switch will follow the reference value of the sine wave voltage, which can be expressed as i _pk ( θ ) = I _pk . |sin( θ )| (20)

In this case, the inductor currents i _L1 and i _L2 can be expressed as

When operating in the critical conduction mode, when the diode current reaches zero, the switch will turn on immediately, at which time Q ₁ current i _{Q 1} = i _{L 1} + i _{L 2} , since i _{L 2} initial current I _{L 20} is negative , then I _{L 10} - I _{L 20} =0, then the peak current of the switch obtained by (20) is

Figure 9 shows the sine-wave envelope of the ( i _{L 1} + i _{L 2} ) current waveform and its peak when the SEPIC with PFC function corresponds to the switch on/off operation.

Then the switch on time t _on is obtained by (23)

Where L _e is equal to L _{1 in} parallel with L ₂ , and it is known from equation (24) that the switch-on time of the PPIC-enabled SEPIC for CRM operation is independent of θ.

In addition, the volt-second balance of the inductor L ₂ is available.

It can be seen from equation (25) that the switching off time of the PPIC-enabled SEPIC for CRM operation is related to θ. Knowing the conduction and cut-off time of the switch, the switching frequency f _s can be obtained as

Then it is balanced by the amount of electricity (Amp) of C ₁

When I _{L 10} - I _{L 20} =0, I _{L 10} ( θ ) can be obtained as

Further, i _L of the average current I _{1 L 1} is

among them . It can be seen from equation (29) that the input current is not a pure sine wave, and the amount of distortion it contains is related to k _v . Even if the input current has some distortion, its power can be corrected quite well. Although the average voltage on C ₁ is equal to the supply voltage, there are some chopping voltages caused by the chopping of the inductor current, and the chopping voltage is

Substituting (19), (24), and (25) into (30), you can get

The average power at the input can be obtained as

Where the property function is defined as . According to the design specifications, the output power P _o , the efficiency η , and the input voltage V _rms are known, then the input current peak can be obtained as

By (24), (26), and (33), the switching frequency of the switch can be rewritten as

When the minimum input voltage V _{rms -min} and sin( θ )=1, the minimum switching frequency f _s-min is obtained.

LED power supply voltage dynamic control (DVC) mechanism:

A. DVC action principle and control mechanism:

FIG. 10 is a schematic diagram of a feedback loop of a power supply voltage dynamic adjustment control mechanism for an LED string according to the present invention. As shown in FIG. 10, a drain voltage V _D is processed by an LED string voltage drop detection circuit and sent to a DVC inference logic unit to generate a DVC control voltage V _DVC . The V _LED generated by this circuit can be expressed as

Where V _ref is one of the reference voltages of the coarse feedback control loop of the SEPIC converter, the coarse loop is mainly used to control the output voltage of the SEPIC converter; V _DVC is the dynamic adjustment controller output voltage for a fine return In the fine loop, the fine loop draws the LED string voltage drop. When the LED forward voltage changes, the V _LED voltage can be dynamically regulated to minimize the circuit power consumption. V _DVC can be added to the coarse loop to change the SEPIC converter output voltage to optimize the LED string supply voltage. If the maximum and minimum values of V _DVC V _{DVC, max} and V _{DVC, min,} the maximum and the minimum supply voltage of the LED strings is

Therefore, as long as V _ref , R ₁ , R _{2 are} designed according to the required V _LED , and then the appropriate R _DVC value is selected, the voltage range of the V _LED can be dynamically adjusted according to the V _DVC size of the output, and the adjustable range is about V. _{LED is about} ±20%. Through the digital DVC control mechanism, the two control loops do not require very precise compensation limits as used in conventional dc-dc converters. The power consumption of the constant current dimming MOSFET is P _FET = ( V _D - V _S ) × I _LED .

Figure 11 shows the proposed intelligent LED string supply voltage dynamic adjustment control operation program. When the system starts to work, V _DVC will be equal to its preset value V _DVC,df , according to the (36) type corresponding SEPIC preset. The output is V _{LED, df} =V _ref (1+ R ₁ / R ₂ ). When the DVC detects a change in the forward voltage drop of the LED string, it begins to enter the automatic regulation V _LED operation procedure. When the LED string forward voltage drop V _FD becomes smaller, the drain voltage is sensed to increase, and the dynamic voltage regulation mechanism will increase the V _DVC . According to the formula (36), when the V _{DVC is} increased, the V _LED is reduced to reduce the power consumption of the circuit, thereby improving the performance of the driving circuit; on the other hand, when the forward voltage drop V _{FD of the} LED string becomes large, the 汲 is sensed. The pole voltage is reduced, and the dynamic voltage regulation mechanism will reduce the V _DVC . According to equation (36), as V _DVC decreases, the V _LED will increase to provide the required current demand. When V _DVC remains fixed, it indicates that V _{FD has} not changed, then DVC will maintain the original operating state, and DVC will memorize the optimal LED supply voltage after regulation.

B. Constant current control and dimming mechanism:

FIG. 12(a) is a diagram showing an LED constant current driving amplifier and a dimming control circuit according to the present invention, which uses a reference voltage of an analog comparator in the MCU 1 to determine a current value of a desired LED string. The value of V _Sx is sensed by the LED current sense resistor R _sx , and the I _{LED x} value is adjusted via the PWM modulation mode to meet the set brightness requirement. In addition, a kind of specific voltage V _dim input can be added as V _ref as linear dimming, and the dimming linear range is designed to be 10%~100%, as shown in Fig. 12(b). If V _dim <V _dim,max , then I _LED =V _dim /R _s , and if V _dim >V _dim,max , then I _LED =V _ref,df /R _s .

C. Fault detection and protection mechanism:

FIG. 13 is a block diagram showing a digital fault detection and protection mechanism further adopted by the present invention. In order for the drive circuit to work safely, there must be a fault detection and protection mechanism. In the LED aspect, it is judged whether the LED string has an open circuit or a short circuit fault by sensing the V _Dx voltage, and in the MOSFET of the constant current control, it is judged whether the MOSFET has an open circuit or a short circuit fault by sensing the V _Sx power. When the debug comparator senses an abnormal state, the DVC control mechanism will try to solve the problem and return V _Dx to the normal value. When the DVC control mechanism cannot be solved, the fault discriminating logic mechanism will determine that a fault has occurred, and The LED string that has an open or short circuit fault is automatically turned off and separated from the normal operation LED string to provide a fault warning. For example, when V _{Dx is} lower than a critical value V _D,th , the LED open-circuit detector output is Hi, and the DVC control mechanism also detects the low level V _Dx , so DVC will lower V _DVC and try to improve V _LED voltage, V _Dx returns to normal value, when the LED voltage increases to V _{LED, max} , V _Dx can not return to the normal value, then the fault discrimination and protection logic determines the LED open circuit fault, and sends the fault signal, the same reason LED short-circuit fault discrimination and protection are similar to open circuit. Figure 14 is a schematic diagram of the operation procedure of LED short-circuit and open-circuit fault discrimination and DVC control mechanism.

As can be seen from the above description, the single-stage SEPIC LED driver with PFC function of the present invention has the following advantages:

1. The SEPIC architecture of the present invention has better power factor correction performance.

2. The SEPIC architecture of the present invention provides a buck or boost output voltage.

3. The SEPIC architecture of the present invention allows for a wide range of input voltages.

4. The SEPIC architecture of the present invention minimizes input current ripple to minimize input filter requirements.

5. The single-stage SEPIC architecture with the digital controller as the core can meet the requirements of power management (smart grid), and can develop high power density and cost-effective power supply in a more flexible manner.

The disclosure of the present invention is a preferred embodiment. Any change or modification of the present invention originating from the technical idea of the present invention and being easily inferred by those skilled in the art will not deviate from the scope of patent rights of the present invention.

In summary, this case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first invention is practical and practical, and it is also in compliance with the patent requirements of the invention. I will be granted a patent at an early date.

10‧‧‧Bridge rectifier

20‧‧‧voltage circuit

30‧‧‧SEPIC circuit

31‧‧‧First inductance

32‧‧‧second inductance

33‧‧‧Power Conversion Capacitor

34‧‧‧ diode

35‧‧‧ output capacitor

36‧‧‧Power switch

37‧‧‧ Current sense resistor

38‧‧‧ Third inductance

40‧‧‧PFC PWM controller

41‧‧‧First resistance

42‧‧‧second resistance

43‧‧‧ Third resistor

50‧‧‧LED module

60‧‧‧Constant current regulation circuit

70‧‧‧Microcontroller

71‧‧‧fourth resistor

72‧‧‧ fifth resistor

73‧‧‧ gate drive circuit

Claims (4)

A light-emitting diode driver with a single-stage single-ended main inductance conversion architecture with power correction function, comprising: a voltage dividing circuit for dividing a full-wave rectified voltage to generate a first current upper limit signal a single-ended main inductor conversion architecture circuit having a first inductor, a second inductor, a power conversion capacitor, a diode, an output capacitor, a power switch, a current sense resistor, and a third An inductor, wherein the first inductor, the second inductor, the power conversion capacitor, the diode, the output capacitor, and the power-on relationship are used to provide a critical conduction energy conversion mode, The current sensing resistor is configured to convert a current flowing through the power switch into a current sensing signal; and the third inductor is configured to generate a zero current detecting signal; and a power factor correction pulse width modulation control And generating a first pulse width modulation signal to drive the power on according to the first current upper limit signal, the current sensing signal, the zero current detection signal, and a voltage feedback signal And performing the critical conduction energy conversion mode, wherein the power correction pulse width modulation controller generates an error signal according to a voltage difference between the voltage feedback signal and one of its internal reference voltages, and then The product of the error signal and the first current upper limit signal generates a second current upper limit signal; the power factor correction pulse width modulation controller determines the first pulse width modulation signal according to the zero current detection signal And a power factor correction pulse width modulation controller determines the first pulse width modulation signal when the current sensing signal climbs up to a level of the second current upper limit signal The point at which the conduction level ends; a first resistor, one end of which is coupled to an output voltage; a second resistor having one end coupled to the other end of the first resistor to provide the voltage feedback signal, and the other end coupled Connected to a reference ground; a third resistor having one end coupled to the first resistor and the second resistor, and the other end coupled to an adjustment voltage; a light emitting diode module, a certain current regulating circuit is connected in series to form a load of the output voltage, wherein the constant current adjusting circuit has a plurality of N-type metal-oxide-semiconductor transistors, and each of the N-type metal-oxide-semiconductor transistors has a a drain, a gate, and a source, the drain is coupled to a cathode of one of the light emitting diodes to provide a signal of a plurality of gate voltage signals, The gate system is coupled to one of the plurality of gate drive signals, and the source is coupled to the reference ground via a resistor to provide one of the plurality of source voltage signals; a device for generating a plurality of gate voltage signals Adjusting a voltage, and generating a plurality of second pulse width modulation signals according to a plurality of voltage difference values between the brightness adjustment signal and the plurality of source voltage signals, wherein the second pulse width modulation signal is occupied by The air ratio is proportional to the voltage difference; and the microcontroller is raised/decreased when the level of the plurality of drain voltage signals rises/falls due to a voltage change of the LED module The voltage value of the adjustment voltage is increased/decreased; a fourth resistor is coupled to the DC voltage at one end; a fifth resistor is a variable resistor, one end of which is coupled to the other end of the fourth resistor Coupling to provide the brightness adjustment signal, and the other end is coupled to the reference ground; a gate driving circuit for generating the plurality of gate driving signals according to the plurality of second pulse width modulation signals. The LED driver of the single-stage single-ended main inductance conversion architecture with the function correction function described in claim 1 further has a bridge rectifier for generating the full-wave rectified voltage according to an AC voltage. . The illuminating diode driver of the single-stage single-ended main inductance conversion architecture with the function correction function described in claim 1, wherein the microcontroller further has a fault detection and protection mechanism. The illuminating diode driver of the single-stage single-ended main inductance conversion architecture with the function correction function according to the first aspect of the patent application, wherein the power factor correction pulse width modulation controller can be a microcontroller and a gate The pole drive circuit is implemented.