TWI515801B - Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device - Google Patents
Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device Download PDFInfo
- Publication number
- TWI515801B TWI515801B TW100135037A TW100135037A TWI515801B TW I515801 B TWI515801 B TW I515801B TW 100135037 A TW100135037 A TW 100135037A TW 100135037 A TW100135037 A TW 100135037A TW I515801 B TWI515801 B TW I515801B
- Authority
- TW
- Taiwan
- Prior art keywords
- nitridation
- nitriding
- oxide layer
- layer
- nitridation step
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 112
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 title description 2
- 150000004706 metal oxides Chemical class 0.000 title description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 46
- 238000005121 nitriding Methods 0.000 claims description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims description 32
- 238000005496 tempering Methods 0.000 claims description 31
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 15
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 15
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 12
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 11
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 11
- 229910052707 ruthenium Inorganic materials 0.000 claims description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 230000035515 penetration Effects 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims description 2
- 238000006193 diazotization reaction Methods 0.000 claims 1
- 229910000484 niobium oxide Inorganic materials 0.000 claims 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 12
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910000420 cerium oxide Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 4
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 1
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Description
本發明是有關於一種半導體製程方法以及金氧半導體元件的製造方法。The present invention relates to a semiconductor process method and a method of fabricating a metal oxide semiconductor device.
隨著超大積體電路工業的發展,元件尺寸不斷小型化,閘極的線寬以及閘介電層的厚度逐漸縮小或變薄。氧化矽是最為常見的一種閘介電層。然而,氧化矽層之中的孔隙(pin hole)容易造成各種的電性問題,例如是直接穿隧電流,因此,氧化矽層難以做成薄介電層。目前,已揭露一種將氮植入氧化矽而使其氮化形成氮氧化矽的作法,以降低漏電流,改進製程的可靠度。然而,此種方式在進行氮化製程時,易衍生出氮原子容易擴散到矽基底以及氧化矽層之間的界面等問題,而影響元件的效能以及可靠度。With the development of the ultra-large integrated circuit industry, the component size has been continuously miniaturized, and the gate width and the thickness of the gate dielectric layer have been gradually reduced or thinned. Cerium oxide is the most common type of gate dielectric. However, the pin holes in the ruthenium oxide layer are liable to cause various electrical problems such as direct tunneling current, and therefore, it is difficult to form a thin dielectric layer. At present, a method of implanting nitrogen into yttrium oxide and nitriding it to form bismuth oxynitride has been disclosed to reduce leakage current and improve process reliability. However, in such a manner, when the nitridation process is performed, problems such as easy diffusion of nitrogen atoms to the interface between the ruthenium substrate and the ruthenium oxide layer are easily derived, which affects the efficiency and reliability of the device.
本發明提供一種半導體製程方法,可以使得所形成的氮氧化矽層具有足夠的氮濃度,具有較高的介電常數k值,以提升其電性表現。The invention provides a semiconductor manufacturing method, which can make the formed yttria layer have a sufficient nitrogen concentration and a high dielectric constant k value to enhance its electrical performance.
本發明提供一種金氧半導體元件的製造方法,其所形成的氮氧化矽層具有足夠的氮濃度,具有較高的介電常數k值,可以使得金氧半導體元件具有良好的效能。The invention provides a method for manufacturing a gold-oxygen semiconductor device, wherein the formed yttria layer has a sufficient nitrogen concentration and has a high dielectric constant k value, so that the MOS device can have good performance.
本發明提出一種半導體製程方法,包括形成氧化矽層,之後進行至少兩步驟之氮化製程,使上述氧化矽層氮化形成一氮氧化矽層。氮化製程依序包括第一氮化步驟與第二氮化步驟,且施行上述第一氮化步驟與施行上述第二氮化步驟之參數至少有一者不同。The present invention provides a semiconductor processing method comprising forming a ruthenium oxide layer, followed by at least two steps of nitriding, and nitriding the ruthenium oxide layer to form a ruthenium oxynitride layer. The nitridation process sequentially includes a first nitridation step and a second nitridation step, and at least one of the parameters of performing the first nitridation step and the performing the second nitridation step is different.
依照本發明一實施例所述,上述第一氮化步驟與上述第二氮化步驟分別包括去耦合電漿氮化製程、遠端電漿氮化製程或氨氣熱氮化製程。According to an embodiment of the invention, the first nitriding step and the second nitriding step respectively comprise a decoupling plasma nitridation process, a remote plasma nitridation process or an ammonia gas thermal nitridation process.
依照本發明一實施例所述,上述第一氮化步驟與上述第二氮化步驟的功率不同。According to an embodiment of the invention, the first nitriding step is different from the power of the second nitriding step.
依照本發明一實施例所述,上述第一氮化步驟的功率大於上述第二氮化步驟的功率。第二氮化步驟施行的時間較長於上述第一氮化步驟施行的時間。第一氮化步驟的工作週期(duty cycle)大於上述第二氮化步驟的工作週期。According to an embodiment of the invention, the power of the first nitriding step is greater than the power of the second nitriding step. The second nitridation step is performed for a longer period of time than the first nitridation step. The duty cycle of the first nitridation step is greater than the duty cycle of the second nitridation step.
依照本發明一實施例所述,上述第一氮化步驟的功率小於上述第二氮化步驟的功率。第一氮化步驟施行的時間較長於上述第二氮化步驟施行的時間。第二氮化步驟的工作週期大於上述第一氮化步驟的工作週期。According to an embodiment of the invention, the power of the first nitriding step is less than the power of the second nitriding step. The first nitridation step is performed for a longer period of time than the second nitridation step. The duty cycle of the second nitridation step is greater than the duty cycle of the first nitridation step.
依照本發明一實施例所述,上述氧化矽層的形成方法包括臨場蒸氣產生(ISSG)法、化學氣相沉積法或去耦合電漿氧化法。According to an embodiment of the invention, the method for forming the ruthenium oxide layer includes an on-site vapor generation (ISSG) method, a chemical vapor deposition method, or a decoupling plasma oxidation method.
依照本發明一實施例所述,上述半導體製程方法更包括後段回火製程。According to an embodiment of the invention, the semiconductor manufacturing method further includes a post-stage tempering process.
依照本發明一實施例所述,上述後段回火製程依序包括氮氣回火製程與氧氣回火製程。According to an embodiment of the invention, the subsequent tempering process includes a nitrogen tempering process and an oxygen tempering process.
本發明還提出一種金氧半導體元件的製造方法,包括在基底上形成形成氧化矽層,之後進行至少兩步驟之氮化製程,使上述氧化矽層氮化形成氮氧化矽層。氮化製程依序包括第一氮化步驟與第二氮化步驟,且施行第一氮化步驟與施行第二氮化步驟之參數至少有一者不同。之後,在上述氮氧化矽層上形成閘極導體層。The present invention also provides a method of fabricating a MOS device, comprising forming a yttrium oxide layer on a substrate, and then performing a nitridation process of at least two steps to nitride the ruthenium oxide layer to form a ruthenium oxynitride layer. The nitridation process sequentially includes a first nitridation step and a second nitridation step, and at least one of the parameters of performing the first nitridation step and the performing the second nitridation step is different. Thereafter, a gate conductor layer is formed on the above yttria layer.
依照本發明一實施例所述,上述第一氮化步驟與上述第二氮化步驟分別包括去耦合電漿氮化製程、遠端電漿氮化製程或氨氣熱氮化製程。According to an embodiment of the invention, the first nitriding step and the second nitriding step respectively comprise a decoupling plasma nitridation process, a remote plasma nitridation process or an ammonia gas thermal nitridation process.
依照本發明一實施例所述,上述第一氮化步驟與上述第二氮化步驟的功率不同。According to an embodiment of the invention, the first nitriding step is different from the power of the second nitriding step.
依照本發明一實施例所述,上述第一氮化步驟的功率大於上述第二氮化步驟的功率。第二氮化步驟施行的時間較長於上述第一氮化步驟施行的時間。第一氮化步驟的工作週期大於上述第二氮化步驟的工作週期。According to an embodiment of the invention, the power of the first nitriding step is greater than the power of the second nitriding step. The second nitridation step is performed for a longer period of time than the first nitridation step. The duty cycle of the first nitridation step is greater than the duty cycle of the second nitridation step.
依照本發明一實施例所述,上述第一氮化步驟的功率小於上述第二氮化步驟的功率。第一氮化步驟施行的時間較長於上述第二氮化步驟施行的時間。第二氮化步驟的工作週期大於上述第一氮化步驟的工作週期。According to an embodiment of the invention, the power of the first nitriding step is less than the power of the second nitriding step. The first nitridation step is performed for a longer period of time than the second nitridation step. The duty cycle of the second nitridation step is greater than the duty cycle of the first nitridation step.
依照本發明一實施例所述,上述氧化矽層的形成方法包括臨場蒸氣產生(ISSG)法、化學氣相沉積法或去耦合電漿氧化法。According to an embodiment of the invention, the method for forming the ruthenium oxide layer includes an on-site vapor generation (ISSG) method, a chemical vapor deposition method, or a decoupling plasma oxidation method.
依照本發明一實施例所述,上述金氧半導體元件的製造方法,更包括後段回火製程。According to an embodiment of the invention, the method for fabricating the MOS device further includes a post-stage tempering process.
基於上述,本發明之半導體製程方法透過至少兩步驟的氮化製程將氧化矽層氮化,可以使得所形成的氮氧化矽層具有足夠的氮濃度,以提升其電性表現。當此氮氧化矽層應用於金氧半導體元件做為閘介層時,可以使得金氧半導體元件具有良好的效能。Based on the above, the semiconductor process method of the present invention nitrides the hafnium oxide layer through a nitridation process of at least two steps, so that the formed hafnium oxynitride layer has a sufficient nitrogen concentration to enhance its electrical performance. When the ruthenium oxynitride layer is applied to the MOS device as a gate dielectric layer, the MOS device can have good performance.
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1是依照本發明實施例所繪示的半導體製程方法的流程圖。圖2是依照本發明實例所繪示的氮氧化矽層中氮濃度與深度的關係圖。FIG. 1 is a flow chart of a semiconductor process method according to an embodiment of the invention. 2 is a graph showing the relationship between nitrogen concentration and depth in a ruthenium oxynitride layer according to an example of the present invention.
請參照圖1,本發明之半導體製程方法包括步驟10、20及30。步驟10,在基底上形成氧化矽層。基底的材質可以是半導體,例如是矽,或是半導體化合物,例如是矽化鍺,或是絕緣層上有矽(SOI)。形成氧化矽層的方法包括臨場蒸氣產生(ISSG)法、化學氣相沉積法或去耦合電漿氧化法。氧化矽層的厚度例如是1.68奈米至1.76奈米。氧化矽層的厚度太厚,則其效能會下降;氧化矽層的厚度太薄,則其在後續進行氮化製程時容易有氮穿透的問題。Referring to FIG. 1, the semiconductor manufacturing method of the present invention includes steps 10, 20 and 30. In step 10, a ruthenium oxide layer is formed on the substrate. The material of the substrate may be a semiconductor such as germanium or a semiconductor compound such as germanium germanium or germanium (SOI) on the insulating layer. Methods of forming a ruthenium oxide layer include an on-site vapor generation (ISSG) method, a chemical vapor deposition method, or a decoupled plasma oxidation method. The thickness of the ruthenium oxide layer is, for example, from 1.68 nm to 1.76 nm. If the thickness of the yttrium oxide layer is too thick, the efficiency thereof will decrease; if the thickness of the yttrium oxide layer is too thin, it will easily have a problem of nitrogen penetration during the subsequent nitriding process.
請參照圖1,步驟20,進行至少兩步驟之氮化製程,使上述氧化矽層氮化。所形成的氮氧化矽層中,氮的原子含量為20%至25%。步驟20之氮化製程依序包括第一氮化步驟22與第二氮化步驟24,且施行第一氮化步驟22與施行第二氮化步驟24之參數至少有一者不同。前述不同的參數例如是功率、時間、工作週期(duty cycle)、腔體壓力及/或氮氣流量。氮化製程例如是去耦合電漿氮化製程、遠端電漿氮化製程或是氨氣熱氮化製程。去耦合電漿氮化製程包括腔體去耦合電漿氮化製程、遠端去耦合電漿氮化製程或氨氣熱去耦合電漿氮化製程。Referring to FIG. 1, step 20, a nitridation process of at least two steps is performed to nitride the ruthenium oxide layer. In the formed ruthenium oxynitride layer, the atomic content of nitrogen is 20% to 25%. The nitridation process of step 20 includes a first nitridation step 22 and a second nitridation step 24, respectively, and at least one of the parameters of performing the first nitridation step 22 and the performing the second nitridation step 24 is different. The aforementioned different parameters are, for example, power, time, duty cycle, cavity pressure and/or nitrogen flow. The nitridation process is, for example, a decoupled plasma nitridation process, a remote plasma nitridation process, or an ammonia gas thermal nitridation process. The decoupling plasma nitridation process includes a cavity decoupling plasma nitridation process, a remote decoupling plasma nitridation process, or an ammonia gas thermal decoupling plasma nitridation process.
請參照圖1,在一實施例中,上述第一氮化步驟22與第二氮化步驟24分別包括去耦合電漿氮化製程,第一氮化步驟22與第二氮化步驟24所使用的功率、時間或工作週期不同。更具體地說,第一氮化步驟22的功率大於第二氮化步驟24的功率;第二氮化步驟24施行的時間較長於第一氮化步驟22施行的時間;第一氮化步驟22的工作週期大於第二氮化步驟24的工作週期。更詳言之,上述第一氮化步驟22的壓力例如是200毫托,功率例如是2200瓦特,工作週期例如是大於20%,時間例如是30秒。第二氮化步驟24的壓力例如是200毫托,功率例如是2000瓦特,工作週期例如是20%,時間例如是60秒。Referring to FIG. 1, in an embodiment, the first nitridation step 22 and the second nitridation step 24 respectively include a decoupling plasma nitridation process, and the first nitridation step 22 and the second nitridation step 24 are used. The power, time or duty cycle is different. More specifically, the power of the first nitridation step 22 is greater than the power of the second nitridation step 24; the second nitridation step 24 is performed for a longer time than the first nitridation step 22; the first nitridation step 22 The duty cycle is greater than the duty cycle of the second nitridation step 24. More specifically, the pressure of the first nitridation step 22 is, for example, 200 mTorr, the power is, for example, 2,200 watts, the duty cycle is, for example, greater than 20%, and the time is, for example, 30 seconds. The pressure of the second nitridation step 24 is, for example, 200 mTorr, the power is, for example, 2000 watts, the duty cycle is, for example, 20%, and the time is, for example, 60 seconds.
除了兩步驟氮化外,可採用更多步驟之氮化處理。In addition to the two-step nitridation, more steps of nitriding can be employed.
從圖2繪示的氮氧化矽層中氮濃度與深度的關係圖來看,上述第一氮化步驟22使用較大的能量,其氮原子的濃度輪廓為曲線26所示,其峰在較遠離氧化矽上表面之處,且由於其施行氮化處理的時間較短,因此可以避免或減緩氮穿透氧化矽層的問題。第二氮化步驟24使用能量較小時間較長的氮化處理,可在接近氧化矽的上表面提供較足夠的氮原子,其氮原子濃度輪廓為曲線28所示。第一氮化步驟22與第二氮化步驟24結合後的曲線如曲線29所示。From the relationship between the nitrogen concentration and the depth in the yttrium oxynitride layer shown in FIG. 2, the first nitridation step 22 uses a larger energy, and the concentration profile of the nitrogen atom is as shown by the curve 26, and the peak is It is far from the upper surface of the cerium oxide, and because of the short time of nitriding treatment, the problem of nitrogen penetrating the cerium oxide layer can be avoided or slowed down. The second nitridation step 24 uses a nitriding treatment with a lower energy for a longer period of time to provide a more sufficient nitrogen atom near the upper surface of the cerium oxide, the nitrogen atom concentration profile of which is shown by curve 28. The curve after the combination of the first nitridation step 22 and the second nitridation step 24 is as shown by the curve 29.
在另一實施中,上述第一氮化步驟22與第二氮化步驟24分別包括去耦合電漿氮化製程,第一氮化步驟22的功率小於第二氮化步驟24的功率;第二氮化步驟24施行的時間較短於第一氮化步驟22施行的時間;第一氮化步驟22的工作週期小於第二氮化步驟24的工作週期。詳言之,上述第一氮化步驟22的壓力例如是200毫托,功率例如是2000瓦特,工作週期例如是20%,時間例如是60秒。第二氮化步驟24的壓力例如是200毫托,功率例如是2200瓦特,工作週期例如是大於20%,時間例如是30秒。In another implementation, the first nitridation step 22 and the second nitridation step 24 respectively include a decoupling plasma nitridation process, the power of the first nitridation step 22 is less than the power of the second nitridation step 24; The nitridation step 24 is performed for a shorter period of time than the first nitridation step 22; the duty cycle of the first nitridation step 22 is less than the duty cycle of the second nitridation step 24. In detail, the pressure of the first nitridation step 22 is, for example, 200 mTorr, the power is, for example, 2000 watts, the duty cycle is, for example, 20%, and the time is, for example, 60 seconds. The pressure of the second nitridation step 24 is, for example, 200 mTorr, the power is, for example, 2200 watts, the duty cycle is, for example, greater than 20%, and the time is, for example, 30 seconds.
從圖2繪示的氮氧化矽層中氮濃度與深度的關係圖來看,第一氮化步驟22使用能量較小時間較長的氮化處理,可以在接近氧化矽的上表面提供較足夠的氮原子,其氮原子的濃度輪廓為曲線28所示。第二氮化步驟24使用較大能量,其氮原子的濃度輪廓在較遠離氧化矽上表面之處,如曲線26所示,由於其施行氮化處理的時間較短,因此可以避免或減緩氮穿透氧化矽層的問題。第一氮化步驟22與第二氮化步驟24結合之後的曲線如曲線29所示。From the relationship between the nitrogen concentration and the depth in the yttrium oxynitride layer shown in FIG. 2, the first nitridation step 22 uses a nitriding treatment with a smaller energy for a longer period of time, which can provide sufficient surface near the yttrium oxide. The nitrogen atom and its nitrogen atom concentration profile are shown by curve 28. The second nitridation step 24 uses a larger energy whose concentration profile of nitrogen atoms is farther from the upper surface of the yttrium oxide, as shown by curve 26, which avoids or slows down nitrogen due to the shorter time it takes to perform the nitridation treatment. The problem of penetrating the ruthenium oxide layer. The curve after the combination of the first nitridation step 22 and the second nitridation step 24 is as shown by curve 29.
步驟30,進行後段回火製程。上述後段回火製程依序包括氮氣回火製程與氧氣回火製程。氮氣回火製程例如是快速熱回火製程、紫外光退火製程或雷射回火製程。氧氣回火製程例如是快速熱回火製程、紫外光退火製程或雷射回火製程。在一實施例中,氮氣回火製程例如是快速熱回火製程,回火的溫度例如是攝氏800度,回火的時間例如是10~120秒;氧氣回火製程例如是快速熱回火製程,回火的溫度例如是攝氏600度,回火時間例如是10~120秒。In step 30, a post-stage tempering process is performed. The above-mentioned post-stage tempering process sequentially includes a nitrogen tempering process and an oxygen tempering process. The nitrogen tempering process is, for example, a rapid thermal tempering process, an ultraviolet annealing process, or a laser tempering process. The oxygen tempering process is, for example, a rapid thermal tempering process, an ultraviolet annealing process, or a laser tempering process. In an embodiment, the nitrogen tempering process is, for example, a rapid thermal tempering process, the tempering temperature is, for example, 800 degrees Celsius, and the tempering time is, for example, 10 to 120 seconds; and the oxygen tempering process is, for example, a rapid thermal tempering process. The tempering temperature is, for example, 600 degrees Celsius, and the tempering time is, for example, 10 to 120 seconds.
圖3是依照本發明實施例所繪示的金氧半導體元件的製造方法的流程圖。圖4A至圖4B是依照本發明實施例所繪示的金氧半導體元件的製造方法的剖面圖。3 is a flow chart of a method of fabricating a MOS device in accordance with an embodiment of the invention. 4A-4B are cross-sectional views showing a method of fabricating a MOS device in accordance with an embodiment of the present invention.
請參照圖3與4A,本發明之金氧半導體元件的製造方法包括步驟110、步驟120、步驟130、步驟140及步驟150。步驟110、120、122、124及130分別如上述步驟10、20、22、24以及30所述,於基底200上形成氮氧化矽層202,其詳細內容可參照上述實施例所述,不再贅述。Referring to FIGS. 3 and 4A, the method of fabricating the MOS device of the present invention includes steps 110, 120, 130, 140, and 150. Steps 110, 120, 122, 124, and 130 respectively form a ruthenium oxynitride layer 202 on the substrate 200 as described in the above steps 10, 20, 22, 24, and 30, the details of which can be referred to the above embodiments, and no longer Narration.
請參照圖3與圖4A,步驟140,在氮氧化矽層202上沉積導體層204。導體層204的材質包括摻雜多晶矽、金屬或其組合。導體層204的形成方法例如是化學氣相沉積法。在一實施例中,導體層204的材質為摻雜多晶矽,其可以使用矽乙烷做為反應氣體,透過化學氣相沉積製程來形成,所沉積的摻雜多晶矽的厚度例如是400埃至900埃。Referring to FIG. 3 and FIG. 4A, in step 140, a conductor layer 204 is deposited on the yttria layer 202. The material of the conductor layer 204 includes doped polysilicon, metal or a combination thereof. The method of forming the conductor layer 204 is, for example, a chemical vapor deposition method. In one embodiment, the conductor layer 204 is made of doped polysilicon, which can be formed by using a CVD ethane as a reactive gas through a chemical vapor deposition process, and the thickness of the deposited doped polysilicon is, for example, 400 Å to 900 Å. Ai.
請參照圖3與4B,步驟150,將上述導體層204及氮氧化矽層202圖案化,以形成圖案化的導體層204a與圖案化的氮氧化矽層202a。將上述導體層204及氮氧化矽層202圖案化的方法例如是微影與蝕刻法。圖案化導體層204a作為閘極導體層,圖案化氮氧化矽層202a作為閘介電層。Referring to FIGS. 3 and 4B, in step 150, the conductor layer 204 and the yttria layer 202 are patterned to form a patterned conductor layer 204a and a patterned yttria layer 202a. The method of patterning the conductor layer 204 and the argon oxynitride layer 202 is, for example, a lithography and etching method. The patterned conductor layer 204a serves as a gate conductor layer, and the patterned yttria layer 202a serves as a gate dielectric layer.
基於上述,本發明之半導體製程方法透過至少兩步驟之氮化製程將氧化矽層氮化,可以使得所形成的氮氧化矽層具有足夠的氮濃度,以增加其介電常數k值,提升其電性表現。當此氮氧化矽層應用於金氧半導體元件做為閘介層時,可以使得金氧半導體元件具有良好的效能。Based on the above, the semiconductor process method of the present invention nitrides the hafnium oxide layer through a nitridation process of at least two steps, so that the formed hafnium oxynitride layer has a sufficient nitrogen concentration to increase its dielectric constant k value and enhance its Electrical performance. When the ruthenium oxynitride layer is applied to the MOS device as a gate dielectric layer, the MOS device can have good performance.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10、20、22、24、30、110、120、122、124、130、140...步驟10, 20, 22, 24, 30, 110, 120, 122, 124, 130, 140. . . step
200...基底200. . . Base
202...氮氧化矽層202. . . Niobium oxynitride layer
202a...圖案化的氮氧化矽層202a. . . Patterned yttria layer
204...導體層204. . . Conductor layer
204a...圖案化的導體層204a. . . Patterned conductor layer
圖1是依照本發明實施例所繪示的半導體製程方法的流程圖。FIG. 1 is a flow chart of a semiconductor process method according to an embodiment of the invention.
圖2是依照本發明實例所繪示的氮氧化矽層中氮濃度與深度的關係圖。2 is a graph showing the relationship between nitrogen concentration and depth in a ruthenium oxynitride layer according to an example of the present invention.
圖3是依照本發明實施例所繪示的金氧半導體元件的製造方法的流程圖。3 is a flow chart of a method of fabricating a MOS device in accordance with an embodiment of the invention.
圖4A至圖4B是依照本發明實施例所繪示的金氧半導體元件的製造方法的剖面圖。4A-4B are cross-sectional views showing a method of fabricating a MOS device in accordance with an embodiment of the present invention.
10、20、22、24、30...步驟10, 20, 22, 24, 30. . . step
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100135037A TWI515801B (en) | 2011-09-28 | 2011-09-28 | Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100135037A TWI515801B (en) | 2011-09-28 | 2011-09-28 | Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201314789A TW201314789A (en) | 2013-04-01 |
| TWI515801B true TWI515801B (en) | 2016-01-01 |
Family
ID=48802614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100135037A TWI515801B (en) | 2011-09-28 | 2011-09-28 | Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI515801B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10541128B2 (en) | 2016-08-19 | 2020-01-21 | International Business Machines Corporation | Method for making VFET devices with ILD protection |
-
2011
- 2011-09-28 TW TW100135037A patent/TWI515801B/en active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10541128B2 (en) | 2016-08-19 | 2020-01-21 | International Business Machines Corporation | Method for making VFET devices with ILD protection |
| US11164959B2 (en) | 2016-08-19 | 2021-11-02 | International Business Machines Corporation | VFET devices with ILD protection |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201314789A (en) | 2013-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104347418B (en) | The forming method of MOS transistor | |
| CN100517716C (en) | Semiconductor device and method for manufacturing the same | |
| CN101425457B (en) | Method for forming high dielectric constant gate dielectric material and semiconductor element | |
| TW201238057A (en) | Plasma treatment of silicon nitride and silicon oxynitride | |
| CN102142369A (en) | Method for improving performance of SiC (Semiconductor Integrated Circuit) device | |
| US20120329285A1 (en) | Gate dielectric layer forming method | |
| CN102687246B (en) | Maintain the integrity of the high-K gate stack by passivation using oxygen plasma | |
| CN111370306B (en) | Manufacturing method of transistor and full-surrounding grid electrode device structure | |
| KR20050002041A (en) | Method for fabricating gate-electrode of semiconductor device using hardmask | |
| CN104103509A (en) | Formation method of interfacial layer and formation method of metal gate transistor | |
| KR20070112783A (en) | Manufacturing Method of Nitride Gate Dielectric | |
| CN101364540B (en) | Manufacturing method of semiconductor device | |
| CN111681961A (en) | Manufacturing method of semiconductor device | |
| JP5387173B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI515801B (en) | Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device | |
| US8741784B2 (en) | Process for fabricating semiconductor device and method of fabricating metal oxide semiconductor device | |
| KR100729354B1 (en) | Manufacturing Method of Semiconductor Device for Improving Electrical Properties of Dielectric Film | |
| CN103794482B (en) | The forming method of metal gates | |
| KR100788361B1 (en) | Formation method of MOSFET device | |
| CN104347393A (en) | Method for removing natural oxidation layer at bottom of contact window | |
| CN103489770A (en) | Grid oxide layer growth method and CMOS tube manufacturing method | |
| CN103943479A (en) | Preparation method for gate oxide | |
| US8691636B2 (en) | Method for removing germanium suboxide | |
| KR100609542B1 (en) | Method for manufacturing a gate electrode of a semiconductor device using an aluminum nitride film as a gate insulating film | |
| JP2004006455A (en) | Semiconductor device and method of manufacturing the same |