TWI515866B - Through silicon via repair circuit of semiconductor device - Google Patents

Description

Straight-through twinned repair circuit for semiconductor devices

The present invention relates to a through silicon via (TSV) repair circuit for a semiconductor device suitable for wafer stacking technology.

With the development of semiconductor process technology, the area of integrated circuits (ICs) is shrinking and the number of transistors in ICs is increasing, resulting in an increase in the area of use of chips, and delay time and power of signals. Power consumption is also more serious. In order to improve problems such as severe delay and power consumption, Three Dimension IC (3DIC) stacking technology is an effective and currently actively developed solution. The three-dimensional wafer stacking technology allows multiple wafers to be vertically stacked in a three-dimensional space to achieve the best efficiency in size reduction, and different wafers are transferred between through wafers through a Through Silicon Via (TSV) structure. Signals, so the interconnect delay length between transistors is significantly shorter than that of conventional flat-area circuits, while improving chip performance and reducing power consumption.

Since the integrated circuits of the plurality of layers must be accurately overlapped when the wafer is pushed, a small offset (offset) will cause the through-silicon vias to fail between the wafer and the wafer. In addition, in order to effectively utilize the wafer area, the smaller the size of the through-silicone via is, the better, but in the fabrication of the through-silicon via, the sidewall insulating layer (for example, SiO ₂ ) is liable to be damaged or foreign. The intrusion of (impurity) causes a short circuit between the through-silicone via and the substrate, or an open defect occurs when the TSVs of the layers are connected in a stacked package. Therefore, in the prior art, the second is often utilized. A straight TSV pair of straight through-twisted perforations is used for signal transmission. If the through-twisting perforation is defective for one of the through-twisted perforations, another pass-through twin-hole perforation can be used to transmit the signal, thereby repairing the defective through-twisted perforation, but there is leakage current. (leakage current) flows through the defective through-silicone vias to the substrate, causing the overall substrate voltage level to drift and be unstable, and the signal will be transmitted incorrectly.

In summary, how to self-detect defects in the through-silicone perforation and repair the transmission signal is an important issue in the field of three-dimensional wafers.

In view of the above, the present disclosure provides a through-silicon via (TSV) repair circuit suitable for a semiconductor device, which can automatically detect whether a TSV is defective and record a defective TSV by using a memory device to prevent leakage current from passing through a defective TSV. Flow to the substrate and save power and self-repair signals by turning off the power of the defective TSV to allow the 3D chip to function properly.

An embodiment of the present disclosure provides a through-silicon via repair circuit for a semiconductor device, including: a first wafer and a second wafer, the first wafer and the second wafer being stacked one on another; at least two through-twisted perforations, Passing through the substrate of the first wafer to transfer data between the first wafer and the second wafer; at least two data path circuits disposed on the first wafer and respectively connected to the at least two through-twisted perforations One of the corresponding straight through crystal perforations, each The at least two data path circuits include: an input driving circuit, converting a signal input by the first signal input terminal according to a power supply voltage and a ground voltage, and transmitting the signal to the first end of the corresponding through-silicone perforation; a 穿孔 穿孔 侦测 侦测 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔The control end is coupled to a second signal input end, and receives and stores the through-pass perforation state from the through-silicone perforation detection circuit; a protection circuit coupled to the memory device and the corresponding through-pass perforation Determining, according to the through-silicon via state stored by the memory device, whether to pull the first end of the corresponding through-silicon via to the ground voltage; and a power control circuit coupled to the Between the power supply voltage and the input driving circuit, the power supply voltage is supplied to the input driving circuit and coupled to the memory device; and an output logic circuit is disposed in the first At least two input terminals of the wafer, the output of the logic circuit respectively coupled to the at least two perforations through a second end of the silicon, and generates an output signal according to the at least two signal input.

Another embodiment of the present disclosure provides a through-silicon via repair circuit for a semiconductor device, comprising: a plurality of wafers stacked on top of each other, each of the wafers including at least two of the substrates penetrating each of the wafers Passing through the twinned vias, and the at least two through-twisted vias of each of the wafers are directly or indirectly connected to one of the at least two through-twisted vias of the wafer adjacent to each wafer, respectively. At least one first chip of the chips includes at least two data path circuits, and at least one of the second chips includes an output logic circuit, and the at least two data path circuits of the at least one first chip are respectively connected to the The at least two through-twisting of at least one first wafer One of the corresponding through-hole twinning holes, each data path circuit includes: an input driving circuit, converting a signal input by the first signal input terminal according to a power supply voltage and a ground voltage, and transmitting the signal to the corresponding through-pass twin a first end of the perforation; a through-hole perforation detecting circuit coupled to the first signal input end and the first end of the corresponding through-twist perforation, and detecting the through-through of the corresponding through-pass perforation a memory device, the control end of which is coupled to a second signal input terminal, receives and stores the through-silicon via state from the through-silicon via detection circuit; and a protection circuit coupled to the memory device And determining, by the first end of the corresponding through-silicon via, whether the first end of the corresponding through-silicon via is pulled to the ground voltage according to the through-silicon via state saved by the memory device; and a power control circuit coupled between the power supply voltage and the input driving circuit, providing the power supply voltage to the input driving circuit, and coupled to the memory device; wherein the At least two input ends of the output logic circuit of a second chip are respectively coupled to the second ends of the at least two through-silicon vias of the upper-level wafer of the at least one second wafer, and according to the at least two The signal at the input produces an output signal.

A further embodiment provides a through-silicon via repair circuit for a semiconductor device, comprising: a plurality of wafers stacked on top of each other, each wafer of the wafers including at least two substrates penetrating each wafer The at least one first chip of the wafers includes at least two data path circuits, and at least one of the second chips includes an output logic circuit and at least two data path circuits, the at least one first chip The at least two data path circuits are respectively connected to one of the at least two through-silicon vias of the at least one first wafer, wherein the corresponding one of the at least one second wafer The two data path circuits are respectively connected to one of the at least two through-silicon vias of the at least one second wafer, wherein each of the data path circuits comprises: an input driving circuit, according to a power supply voltage a ground voltage is converted to a signal input by the first signal input end and transmitted to the first end of the corresponding through-silicon via; the through-hole via detection circuit is coupled to the first signal input end and the corresponding The first end of the through-twisting through hole is configured to detect a through-through perforated state of the corresponding through-twisted through hole; and a memory device, the control end of which is coupled to a second signal input end, and the through hole is perforated from the through hole The detecting circuit receives and stores the through-silicon via state; a protection circuit coupled to the memory device and the first end of the corresponding through-silicon via; the through-silicon via state saved by the memory device Determining whether to pull the first end of the corresponding through-silicon via to the ground voltage; and a power control circuit coupled to the power supply voltage and the input driving circuit Providing the power supply voltage to the input driving circuit and coupled to the memory device; wherein at least two input ends of the output logic circuit of the at least one second chip are respectively coupled to the at least one second chip a second end of the at least two through-silicon vias of the upper-level wafer, and generating an output signal according to the signals of the at least two input ends, the output signal of the output logic circuit of the at least one second chip being coupled to the at least The first signal input terminal of the at least two data path circuits of a second chip.

100, 500, 600, 700‧‧‧ straight through crystal repairing circuit

110, 110A, 110B‧‧‧ substrate

121, 121-1, 121-2, 121-m, 122, 122-1, 122-2, 122-n, 12p-1, 12p-2, 122-q, 221, 222, 321, 322‧‧‧TSV

131, 132, 13p, 231, 232, 331, 332‧‧‧ data path circuit

140, 240, 340‧‧‧ output logic circuits

200, 300‧‧‧ power control circuit

210, 310‧‧‧ input drive circuit

220, 320‧‧‧TSV detection circuit

230, 330‧‧‧ memory devices

250, 350‧‧‧protection circuit

A, A1, A2, B, B1, B2, C, D, E, E1, E2‧‧‧ nodes

CHIP1, CHIP2, CHIP3‧‧‧ wafer

N1, N2, N3, ..., N6‧‧‧ NMOS transistors

NR1, NR2, NR3‧‧‧ reverse or gate

OUT, OUT1, OUT2‧‧‧ output signals

P1, P2, P3, P4‧‧‧ PMOS transistors

VDD‧‧‧Power supply voltage

Vin1, Vin2‧‧‧ signal

FIG. 1 is a schematic diagram of a through-silicon via repair circuit of a semiconductor device according to an embodiment of the present disclosure.

Figure 2 is a block diagram of the through-silicone perforation repair circuit of Figure 1. one.

Figure 3 is one of the circuit diagrams of the data path circuit of Figure 1.

Figure 4 is one of the circuit diagrams of the through-silicone via repair circuit of Figure 1.

FIG. 5 is a schematic diagram of a through-silicon via repair circuit of a semiconductor device according to an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a through-silicon via repair circuit of a semiconductor device according to an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of a through-silicon via repair circuit of a semiconductor device according to an embodiment of the present disclosure.

The following description is an embodiment of the present invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

It is noted that the following disclosure may provide embodiments or examples for practicing various features of the present invention. The specific elements and arrangements of the elements described below are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. In addition, the following description may reuse the same component symbols or characters in various examples. However, the re-use is for the purpose of providing a simplified and clear description, and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. In addition, the description of one of the features described in the following description is connected to, coupled to, and/or formed on another feature, etc., and may include a plurality of different embodiments, including direct contact, or Other additional features are included between the features, etc. such that the features are not in direct contact.

1 is a schematic diagram of a through-silicon via repair circuit 100 of a semiconductor device (eg, a three-dimensional wafer) in accordance with an embodiment of the present disclosure. The through-silicone via repair circuit 100 includes two wafers CHIP1 and CHIP2 stacked on top of each other. The wafer CHIP1 includes a substrate 110, m through-twisted vias 121-1~121-m, and n through-twisted vias 122-1~122. -n, data path circuits 131 and 132 and signal terminals Vin1 and Vin2, wherein the data path circuit 131 is connected to the through-silicon vias 121-1~121-m, and the data path circuit 132 is connected to the through-silicon vias 122-1~122 -n, the through-silicon vias 121-1~121-m and 122-1~122-n penetrate the substrate 110 to transfer signals from the chip CHIP1 to the wafer CHIP2, where m and n are positive integers. The chip CHIP2 includes an output logic circuit 140 and an output signal terminal OUT, wherein the output logic circuit 140 is connected to the through-silicon vias 121-1~121-m and 122-1~122-n. For the sake of simplicity of the drawing, the internal structure of the portion of the wafer CHIP2 is omitted in FIG.

As shown in FIG. 1, this embodiment mainly includes two sets of data paths, the first set of data paths corresponding to the data path circuit 131 and the through-twisted perforations 121-1~121-m, and the second set of data paths corresponding to The data path circuit 132 and the through-silicon vias 122-1 to 122-n. The two sets of data paths receive the input signal through the signal terminal Vin1 and transmit the input signal to the chip CHIP2 through the through-silicone vias 121-1~121-m and 122-1~122-n through at least the through-silicon via, the chip CHIP2 The output logic circuit receives the signals transmitted by the through-silicon vias 121-1~121-m and 122-1~122-n and outputs the output signals through the output signal terminal OUT. However, it should be noted that the disclosure is not limited to two sets of data paths. Those of ordinary skill in the art can apply to three or more sets of data paths in accordance with embodiments of the present disclosure.

It should be noted that the embodiment of FIG. 1 only discloses two wafers CHIP1 and CHIP2 stacked on top of each other, but is not limited thereto. For example, the embodiment can be further applied to each other by at least three wafers. Stacked three-dimensional wafers, wherein any two wafers for transmitting signals to each other are used as the wafers CHIP1 and CHIP2, and at least one other wafer may be included between the wafers CHIP1 and CHIP2, or stacked on top of each other by at least three wafers The formed three-dimensional wafer may include one wafer CHIP1 and at least two second wafers CHIP2. In addition, in the example where at least one other wafer is included between the wafers CHIP1 and CHIP2, the through-silicon vias in the two sets of data paths penetrate the substrate of the multilayer wafer to pass signals to the wafer CHIP2.

FIG. 2 is one of the specific block diagrams of the through-silicon via repair circuit 100 of FIG. As shown in FIG. 2, the data path circuit 131 includes a power supply control circuit 200, an input drive circuit 210, a TSV detection circuit 220, a memory device 230, and a protection circuit 250. The power control circuit 200 is coupled to the power supply voltage VDD and supplies the power to the input drive circuit 210. The input driving circuit 210 is coupled to the signal terminal Vin1 and the first end of the through-silicon vias 121-1~121-m, and converts the signal input by the signal terminal Vin1 according to the power supply voltage VDD and the ground voltage to the through-silicon via 121. The first end of -1~121-m. The TSV detection circuit 220 is coupled to the signal terminal Vin1, the first end of the through-silicon via 121-1~121-m, and the memory device 230. The TSV detection circuit 220 detects the detected driving signal according to the signal terminal Vin1. The TSV state of the through-holes 121-1~121-m is passed through, and the detected TSV state is transmitted to the memory device 230. The output of the memory device 230 is coupled to the power The source control circuit 200 and the protection circuit 250 are coupled to the output end of the TSV detection circuit 220. The control terminal of the memory device 230 is coupled to a second signal input terminal Vin2, and controls the voltage state according to Vin2 to start receiving and saving. TSV status. The protection circuit 250 is coupled to the first end of the through-silicon vias 121-1~121-m for determining whether the first pass through the vias 121-1~121-m is determined according to the TSV state held by the memory device 230. Pull the terminal to ground voltage. The power supply control circuit 200 also determines whether to stop supplying the power supply voltage VDD to the input drive circuit 210 based on the TSV state held by the memory device 230. Since the internal configuration of the data path circuit 132 is the same as that of the data path circuit 131, the internal configuration of the data path circuit 132 is omitted in FIG.

The operation of the through-silicone repair circuit 100 is divided into two parts, one is a self-detection operation for detecting the TSV state, and the other is a data transfer operation after the self-detection operation for transferring data from the chip. CHIP1 is transferred to CHIP2. During the self-detection operation of the through-silicone via repair circuit 100, first, the input driving circuit 210 and the TSV detecting circuit 220 receive the detection driving signal through the signal terminal Vin1, and the memory device 230 receives the memory trigger signal through the signal terminal Vin2. Save the TSV status. The input driving circuit 210 converts the detected driving signal according to the power supply voltage VDD and the ground voltage to the first end of the driving through-silicon vias 121-1~121-m, and the TSV detecting circuit 220 detects the driving signal according to the detection. The TSV state of the through-hole perforation 121-1~121-m is passed through, and the triggered memory device 230 stores the TSV state. According to the detection result of the TSV detection circuit 220, if the through-silicone vias 121-1~121-m have all the through-silicon vias without defects, the TSV state of the first data path is normal (the first data path) The data can be transferred normally, and the memory device 230 saves the TSV status as positive. The power control circuit 200 continuously supplies the power supply voltage to the input driving circuit 210 according to the normal TSV state stored in the memory device 230. The protection circuit 250 does not pass the through-silicon via 121-1 according to the normal TSV state held by the memory device 230. The first end of ~121-m is pulled to the ground voltage. According to the detection result of the TSV detection circuit 220, if at least one of the through-twisting vias 121-1~121-m is defective, the TSV state of the first group of data paths is abnormal (the first group of data) If the path cannot transmit the data normally, the memory device 230 saves the TSV state as abnormal, and the power control circuit 200 stops supplying the power voltage to the input driving circuit 210 according to the abnormal TSV state saved by the memory device 230, and the protection circuit 250 according to the memory. The abnormal TSV state held by device 230 pulls the first end of the through-silicon vias 121-1~121-m to ground.

Fig. 3 is one of the circuit diagrams of the data path circuit 131 of Fig. 1. It should be noted that for the sake of simplicity of the illustration, only the through-twisting perforations 121-1 are retained in FIG. 3 and other through-twisted perforations are omitted. The power control circuit 200 includes a P-type Metal-Oxide-Semiconductor (PMOS) transistor P1, and the input driving circuit 210 includes a PMOS transistor P2 and an N-type metal-Oxide- Semiconductor, NMOS) Inverter composed of transistor N2, TSV detection circuit 220 includes a NOR gate NR1, and memory device 230 includes NMOS transistor N3, which is connected by two inverters. And by an inverting buffer, the protection circuit 250 includes an NMOS transistor N1. The source terminal of the PMOS transistor P1 is coupled to the power supply voltage VDD, and the PMOS transistor P1 is coupled to the source terminal of the PMOS transistor P2. The gate terminal of the PMOS transistor P1 is coupled to the output terminal of the memory device 230 and the NMOS. The gate terminal of transistor N1. Gate terminal of PMOS transistor P2 and gate of NMOS transistor N2 The terminal is coupled to the signal terminal Vin1, the source terminal of the PMOS transistor P2 is coupled to the 汲 terminal of the PMOS transistor P1, and the source terminal of the NMOS transistor N2 is coupled to the ground voltage, the 汲 terminal of the MOS transistor P2 and the NMOS battery The 汲 terminal of the crystal N2 is coupled to the first end of the through-silicon via 121-1. The first input end of the reverse gate NR1 is coupled to the first end of the through-silicon via 121-1, the second input of the reverse gate NR1 is coupled to the signal terminal Vin1, and the output of the reverse gate NR1 is coupled to The NMOS terminal of the NMOS transistor N3 is coupled to the input terminal of the keeper. The gate terminal of the NMOS transistor N3 is coupled to the signal terminal Vin2, and the output terminal of the keeper is coupled to the inverter buffer. The input end of the reverse buffer is coupled to the gate terminal of the PMOS transistor P1 and the gate terminal of the NMOS transistor N1, and the NMOS terminal of the NMOS transistor N1 is coupled to the first of the through-silicon via 121-1. The source terminal of the NMOS transistor N1 is coupled to a ground voltage.

The self-detection operation of the through-silicone via repair circuit 100 will be described below with reference to FIG. During the self-detection operation, first, the signal terminal Vin1 inputs a logic "0" detection driving signal and the signal terminal Vin2 inputs a logic "1" memory trigger signal. In the case where the through-silicone via 121-1 is normal: the inverter of the input driving circuit 210 converts the detection driving signal of the logic "0" into a logic "1" and transmits it to the through-silicone via 121-1. At one end, that is, node A, the inverse gate NR1 of the TSV detection circuit 220 receives a logic "1" from the node A and a logic "0" from the signal terminal Vin1, so the inverse gate NR1 outputs a logic "0" to the memory device. 230. Since the memory device 230 has been triggered by the memory trigger signal of the logic "1" input by the signal terminal Vin2, the memory device 230 can record and save the logic "0" output by the inverse gate NR1. The memory device 230 outputs a logic "0" to the gate terminal of the NMOS transistor N1 of the protection device 250 to turn off the NMOS transistor N1, and memorize The device 230 outputs a logic "0" to the gate terminal of the PMOS transistor P1 of the power supply control circuit 200 to keep the PMOS transistor P1 conducting.

In the case where the through-silicone via 121-1 is defective (for example, a short-circuit defect), the inverter of the input driving circuit 210 converts the detection driving signal of logic "0" into a logic "1" and transmits it to the through-silicon via. The first end of 121-1, which is node A, is pulled to a logic "0" due to a short-circuit defect in the through-silicone via 121-1. The inverse OR gate NR1 of the TSV detection circuit 220 receives a logic "0" from the node A and a logic "0" from the signal terminal Vin1, so the inverse gate NR1 outputs a logic "1" to the memory device 230. Since the memory device 230 has been triggered by the memory trigger signal of the logic "1" input by the signal terminal Vin2, the memory device 230 can record and save the logic "1" output by the inverse gate NR1. The memory device 230 outputs a logic "1" to the gate terminal of the NMOS transistor N1 of the protection device 250 to turn on the NMOS transistor N1, that is, to turn on the protection device 250, and pull the node A to the ground voltage by the turned-on NMOS transistor N1. The memory device 230 also outputs a logic "1" to the gate terminal of the PMOS transistor P1 of the power supply control circuit 200 to turn off the PMOS transistor P1 to prevent leakage current of the power supply voltage VDD from flowing into the substrate. After the self-detection operation, the signal of the signal terminal Vin2 will become a logic "0" to avoid re-triggering the memory device 230, so that the memory device 230 continues to save the TSV state obtained during the self-detection operation. During the self-detection operation of the through-silicone repair repair circuit 100, the operation of the data path circuit 132 is the same as that of the data path circuit 131, and therefore will not be described again. It should be noted that the self-detection operation is performed before the data transfer operation is performed by the through-pass perforation repair circuit 100, so that the memory devices of the data paths record the TSV status of each data path. It should be noted that the memory device of the present disclosure can be a latch, a D-type flip-flop, and a non-swing. Implementations such as memory are not limited to the implementation shown in the figure.

4 is one of the circuit diagrams of the through-silicon via repair circuit 100 of FIG. 1. The structure of the data path circuit 131 and the data path circuit 132 is the same as that of FIG. 3, and therefore will not be described again, and the output logic circuit 140 includes Reverse or gate NR3. The data transfer operation of the through-silicone via repair circuit 100 after the self-detection operation will be described below with reference to FIG. Table 1 is a signal of the data transfer operation in the state in which the memory devices 230 and 330 have respectively stored the TSVs 121-1 and TSV 122-2 as normal or defective after the "self-detection operation program is completed". The truth table, wherein during the data transfer operation, the signal terminal Vin2 is always logic "0", and the table 2 is the component conduction shutdown table of the data transfer operation of the through-silicone repairing circuit 100 after the self-detection operation:

The TSV1 states in Tables 1 and 2 represent the TSV state of the first data path, that is, the state of the through-pass perforation 121-1 in FIG. 4, and the TSV2 state represents the TSV state of the second data path, that is, the fourth state. The state of the through-twist perforation 122-2 in the figure. Taking the TSV1 state as a defect and the TSV2 state as normal, when the signal terminal Vin1 inputs a logic "0", since the memory device 230 has saved the logic "1" corresponding to the TSV1 state as a defect in the previous self-detection operation. The memory device 330 has saved the logic "0" corresponding to the state of the TSV2 being normal, so the node E1 and the node E2 are respectively logic "1" and logic "0", so the NMOS transistor N1 is turned on, and the node A1 is pulled to the logic " 0", and the PMOS transistor P1 is turned off to prevent the VDD leakage current from flowing to the substrate through the defective through-silicon via 121-1, and since the PMOS transistor P1 is turned off, half of the power consumption can be saved. At the same time, the NMOS transistor N4 is turned off, and the PMOS transistor P3 is turned on, so that the second data path transmits data normally. At this time, the first input signal received by the inverse gate NR3 of the output logic circuit 140 from the first data path is logic "0", and the second input signal received from the second data path is logic "1", so the output logic circuit The output OUT of the 140 output logic "0", and the logic "0" signal of the Vin1 signal terminal is correctly outputted, and the TSV transmission signal repair (repair) function is achieved.

As shown in Table 1, except that the TSV1 state and the TSV2 state are both defective and the signal terminal Vin1 inputs a logic "0", the signal of the output terminal OUT and the signal terminal Vin1 is inconsistent, and in other cases, the signal of the output terminal OUT and the signal terminal Vin1 is different. All are consistent, that is, the TSV signal is transmitted correctly. In the case that both the TSV1 state and the TSV2 state are defective, at least one set of data paths, such as the three sets of data paths as shown in FIG. 5, may be added to repair the TSV transmission signal. FIG. 5 is a schematic diagram of a through-silicon via repair circuit 500 of a semiconductor device in accordance with an embodiment of the present disclosure. The through-silicone perforation repair circuit 500 is similar to the through-silicone repair circuit 100. The main difference is that the through-silicone repair circuit 500 uses three sets of data paths, but it should be noted that the straight through-silicone repair circuit of the present disclosure is more More than three sets of data paths are used. Therefore, as long as the TSV status of one of the data paths is normal, the output logic circuit coupled to all data paths can be used to repair the signals to output the correct signals.

The direct through-silicone perforation repair circuit of the present disclosure has considerable flexibility in the application of three-dimensional wafer technology. In a plurality of wafers of a three-dimensional wafer, each of the wafers is provided with at least two through-silicon vias, and at least two through-silicon vias of each wafer are directly or indirectly connected to the wafer adjacent to each wafer. At least two through-twisted perforations of which one of the corresponding through-twisted vias, for example, as shown in FIG. 6, the through-silicon vias 221 of the wafer CHIP2 are connected to the through-silicon vias 121 of the wafer CHIP1 and the through-twist of the wafer CHIP3 Pierce 321. And any one of the plurality of wafers may be configured with at least two data path circuits, and any one of the plurality of wafers may be configured with an output logic circuit. The application of the through-silicone perforation repair circuit in multilayer wafer stacking will be described below with reference to FIGS. 6 and 7. It should be noted that the parts in Figures 6 and 7 The sub-operation is similar to the above, and therefore will not be repeated.

FIG. 6 is a schematic diagram of a through-silicon via repair circuit 600 of a semiconductor device in accordance with an embodiment of the present disclosure. The through-silicone via repair circuit 600 includes a plurality of wafers, such as wafers CHIP1, CHIP2, and CHIP3, which are stacked one on top of the other. The data path circuits 131 and 132 of the through-silicone via repair circuit 600 are not limited to the wafers disposed on the uppermost layer, but may be disposed on other layer wafers. In addition, the output logic circuit may be disposed not only on the wafer CHIP2, but also on any number of wafers such as the wafer CHIP3. A plurality of output signals OUT, OUT1, OUT2, etc. are generated by the output logic circuits 140, 240, 340, etc. on different wafers, so that the input signals input through the signal terminal Vin1 can be correctly transmitted to the respective wafers. In the embodiment of FIG. 6, the data path circuit 131 can check the TSV state of the through-silicon vias 121 in series through the vias 221 and the through-silicon vias 321 during the self-detection operation. In the embodiment of FIG. 6, although the data path circuits 131 and 132 are disposed on the wafer CHIP1, the through-silicon vias of the respective wafers may be short-circuited with the respective substrates, so the data path circuits 131 and 132 can detect For example, one of the wafers CHIP2 is short-circuited and repaired by the through-silicon via, thereby preventing leakage current of the power supply voltage from flowing through the substrate of the wafer CHIP2.

FIG. 7 is a schematic diagram of a through-silicon via repair circuit 700 of a semiconductor device in accordance with an embodiment of the present disclosure. As shown in the through-silicone via repair circuit 700, the data path circuit is not limited to being disposed on only one layer of wafer, but may be disposed on any other wafer, and the correct signal is repaired by output logic on different wafers. Transfer to another layer of wafer. Therefore, according to the through-silicon via repair circuit 700 of FIG. 7, only two sets of data configured in a single wafer are provided. The path does not have defects at the same time, so the signal can be correctly transmitted to another layer of the chip. For example, if the TSV states of the through-silicon vias 121, 222, and 321 are normal and the TSV states of the through-silicon vias 122, 221, and 322 are defective, the signal of the signal terminal Vin1 can be correctly transmitted to the output terminal OUT2. If two sets of data paths configured in a single chip have defects at the same time, signal transmission errors can be avoided by adding a third set of data paths or multiple sets of data paths.

An embodiment of the present invention provides a through-silicon via repair circuit for a semiconductor device, comprising a plurality of wafers stacked on top of each other, and each wafer includes at least two through-twisted vias penetrating the substrate of each wafer. The wafers may include at least one first wafer (eg, wafer CHIP1 of FIG. 6 and wafer CHIP1 of FIG. 7), the at least one first wafer including at least two data path circuits, and the output ends of each data path circuit are connected To the first end of the corresponding through-silicon via, the first signal input end of each data path circuit receives the signal to be transmitted from the upper-level chip or the external, and the second signal input end of each data path circuit receives the data path circuit. The trigger control signal of the memory device. The chips may include at least one second wafer (eg, wafers CHIP2 and CHIP3 of FIG. 6), the at least one second chip includes an output logic circuit, and the output logic circuit includes at least two inputs, each of which is coupled The first end of each of the through-twisted vias of the at least one second wafer is coupled to the second end of a corresponding through-twisted via in the upper-level wafer. The wafers may include at least one third wafer (eg, wafers CHIP2 and CHIP3 of FIG. 7), the at least one third wafer including at least two data path circuits and an output logic circuit, the output ends of each data path circuit being connected a first signal input end of each data path circuit coupled to the first end of the corresponding through-silicon via The output end of the output logic circuit, the second signal input end of each data path circuit receives the trigger control signal of the memory device of the data path circuit, and each input end of the output logic circuit is coupled to a corresponding through-pass perforation in the upper stage wafer The second end. The wafers may also include a wafer having no data path circuitry and no output logic circuitry. The first end of each through-silicon via is directly coupled to a second end of a corresponding through-silicon via in the upper level wafer.

In summary, the through-silicone via repair circuit of the present disclosure transmits data by using at least two sets of TSV data paths, and each set of TSV data paths includes a memory device for recording the TSV status of the TSV data path, and The self-detection operation is performed to detect the TSV status of each TSV data path and the memory device of each TSV data path stores the TSV status of each TSV data path before the data transmission operation of the through-silicone perforation repair circuit. When the TSV status of any one of the TSV data paths is defective, the protection circuit of the TSV data path is turned on to pull the first end of the TSV to the ground voltage, and the power control circuit of the TSV data path is turned off to avoid the power leakage current. Flow to the substrate and save power consumption of the set of TSV data paths. Since the memory device can always save the TSV as a normal or defective state after the self-detection operation, if the TSV is in a defective state, the power control circuit of the TSV data path can be continuously turned off and the first end of the TSV is continuously maintained. Pull to ground voltage. At the same time, the at least two sets of TSV data paths are all connected to the output logic circuit, and the corrected correct circuit is transmitted to the next stage circuit by the output logic circuit.

The above is an overview feature of the embodiment. Those of ordinary skill in the art should be able to readily design or adapt the present invention to perform the same purpose and/or achieve the same advantages of the embodiments described herein. point. It should be understood by those of ordinary skill in the art that the same configuration should not depart from the spirit and scope of the present invention, and various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present invention. The illustrative methods are merely illustrative of the steps, but are not necessarily performed in the order presented. The steps may be additionally added, substituted, changed, and/or eliminated, as appropriate, and are consistent with the spirit and scope of the disclosed embodiments.

110‧‧‧Substrate

121-1, 121-2, 121-m, 122-1, 122-2, 122-n‧‧‧TSV

131, 132‧‧‧ data path circuit

140‧‧‧Output logic circuit

200‧‧‧Power Control Circuit

210‧‧‧Input drive circuit

220‧‧‧TSV detection circuit

230‧‧‧ memory device

250‧‧‧Protection circuit

CHIP1, CHIP2‧‧‧ wafer

OUT‧‧‧output signal end

VDD‧‧‧Power supply voltage

Vin1, Vin2‧‧‧ signal end

Claims (26)

A through-silicon via repair circuit for a semiconductor device includes: a first wafer and a second wafer, the first wafer and the second wafer being stacked one on another; at least two through-silicon vias penetrating the first wafer The substrate is configured to transfer data between the first wafer and the second wafer; at least two data path circuits are disposed on the first wafer, and are respectively connected to one of the at least two through-twisted perforations The crystal perforation, each of the at least two data path circuits includes: an input driving circuit, converting a signal input by the first signal input terminal according to a power supply voltage and a ground voltage, and transmitting the signal to the corresponding through-silicone perforation One end; a through-silicone via detecting circuit coupled to the first signal input end and the first end of the corresponding through-silicon via, detecting a through-through perforated state of the corresponding through-silicon via a memory device, the control end of which is coupled to a second signal input end, and receives and stores the through-passing perforated state from the through-silicone perforation detecting circuit; And coupling to the first end of the memory device and the corresponding through-silicon via, determining whether to pull the first end of the corresponding through-silicon via according to the through-silicon via state saved by the memory device And the power supply control circuit is coupled between the power supply voltage and the input drive circuit to provide the power supply voltage to the input drive circuit, and And coupled to the memory device; and an output logic circuit disposed on the second chip, the at least two input ends of the output logic circuit are respectively coupled to the second ends of the at least two through-silicon vias, and according to The signals of the at least two inputs generate an output signal. The through-silicone perforation repairing circuit of claim 1, wherein the first signal input terminal inputs a detection driving signal before the data transmission is performed by the through-silicone repairing circuit, and the direct-passing perforation detection The measuring circuit detects the through-silicon via state according to the detected driving signal, and the second signal input terminal inputs a memory trigger signal to trigger the memory device to save the through-silicon via state. The through-silicone via repair circuit according to claim 2, wherein if the through-silicon via state is a defect, the power control circuit stops supplying the power voltage to the input driving circuit, and the protection circuit The first end of the corresponding through-silicon via is pulled to the ground voltage. The straight-through twinned hole repairing circuit of claim 1, wherein the power control circuit comprises: a first switch, the first end of the first switch is coupled to the power supply voltage, and the first switch is The two ends are coupled to the power supply end of the input driving circuit, and the control end of the first switch is coupled to the output end of the memory device. The straight-through twinned hole repairing circuit of claim 1, wherein the protection circuit comprises: a second switch, the first end of the second switch being coupled to the first of the corresponding through-twisted perforations The second end of the second switch is coupled to the connection The ground voltage, the control end of the second switch is coupled to the output end of the memory device. The straight-through twinned hole repairing circuit of claim 1, wherein the input driving circuit comprises: an inverter having an input end coupled to the first signal input end and an output end coupled to the corresponding end; Straight through the first end of the twinned perforation. The through-silicone via repair circuit of claim 1, wherein the through-silicon via detection circuit comprises: a first reverse gate, the first input end of which is coupled to the corresponding through-silicon via The first end of the first end is coupled to the first signal input end, and the output end is coupled to the input end of the memory device. The straight-through twinned hole repairing circuit of claim 1, wherein the output logic circuit comprises: a second reverse gate, wherein at least two input ends are respectively coupled to the at least two through-twisted perforations The second end. The through-silicone perforation repair circuit of the first aspect of the invention, wherein the memory device comprises: a holder; a third switch, the first end of the third switch is coupled to the through-silicone via detection An output end of the circuit, the second end of the third switch is coupled to the input end of the holder, the control end of the third switch is coupled to the second signal input end; and a buffer, the input of the buffer The end is coupled to the output of the holder, and the output of the buffer is coupled to the protection circuit. The through-silicone via repair circuit of claim 1, wherein the memory device comprises a latch, a D-type flip-flop or a non-volatile memory. The through-silicone perforation repairing circuit of claim 1, wherein the at least two through-twisting vias comprise at least one first through-twisting perforation and at least one second through-twisting perforation, the at least two The data path circuit includes a first data path circuit and a second data path circuit, the first data path circuit is coupled to the first end of the at least one first through-silicon via, and the second data path circuit is coupled And to the first end of the at least one second through-twisting hole. The through-silicone perforation repairing circuit of claim 1, wherein the at least two through-silicon vias comprise at least one first through-silicon via, at least one second through-silicon via, and at least a third The at least two data path circuits include a first data path circuit, a second data path circuit, and a third data path circuit, and the first data path circuit is coupled to the at least one first straight The first data path is coupled to the first end of the at least one second through-silicon via, the third data path circuit is coupled to the at least one third through-silicon via The first end. A through-silicon via repair circuit for a semiconductor device includes: a plurality of wafers stacked on top of each other, each wafer of the wafers including at least two through-twisted perforations penetrating the substrate of each wafer, and each The at least two through-twisted perforations of a wafer are directly or indirectly Connecting to one of the at least two through-silicon vias of the wafer adjacent to each of the wafers, wherein the at least one first wafer includes at least two data path circuits, and the wafers are The at least one second chip includes an output logic circuit, and the at least two data path circuits of the at least one first wafer are respectively connected to the at least two through-twisted vias of the at least one first wafer. Perforating, each data path circuit includes: an input driving circuit, converting a signal input by a first signal input terminal according to a power supply voltage and a ground voltage, and transmitting the signal to the first end of the corresponding through-silicone perforation; a 穿孔 穿孔 侦测 侦测 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔The control end is coupled to a second signal input end, and receives and stores the through-passing perforated state from the through-silicone via detection circuit; a protection circuit coupled to The first end of the memory device and the corresponding through-silicon via is determined according to the through-silicon via state stored by the memory device to determine whether the first end of the corresponding through-silicon via is pulled to the ground voltage; And a power control circuit coupled between the power supply voltage and the input driving circuit, the power supply voltage is supplied to the input driving circuit, and coupled to the memory device; wherein the output logic circuit of the at least one second chip At least two The input ends respectively correspond to the second ends of the at least two through-silicon vias coupled to the upper-level wafer of the at least one second wafer, and generate output signals according to the signals of the at least two inputs. The through-silicone perforation repair circuit of claim 13, wherein the first signal input terminal inputs a detection driving signal before the data transmission is performed by the through-silicone repairing circuit, and the direct-passing perforation detection The measuring circuit detects the through-silicon via state according to the detected driving signal, and the second signal input terminal inputs a memory trigger signal to trigger the memory device to save the through-silicon via state. The through-silicone via repair circuit according to claim 14, wherein if the through-silicon via state is a defect, the power control circuit stops supplying the power voltage to the input driving circuit, and the protection circuit The first end of the corresponding through-silicon via is pulled to the ground voltage. The straight-through twinned hole repairing circuit of claim 13 , wherein the power control circuit comprises: a first switch, the first end of the first switch is coupled to the power supply voltage, and the first switch is The two ends are coupled to the power supply end of the input driving circuit, and the control end of the first switch is coupled to the output end of the memory device. The straight-through twinned hole repairing circuit of claim 13 , wherein the protection circuit comprises: a second switch, the first end of the second switch being coupled to the first of the corresponding through-twisted perforations The second end of the second switch is coupled to the ground voltage, and the control end of the second switch is coupled to the output end of the memory device. The straight-through twinned hole repairing circuit of claim 13 , wherein the input driving circuit comprises: an inverter having an input end coupled to the first signal input end and an output end coupled to the corresponding end Straight through the first end of the twinned perforation. The through-silicone via repair circuit of claim 13 , wherein the through-silicon via detection circuit comprises: a first reverse gate, the first input end of which is coupled to the corresponding through-silicon via The first end of the first end is coupled to the first signal input end, and the output end is coupled to the input end of the memory device. The through-silicone via repair circuit of claim 13, wherein the output logic circuit comprises: a second reverse gate, wherein at least two input terminals are respectively coupled to the at least one second wafer The second ends of the at least two through-twisted vias of the primary wafer. The through-silicone perforation repair circuit of claim 13, wherein the memory device comprises: a holder; a third switch, the first end of the third switch is coupled to the through-silicone via detection An output end of the circuit, the second end of the third switch is coupled to the input end of the holder, the control end of the third switch is coupled to the second signal input end; and a buffer, the input of the buffer The end is coupled to the output of the holder, and the output of the buffer is coupled to the protection circuit. Straight through perforation repair as described in claim 13 The circuit, wherein the memory device comprises a latch, a D-type flip-flop or a non-volatile memory. The through-silicone via repair circuit of claim 13, wherein the at least two through-silicon vias of a wafer comprise at least one first through-silicon via and at least one second through-silicon via. The at least two data path circuits of the at least one first chip include a first data path circuit and a second data path circuit, and the first data path circuit of the at least one first chip is coupled to the at least one first chip The first end of the at least one first through-silicon via is coupled to the second data path circuit of the at least one first wafer to the at least one second through-silicon via of the at least one first wafer One end. The through-silicone via repair circuit of claim 13, wherein the at least two through-silicon vias of the wafer comprise at least one first through-silicon via, at least one second through-silicon via, and at least a third through-silicon via, the at least two data path circuits of the at least one first chip comprise a first data path circuit, a second data path circuit and a third data path circuit, the at least one first chip The first data path circuit is coupled to the first end of the at least one first through-silicon via of the at least one first chip, and the second data path circuit of the at least one first chip is coupled to the at least one a first end of the at least one second through-silicon via of the first die, the third data path circuit of the at least one first die coupled to the at least one third pass twin of the at least one first die The first end of the perforation. Straight through perforation repair as described in claim 13 The circuit, wherein the second ends of the at least two through-silicon vias of the upper-level wafer of the at least one second wafer are respectively coupled to one of the at least two through-twisted vias of the at least one second wafer The first end of the twinned perforation. A through-silicon via repair circuit for a semiconductor device includes: a plurality of wafers stacked on top of each other, each wafer of the wafers including at least two through-twisted perforations that penetrate a substrate of each wafer, At least one first chip in the wafer includes at least two data path circuits, and at least one of the second chips includes an output logic circuit and at least two data path circuits, and the at least two data paths of the at least one first chip The circuit is respectively connected to one of the at least two through-silicon vias of the at least one first wafer, wherein the at least two data path circuits are respectively connected to the at least one second Each of the data path circuits includes: an input driving circuit for converting a signal input by the first signal input terminal according to a power supply voltage and a ground voltage; and the corresponding one of the at least two through-silicon vias And transmitting to the first end of the corresponding through-silicone via; the through-hole via detection circuit is coupled to the first signal The input end and the first end of the corresponding through-silicon via are detected by the corresponding through-silicon via perforation state; and a memory device having a control end coupled to a second signal input terminal The through-silicone perforation detecting circuit receives and saves the through-channel a crystal-perforated state; a protection circuit coupled to the memory device and the first end of the corresponding through-silicon via; and determining whether to pass the corresponding through-pass twin according to the through-silicon via state saved by the memory device The first end of the through hole is pulled to the ground voltage; and a power control circuit is coupled between the power supply voltage and the input drive circuit to provide the power supply voltage to the input drive circuit and coupled to the memory device; The at least two input ends of the output logic circuit of the at least one second chip are respectively coupled to the second ends of the at least two through-silicon vias of the upper-level wafer of the at least one second wafer, and according to the The output signals of the at least two input signals are coupled to the first signal input end of the at least two data path circuits of the at least one second chip.