TWI515855B - Lead frame package with improved ground bond stability - Google Patents
Lead frame package with improved ground bond stability Download PDFInfo
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- TWI515855B TWI515855B TW099135404A TW99135404A TWI515855B TW I515855 B TWI515855 B TW I515855B TW 099135404 A TW099135404 A TW 099135404A TW 99135404 A TW99135404 A TW 99135404A TW I515855 B TWI515855 B TW I515855B
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- H10W70/411—
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- H10W70/421—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H10W72/0198—
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- H10W72/075—
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- H10W72/07511—
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- H10W72/07533—
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- H10W72/536—
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- H10W72/5363—
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- H10W72/5434—
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- H10W72/5445—
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- H10W72/5522—
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- H10W72/5525—
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- H10W74/00—
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- H10W90/756—
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- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明大體而言係關於基於引線架之半導體封裝。更特定而言,描述提昇晶粒與充當用於封裝之接點之晶粒附著襯墊之間的電連接之穩定性的配置。The present invention relates generally to lead frame based semiconductor packages. More specifically, a configuration is described that enhances the stability of the electrical connection between the die and the die attach pad that serves as a contact for the package.
許多半導體封裝利用金屬引線架來提供積體電路晶粒與外部組件之間的電互連。常使用被稱作「接合線」之極小電線來將晶粒上之I/O襯墊(常稱作「接合襯墊」)電連接至引線架中之對應引線/接點。典型地,晶粒、接合線及引線架之部分囊封於塑膠中以進行保護,而留下引線架之部分暴露以促進至外部裝置之電連接。Many semiconductor packages utilize metal leadframes to provide electrical interconnection between the integrated circuit die and external components. Very small wires called "bonding wires" are often used to electrically connect the I/O pads on the die (often referred to as "bond pads") to corresponding leads/contacts in the leadframe. Typically, portions of the die, bond wires, and leadframe are encapsulated in the plastic for protection while leaving portions of the leadframe exposed to facilitate electrical connection to external devices.
許多引線架包括在封裝之組裝期間支撐晶粒的晶粒附著襯墊(DAP)。在一些此種封裝中,晶粒附著襯墊暴露於封裝之一表面(典型地,底表面)上。暴露之晶粒附著襯墊可幫助進行封裝之熱管理,因為晶粒附著襯墊提供用於耗散由晶粒產生之過量熱的良好熱傳導路徑。在一些暴露之DAP封裝中,亦將晶粒附著襯墊用作用於封裝之電接點。最常見的是,將晶粒附著襯墊用作接地襯墊,但在少許封裝中其可用作一電源襯墊,且理論上其可或者用作一信號襯墊。Many leadframes include a die attach pad (DAP) that supports the die during assembly of the package. In some such packages, the die attach pad is exposed to one surface (typically the bottom surface) of the package. The exposed die attach liner can aid in thermal management of the package because the die attach pad provides a good thermal conduction path for dissipating excess heat generated by the die. In some exposed DAP packages, die attach pads are also used as electrical contacts for packaging. Most commonly, a die attach pad is used as the ground pad, but it can be used as a power pad in a few packages, and theoretically it can be used either as a signal pad.
當晶粒附著襯墊用作電接點時,常使用接合線來將晶粒上之一或多個接地I/O襯墊電連接至晶粒附著襯墊(常稱作「向下接合」之程序)。最常見的是,將極精細金或銅線用作接合線,且引線架係由銅或銅基合金形成。由於金並不良好地黏附至銅,故晶粒附著襯墊之頂表面(及引線架之其他相關部分)典型地鍍有銀薄膜,該銀薄膜較銅而易於黏附至金接合線。偶爾發生之問題為在裝置之使用期間晶粒有時將自晶粒附著襯墊脫層。亦可在晶粒附著襯墊與囊封晶粒之模製化合物之間發生脫層。當發生脫層時,相對於晶粒附著襯墊之晶粒之移動有時可使向下接合線與晶粒附著襯墊分離或以其他方式破壞向下接合線。When a die attach pad is used as an electrical contact, a bond wire is often used to electrically connect one or more ground I/O pads on the die to the die attach pad (often referred to as "down-bonding" Program). Most commonly, very fine gold or copper wires are used as bonding wires, and the lead frame is formed of copper or a copper-based alloy. Since gold does not adhere well to copper, the top surface of the die attach pad (and other related portions of the lead frame) is typically plated with a silver film that is easier to adhere to the gold bond wire than copper. Occasionally the problem is that the granules sometimes delaminate from the die attach liner during use of the device. Debonding may also occur between the die attach liner and the molding compound that encapsulates the die. When delamination occurs, the movement of the die relative to the die attach pad can sometimes separate or otherwise break the down bond line from the die attach pad.
亦可在引線處發生類似脫層問題。舉例而言,脫層有時發生在模製材料與引線指狀物之間,尤其在鍍有銀之引線架之區中。模製材料與引線之間的脫層亦可損壞接合線。A similar delamination problem can also occur at the leads. For example, delamination sometimes occurs between the molding material and the lead fingers, particularly in the area of the silver-plated lead frame. Debonding between the molding material and the leads can also damage the bond wires.
在圖1A及圖1B中圖解地說明適用於具有暴露晶粒附著襯墊之封裝中的代表性引線架。圖1A為引線架100之俯視平面圖,其中一晶粒附著且電連接至該引線架。圖1B為沿剖面線A-A截取之圖1A之橫截面側視圖。晶粒102使用接地接合線106線接合至接地之晶粒附著襯墊104。接地接合線106之一端附著至晶粒102上之接地I/O襯墊110,而另一端直接附著至晶粒附著襯墊104。在使用金接地接合線106之設計中,接地之晶粒附著襯墊104常鍍有銀以便改良接合之品質。另外,接合線108將晶粒102之I/O襯墊116連接至引線架124之相關聯引線112,以便按照積體電路設計中的需要電連接晶粒。舉例而言,可使用接合線108將晶粒102連接至電源、信號線,或任何其他適合電連接。晶粒附著襯墊104係藉由連接桿118支撐。A representative lead frame suitable for use in a package having exposed die attach pads is illustrated diagrammatically in Figures 1A and 1B. 1A is a top plan view of leadframe 100 with a die attached and electrically connected to the leadframe. Figure 1B is a cross-sectional side view of Figure 1A taken along section line A-A. The die 102 is wire bonded to the grounded die attach pad 104 using ground bond wires 106. One end of the ground bond wire 106 is attached to the ground I/O pad 110 on the die 102 while the other end is directly attached to the die attach pad 104. In the design using the gold ground bond wire 106, the grounded die attach pad 104 is often plated with silver to improve the quality of the bond. In addition, bond wires 108 connect I/O pads 116 of die 102 to associated leads 112 of leadframe 124 to electrically connect the die as needed in the integrated circuit design. For example, bond wires 108 can be used to connect die 102 to a power supply, signal line, or any other suitable electrical connection. The die attach liner 104 is supported by a tie bar 118.
儘管習知接地接合方法良好地適用於許多應用中,但仍持續努力改良接地接合之穩定性。While conventional ground bonding methods are well suited for use in many applications, efforts continue to improve the stability of ground bonding.
為達成本發明之前述及其他目標,晶粒上之一或多個選定I/O襯墊(例如,接地I/O襯墊)電耦接至一攜載晶粒附著襯墊之連接桿之一部分,或一連接至此連接桿之結構。該接合區在該晶粒附著襯墊上方升高。由於將晶粒電連接至該晶粒附著襯墊之接合線在與晶粒附著襯墊不同之平面中接合,故若晶粒自晶粒附著襯墊脫層,則該等接合較不可能被破壞或損壞。相對於接合區而下置(downset)晶粒附著襯墊准許在脫層情況下進行較多相對運動,從而引起具有提昇之電穩定性的接地接合。在一些較佳具體實例中,接地區比相關聯連接桿之其他部分寬。此配置允許多個接地I/O襯墊電耦接至晶粒附著襯墊。To achieve the foregoing and other objects of the present invention, one or more selected I/O pads (eg, ground I/O pads) on the die are electrically coupled to a tie bar carrying a die attach pad. A part, or a structure connected to this connecting rod. The land is raised above the die attach pad. Since the bonding wires electrically connecting the die to the die attach pad are bonded in a different plane from the die attach pad, if the die is delaminated from the die attach pad, the bonding is less likely to be Damaged or damaged. Downsetting the die attach pad relative to the land permits more relative motion in the case of delamination, resulting in a ground bond with improved electrical stability. In some preferred embodiments, the landing area is wider than the other portions of the associated connecting rod. This configuration allows multiple ground I/O pads to be electrically coupled to the die attach pads.
一些具體實例可具有一矩形放大接合區,而其他具體實例可具有一熔合之引線形狀。熔合之引線形狀包括自連接桿朝向晶粒附著襯墊向內延伸之至少一指狀部分。放大接合區之增加之表面積允許一連接桿上有多個接地接合位置。且,在一些設計中,引線架可具有多個連接桿及放大接合區,其可定位於晶粒之相對側上或在其他適合位置處。Some specific examples may have a rectangular enlarged land, while other embodiments may have a fused lead shape. The fused lead shape includes at least one finger portion extending inwardly from the connecting rod toward the die attach pad. The increased surface area of the enlarged land allows for a plurality of ground engaging locations on a connecting rod. Also, in some designs, the lead frame can have a plurality of tie bars and enlarged landing zones that can be positioned on opposite sides of the die or at other suitable locations.
半導體封裝亦可囊封於塑膠囊封物中以便保護任何相關聯裝置。晶粒附著襯墊之後表面常暴露以促進至外部裝置之電連接。The semiconductor package can also be encapsulated in a plastic encapsulant to protect any associated device. The surface of the die attach liner is often exposed to facilitate electrical connection to an external device.
在審查以下圖式及詳細描述之後,對於熟習此項技術者而言,本發明之其他設備、方法、特徵及優點將顯而易見或將變得顯而易見。所有此等額外系統、方法、特徵及優點意欲包括於此描述內,包括於本發明之範疇內,且由隨附申請專利範圍保護。Other devices, methods, features, and advantages of the present invention will be apparent or apparent from the <RTIgt; All such additional systems, methods, features, and advantages are intended to be included within the scope of the present invention and are covered by the scope of the appended claims.
在以下圖式中,相同參考符號有時用以指示相同結構元件。亦應瞭解,該等圖中之描繪為圖解的且並未按比例繪製。結合隨附圖式,藉由參考以下描述,可最好地理解本發明及其優點。In the following figures, the same reference symbols are sometimes used to indicate the same structural elements. It is also to be understood that in the drawings The invention and its advantages are best understood by referring to the following description in conjunction with the claims.
本發明大體而言係關於用於將晶粒上之選定I/O襯墊(例如,接地襯墊)電連接至基於引線架之積體電路封裝中之晶粒附著襯墊的改良型設計及技術。The present invention relates generally to an improved design for electrically connecting selected I/O pads (e.g., ground pads) on a die to a die attach pad in a lead frame based integrated circuit package and technology.
在以下描述中,闡述眾多特定細節,以便提供對本發明之透徹理解。然而,應理解,可在無一些或全部此等特定細節之情況下實踐本發明。在其他情況下,未詳細描述熟知程序操作,從而不會不必要地混淆本發明。Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. However, it is to be understood that the invention may be practiced without some or all of these specific details. In other instances, well-known program operations have not been described in detail so as not to unnecessarily obscure the invention.
如在【先前技術】章節中所描述,一些基於引線架之積體電路封裝經設計以使得晶粒藉由將晶粒直接線接合至引線架之接地之晶粒附著襯墊部分而電連接至接地。此程序常被稱作「向下接合」。在向下接合封裝中有時會出現之問題為:晶粒有時可自晶粒附著襯墊脫層,從而潛在地引起晶粒與晶粒附著襯墊之間的相對運動。當發生此移動時,存在向下接合之接合線可自晶粒附著襯墊開裂或以其他方式損壞或破壞之風險,其可引起不良電穩定性。As described in the [Prior Art] section, some leadframe-based integrated circuit packages are designed such that the die is electrically connected to the die attach pad portion of the lead frame by direct wire bonding to the lead frame. Ground. This program is often referred to as "downward bonding." A problem that sometimes arises in down-bonded packages is that the grains can sometimes be delaminated from the die attach pads, potentially causing relative motion between the die and the die attach pads. When this movement occurs, there is a risk that the downwardly joined bond wires may crack or otherwise be damaged or destroyed from the die attach pads, which may cause poor electrical stability.
為解決此問題,本發明描述一種積體電路封裝,其中晶粒上之選定接地I/O襯墊使用接合線電耦接至連接桿之線接合導降區。連接桿(其為引線架之一部分)在封裝期間直接連接至晶粒附著襯墊,且機械地支撐晶粒附著襯墊,但大體上自身不欲用作用於封裝之電接點。在來自先前技術之許多設計中,連接桿為僅用以支撐晶粒附著襯墊之薄金屬片。本申請案預期進一步使用連接桿作為用於積體電路封裝之接地平面之部分。晶粒附著襯墊之晶粒安裝表面相對於連接桿之線接合導降區而下置。在一些具體實例中,線接合導降區在封裝內與引線處於相同高度。儘管所描述之具體實例預期使用晶粒附著襯墊作為接地接點,但應理解,可將晶粒附著襯墊用作用於其他功能(諸如電源或信號端子)之接點。To address this problem, the present invention describes an integrated circuit package in which selected ground I/O pads on the die are electrically coupled to the wire bond landings of the tie bars using bond wires. The connecting rod, which is part of the lead frame, is directly connected to the die attach pad during packaging and mechanically supports the die attach pad, but is generally not itself intended to be used as an electrical contact for the package. In many designs from the prior art, the tie bars are thin metal sheets that are only used to support the die attach pads. The present application contemplates the use of a connecting rod as part of the ground plane for the integrated circuit package. The die attach surface of the die attach pad is lowered relative to the wire bonding landing zone of the tie bar. In some embodiments, the wire bond landing zone is at the same height as the lead within the package. While the specific examples described are contemplated to use a die attach pad as a ground contact, it should be understood that the die attach pad can be used as a contact for other functions, such as power or signal terminals.
最初參看圖2A至圖2D,展示根據本發明之第一具體實例。圖2A說明一引線架面板224之一裝置區域214之俯視平面圖,其包括引線212、連接桿218以及晶粒附著襯墊204。除了此等組件之外,放大接合區220與連接桿218整體地形成。晶粒附著襯墊204藉由連接桿218攜載且因此電耦接且機械耦接至連接桿218,連接桿218又附著至引線架面板224中之支撐桿223。複數條引線212亦機械地附著至引線架224且朝向晶粒附著襯墊204向內延伸。接合區220可藉由經由連接桿218電連接至一接地之晶粒附著襯墊204而接地。當引線架係由銅或銅合金形成時,大體需要接合區220鍍有銀膜以提昇金接合線之黏附性。Referring initially to Figures 2A through 2D, a first embodiment in accordance with the present invention is shown. 2A illustrates a top plan view of a device region 214 of a leadframe panel 224 that includes leads 212, tie bars 218, and die attach pads 204. In addition to these components, the enlarged land 220 is integrally formed with the connecting rod 218. The die attach pad 204 is carried by the tie bar 218 and is thus electrically coupled and mechanically coupled to the tie bar 218, which in turn is attached to the support bar 223 in the lead frame panel 224. A plurality of leads 212 are also mechanically attached to the lead frame 224 and extend inwardly toward the die attach pad 204. The land 220 can be grounded by being electrically connected to a grounded die attach pad 204 via a tie bar 218. When the lead frame is formed of copper or a copper alloy, it is generally required that the land 220 is plated with a silver film to enhance the adhesion of the gold bonding wires.
在此第一具體實例中,將接合區220形成為一矩形區域,其實際上為連接桿218之一部分。然而,將瞭解,接合區220可形成於連接桿上之其他適合部位處且可採用任何其他適合形狀及大小。接合區220典型地比其相關聯之連接桿218之其他部分寬。較大區由於各種原因可為有用的,諸如提供用以接合多條線之較大表面積。且,儘管在此具體實例中展示兩個連接桿及放大接合區,但視晶粒之設計所需,每一裝置區域214可具有僅一個連接桿及接合區,或者兩個以上連接桿及接合區。圖2A說明在晶粒附著襯墊204之相對側上將兩個連接桿218機械地連接至晶粒附著襯墊204,但連接桿218亦可附著至任何(或所有)晶粒附著襯墊角部。In this first specific example, the land 220 is formed as a rectangular region that is actually a portion of the connecting rod 218. However, it will be appreciated that the lands 220 can be formed at other suitable locations on the connecting rod and can take any other suitable shape and size. Junction zone 220 is typically wider than other portions of its associated connecting rod 218. Larger regions may be useful for a variety of reasons, such as providing a larger surface area for joining multiple wires. Moreover, although two tie bars and enlarged lands are shown in this particular example, each device region 214 may have only one tie rod and lands, or more than two tie bars and joints, depending on the design of the die. Area. 2A illustrates the mechanical connection of two tie bars 218 to the die attach pad 204 on opposite sides of the die attach pad 204, but the tie bars 218 may also be attached to any (or all) die attach pad angles. unit.
圖2B描繪積體電路封裝200之俯視平面圖。在圖2B中,晶粒202機械地附貼至晶粒附著襯墊204之晶粒安裝表面226。該晶粒包括在晶粒202之作用表面上之複數個I/O襯墊(接合襯墊)。第一組I/O襯墊216中之每一I/O襯墊設計成將晶粒202連接至引線架224之相關聯引線212。I/O襯墊216可用於各種目的,包括將晶粒202連接至電源、信號線、接地平面或其他適合功能。如圖2B中所說明,I/O襯墊216使用接合線208電連接至引線212。在一較佳具體實例中,接合線208係由金製成,但可使用諸如銅之其他適合材料。此外,接合線較佳地以熱超音波方式接合,從而引起在一I/O襯墊216處之金焊球接合及一對應引線212處之針接合。2B depicts a top plan view of integrated circuit package 200. In FIG. 2B, die 202 is mechanically attached to die mounting surface 226 of die attach pad 204. The die includes a plurality of I/O pads (bond pads) on the active surface of the die 202. Each of the first set of I/O pads 216 is designed to connect the die 202 to the associated leads 212 of the lead frame 224. I/O pads 216 can be used for a variety of purposes, including connecting die 202 to a power source, signal line, ground plane, or other suitable function. As illustrated in FIG. 2B, I/O pads 216 are electrically connected to leads 212 using bond wires 208. In a preferred embodiment, bond wire 208 is made of gold, but other suitable materials such as copper can be used. In addition, the bond wires are preferably joined in a thermal ultrasonic manner to cause gold bond ball bonding at an I/O pad 216 and pin bonding at a corresponding lead 212.
第二組I/O襯墊210(「接地I/O襯墊」)中之每一I/O襯墊設計成將晶粒202電連接至一接地平面,該接地平面在此狀況下為放大接合區220。在圖2A至圖2D之具體實例中,接地I/O襯墊210經由接地接合線206接合至連接桿218之放大接合區220。較佳地,接地接合線係由金製成,且該等接合係以超音波方式產生,從而引起在一I/O襯墊210處之金焊球接合及一對應放大接合區220處之針接合。儘管在圖2B中將兩條接地接合線206連接至每一接合區220,但在一些具體實例中將僅一個或者兩個以上接地接合線連接至單一接合區可為有用的。積體電路封裝200亦可包括囊封物,其未在圖2B中展示。Each of the second set of I/O pads 210 ("grounded I/O pads") is designed to electrically connect the die 202 to a ground plane that is magnified in this situation. Junction area 220. In the example of FIGS. 2A-2D, the ground I/O pad 210 is bonded to the enlarged lands 220 of the tie bars 218 via ground bond wires 206. Preferably, the ground bonding wires are made of gold and the bonding is produced in an ultrasonic manner to cause gold ball bonding at an I/O pad 210 and a corresponding pin at the enlarged bonding region 220. Engage. Although two ground bond wires 206 are connected to each land 220 in FIG. 2B, it may be useful in some embodiments to connect only one or more ground bond wires to a single land. The integrated circuit package 200 can also include an encapsulant, which is not shown in Figure 2B.
圖2C說明沿剖面B-B截取的在圖2B中呈現之封裝200之側視橫截面圖。如圖式中展示,晶粒附著襯墊204之晶粒安裝表面226較佳以距離h 1 相對於連接桿218之放大接合區220而下置。將接地接合線206耦接至一升高之放大接合區220會改良接地接合之電穩定性。該連接較不易受歸因於晶粒脫層之損壞之影響,因為藉由接地接合線產生之迴路相比於先前技術設計(諸如圖1中所展示之先前技術設計)准許有較多的相對運動。晶粒與晶粒附著襯墊之間的相對運動因此較不可能引起對接地接合線206之損壞。2C illustrates a side cross-sectional view of the package 200 presented in FIG. 2B taken along section BB. As shown in the figures, the die attach surface 226 of the die attach pad 204 is preferably lowered at a distance h 1 relative to the enlarged land 220 of the tie bar 218. Coupling the ground bond wire 206 to a raised amplifying land 220 improves the electrical stability of the ground bond. This connection is less susceptible to damage due to die delamination because the loop generated by the ground bond wire permits more relative than prior art designs, such as the prior art design shown in FIG. motion. The relative motion between the die and the die attach pad is therefore less likely to cause damage to the ground bond wire 206.
圖2D為沿剖面C-C截取的在圖2B中呈現之封裝200之側視橫截面圖。引線212朝向晶粒202向內延伸。儘管在圖2D中引線212不直接上覆於晶粒202上,但熟習此項技術者將瞭解,引線212可不同地安置。晶粒附著襯墊204之晶粒安裝表面226以距離h 2 相對於引線212而下置。距離h 2 可大於或小於圖2C中所展示之距離h 1 。然而,在一較佳具體實例中,距離h 1 與h 2 實質上相等,以使得放大接合區220與引線212定位於晶粒安裝表面226上方之大致相同之高度。2D is a side cross-sectional view of the package 200 presented in FIG. 2B taken along section CC. Lead 212 extends inwardly toward die 202. Although lead 212 does not directly overlie die 202 in FIG. 2D, those skilled in the art will appreciate that lead 212 can be placed differently. Die attach pad mounting surface 204 of the die 226 by a distance h 2 from the leads 212 and the next set. The distance h 2 may be greater or less than the distance h 1 shown in Figure 2C. However, in a preferred embodiment, the distances h 1 and h 2 are substantially equal such that the enlarged land 220 and the leads 212 are positioned at substantially the same height above the die mounting surface 226.
晶粒202、晶粒附著襯墊204、引線212、I/O襯墊216、接地I/O襯墊210、接合線208、接地接合線206及連接桿218之部分可囊封於囊封物或模製材料222內。模製化合物通常為非導電塑膠或樹脂。在圖2C及圖2D中所說明之具體實例中,引線212之外部自囊封之封裝200之側面延伸以促進與一適合基板之電連接。The die 202, the die attach pad 204, the leads 212, the I/O pads 216, the ground I/O pads 210, the bond wires 208, the ground bond wires 206, and portions of the tie bars 218 may be encapsulated in the encapsulant Or within the molding material 222. The molding compound is usually a non-conductive plastic or resin. In the particular example illustrated in Figures 2C and 2D, the outer portion of lead 212 extends from the side of encapsulated package 200 to facilitate electrical connection to a suitable substrate.
晶粒附著襯墊204之底表面經由囊封物222暴露以促進將晶粒附著襯墊204電耦接至電接地平面。由於晶粒附著襯墊204電連接至連接桿218之接合區220,故此情形呈現一種將接地I/O襯墊電連接至接地的方法。The bottom surface of the die attach pad 204 is exposed via the encapsulant 222 to facilitate electrically coupling the die attach pad 204 to the electrical ground plane. Since the die attach pad 204 is electrically connected to the land 220 of the tie bar 218, this situation presents a method of electrically connecting the ground I/O pad to ground.
接著參看圖3A至圖3C,將描述根據本發明之另一具體實例。此具體實例中之許多特徵實質上類似於圖2A至圖2D之特徵,但在本文中呈現若干差異。圖3A展示一引線架裝置區域314,其具有在連接桿318上之放大接合區320且具有朝向晶粒附著襯墊304向內延伸之多條引線312。圖3A之放大接合區320之形狀(熔合之引線形狀)包括自連接桿318朝向晶粒附著襯墊304向內延伸之至少一指狀部分330。接合區320之大表面積允許單一連接桿318上有多個接地接合位置。接合區320又經由連接桿318電連接至晶粒附著襯墊304。3A to 3C, another specific example according to the present invention will be described. Many of the features in this particular example are substantially similar to the features of Figures 2A-2D, but present several differences. 3A shows a leadframe device region 314 having an enlarged lands 320 on the tie bars 318 and having a plurality of leads 312 extending inwardly toward the die attach pads 304. The shape of the enlarged lands 320 of FIG. 3A (fused lead shape) includes at least one finger portion 330 extending inwardly from the connecting rod 318 toward the die attach pad 304. The large surface area of the land 320 allows for a plurality of ground engaging locations on the single connecting rod 318. The land 320 is in turn electrically connected to the die attach pad 304 via a tie bar 318.
圖3B描繪積體電路封裝300之俯視圖,其中一晶粒302附著至晶粒附著襯墊304。類似圖2B之具體實例,接合線308將選定I/O襯墊316自晶粒302電連接至引線312。I/O襯墊316可用於各種目的,包括將晶粒302連接至電源、信號線、接地平面,或其他適合功能。在一較佳具體實例中,接合線308由金製成。此外,接合線308較佳地以超音波方式接合,從而引起在一I/O襯墊316處之金焊球接合及一對應引線312處之針接合。FIG. 3B depicts a top view of integrated circuit package 300 with a die 302 attached to die attach pad 304. Similar to the example of FIG. 2B, bond wires 308 electrically connect selected I/O pads 316 from die 302 to leads 312. I/O pads 316 can be used for a variety of purposes, including connecting die 302 to a power supply, signal lines, ground planes, or other suitable function. In a preferred embodiment, bond wire 308 is made of gold. In addition, bond wires 308 are preferably ultrasonically bonded to cause gold bond ball bonding at an I/O pad 316 and pin bonding at a corresponding lead 312.
第二組I/O襯墊310設計成將晶粒302電連接至一接地平面。在本具體實例中,接地I/O襯墊310經由接地接合線306接合至連接桿318之放大接合區320。較佳地,接地接合線306係由金製成,且該等接合係以超音波方式產生,從而引起在一I/O襯墊310處之金焊球接合及一對應放大接合區320處之針接合。The second set of I/O pads 310 are designed to electrically connect the die 302 to a ground plane. In this particular example, the ground I/O pad 310 is bonded to the enlarged lands 320 of the tie bars 318 via ground bond wires 306. Preferably, the ground bond wires 306 are made of gold and the bonds are ultrasonically generated to cause gold ball bonding at a I/O pad 310 and a corresponding enlarged land 320. Needle joint.
當適當地按比例繪製時,沿剖面D-D及E-E截取的在圖3B中展示之具體實例之側視圖可實質上分別類似於圖2C及圖2D之具體實例中所描繪之側視圖。作為該等具體實例之間的一顯著差異,圖3C說明沿圖3B之剖面F-F截取的積體電路封裝300之側視橫截面圖。接地接合線306將接地I/O襯墊310電連接至連接桿318之放大接合區320。在圖3C之圖式中,接地接合線306以超音波方式接合至接合區320之指狀部分330,該指狀部分330朝向晶粒向內延伸。When properly drawn to scale, the side views of the specific examples shown in FIG. 3B taken along sections D-D and E-E may be substantially similar to the side views depicted in the specific examples of FIGS. 2C and 2D, respectively. As a significant difference between these specific examples, FIG. 3C illustrates a side cross-sectional view of the integrated circuit package 300 taken along section F-F of FIG. 3B. The ground bond wire 306 electrically connects the ground I/O pad 310 to the amplifying land 320 of the tie rod 318. In the diagram of FIG. 3C, the ground bond wire 306 is ultrasonically bonded to the finger portion 330 of the land 320, the finger portion 330 extending inwardly toward the die.
類似圖2A至圖2D中所展示之具體實例,晶粒附著襯墊304之晶粒安裝表面326以距離h 1 相對於放大接合區320而下置且以距離h 2 相對於引線312而下置。儘管此等距離無需為相等的,但接合區320及引線312可處於晶粒附著襯墊304之晶粒安裝表面326上方之實質上相同之高度。放大接合區320之高安置藉由減少接地接合線306上之相關聯應力來改良接地接合之穩定性。Similar to the embodiment shown in FIGS. 2A-2D, the die attach surface 326 of the die attach pad 304 is lowered at a distance h 1 relative to the enlarged land 320 and is lowered relative to the lead 312 by a distance h 2 . . Although the equidistances need not be equal, the lands 320 and leads 312 can be at substantially the same height above the die attach surface 326 of the die attach pad 304. The high placement of the amplifying junction 320 improves the stability of the ground junction by reducing the associated stress on the ground bond wires 306.
類似於上文描述之具體實例,積體電路封裝300較佳地封閉於囊封物或模製材料322內。晶粒附著襯墊304之後表面經由囊封物322暴露以連接至一接地平面,如上文詳細揭示。Similar to the specific examples described above, the integrated circuit package 300 is preferably enclosed within an encapsulant or molding material 322. The surface of the die attach liner 304 is then exposed via the encapsulant 322 to connect to a ground plane, as disclosed in detail above.
圖4A及圖4B呈現用以改良積體電路封裝中之接地接合穩定性之又一做法。在圖4中所說明之具體實例中,晶粒402上之接地I/O襯墊410中之一些使用具有固定於焊球上之楔之焊球接合(BSOB)技術直接耦接至接地之晶粒附著襯墊404。如圖4A中可見,最初在接地之晶粒附著襯墊404之晶粒安裝表面426上產生線接合凸塊432。藉由使用一標準線接合毛細管來將一焊球接合超音波地沈積至接地之晶粒附著襯墊404上來製成凸塊432。並非繼續導線之擠出,而是毛細管截去焊球接合凸塊432之頂部附近之導線,以使得僅線接合「焊球」或「凸塊」432保留在晶粒附著襯墊404之頂上。凸塊432可使用相比於正常用於線接合之力較大的力產生,其具有壓平凸塊從而增加其接合表面積且增加所得凸塊之強度的效應。4A and 4B present yet another practice for improving the stability of ground bonding in an integrated circuit package. In the specific example illustrated in FIG. 4, some of the ground I/O pads 410 on the die 402 are directly coupled to the ground using a solder ball bonding (BSOB) technique with a wedge attached to the solder balls. A particle attachment pad 404. As seen in FIG. 4A, wire bond bumps 432 are initially created on the die attach surface 426 of the grounded die attach pad 404. A bump 432 is formed by ultrasonically depositing a solder ball bond onto the grounded die attach pad 404 using a standard wire bond capillary. Rather than continuing the extrusion of the wire, the capillary intercepts the wire near the top of the ball bond bump 432 such that only the wire bond "bump" or "bump" 432 remains on top of the die attach pad 404. The bumps 432 can be produced using a force greater than the force normally used for wire bonding, which has the effect of flattening the bumps to increase their joint surface area and increase the strength of the resulting bumps.
接地I/O襯墊410接著使用接合線406線接合至凸塊432。接合線406可由金、銅或其他適合導電材料形成。在線接合程序期間,在接地I/O襯墊410處較佳地形成第二焊球接合,且可在凸塊432之頂部上形成針接合434。因此,接合線406經由位於凸塊432之頂上之針接合434電耦接至接地之晶粒附著襯墊404。在一些具體實例中,凸塊432在接地I/O襯墊410處之焊球接合之約1/3高度處。若晶粒附著襯墊404鍍有銀,則圖4中所揭示之具體實例改良接地接合之穩定性。此係因為焊球接合凸塊432相比於針接合較好地黏附至鍍銀之晶粒附著襯墊404。因此,凸塊432提供接合線406與晶粒附著襯墊404之晶粒安裝表面426之間的界面,從而減少接合線406中之剪應力且改良穩定性。Ground I/O pad 410 is then wire bonded to bump 432 using bond wires 406. Bond wire 406 can be formed from gold, copper, or other suitable electrically conductive material. A second solder ball bond is preferably formed at the ground I/O pad 410 during the wire bonding process, and a pin bond 434 can be formed on top of the bump 432. Thus, bond wire 406 is electrically coupled to grounded die attach pad 404 via pin bond 434 located atop top of bump 432. In some embodiments, bumps 432 are at about 1/3 of the height of the solder ball bond at ground I/O pad 410. If the die attach pad 404 is plated with silver, the specific example disclosed in Figure 4 improves the stability of the ground bond. This is because the solder ball bonding bumps 432 adhere better to the silver plated die attach pads 404 than the pin bonds. Thus, bumps 432 provide an interface between bond wires 406 and die attach surface 426 of die attach pads 404, thereby reducing shear stress in bond wires 406 and improving stability.
在圖4B中說明一另外之焊球上固定技術。在此具體實例中,在晶粒402上之接地I/O襯墊410上形成一初始凸塊442。接著使用接合線406將晶粒附著襯墊404電連接至I/O襯墊410上之凸塊442。在線接合程序期間,在晶粒附著襯墊404上形成一第二焊球接合446。再次,線接合器可利用相比於正常較大之接合力,其具有壓平凸塊從而增加接合強度及表面積的效應。An additional solder ball mounting technique is illustrated in Figure 4B. In this particular example, an initial bump 442 is formed on the ground I/O pad 410 on the die 402. The die attach pads 404 are then electrically connected to the bumps 442 on the I/O pads 410 using bond wires 406. A second solder ball bond 446 is formed on the die attach pad 404 during the wire bonding process. Again, the wire bonder can utilize the bonding force compared to normal, which has flattened bumps to increase the joint strength and surface area effects.
接著參看圖5A至圖5C,將描述本發明之又一具體實例。如熟習此項技術者將熟悉的,使用支撐裝置區域514之陣列528之引線架條帶524來組裝積體電路封裝常為有用的。此組態允許大量製造積體電路封裝。儘管圖5A至圖5C描繪類似於圖2A至圖2D中所呈現之裝置區域的裝置區域,但亦應瞭解,該引線架可支撐圖3A至圖3C及圖4之具體實例,以及任何其他適合具體實例。5A to 5C, still another specific example of the present invention will be described. It is often useful to assemble integrated circuit packages using lead frame strips 524 of array 528 of support device regions 514 as would be familiar to those skilled in the art. This configuration allows a large number of integrated circuit packages to be fabricated. Although FIGS. 5A-5C depict device regions similar to the device regions presented in FIGS. 2A-2D, it should also be appreciated that the leadframe can support the specific examples of FIGS. 3A-3C and FIG. 4, as well as any other suitable Specific examples.
圖5A描繪具有多重裝置區域514之引線架條帶524之一部分。通常,裝置區域514配置於面板524上之至少一個二維陣列528上,但各種其他配置為可能的(例如,一維陣列、非線性配置等)。在所說明具體實例中,展示裝置區域514之五個二維陣列528。然而,應瞭解,可提供更多或更少陣列528。引線架面板524典型地由銅或銅基合金形成,但其他適合材料(例如,鋁)可用於各種替代具體實例中。每一裝置區域514可含有如在以上具體實例中之任一者中描述之積體電路封裝。在將封裝組裝至引線架524上之後,引線架524在必要時單一化以產生準備好用於任何所要應用中之多個個別積體電路封裝。該單一化可經配置以犧牲連接桿518,且可使引線512與引線架524之晶粒附著襯墊504電隔離。FIG. 5A depicts a portion of a leadframe strip 524 having multiple device regions 514. Typically, device area 514 is disposed on at least one two-dimensional array 528 on panel 524, although various other configurations are possible (eg, one-dimensional arrays, non-linear configurations, etc.). In the illustrated embodiment, five two-dimensional arrays 528 of device regions 514 are shown. However, it should be appreciated that more or fewer arrays 528 may be provided. Lead frame panel 524 is typically formed from a copper or copper based alloy, although other suitable materials (e.g., aluminum) can be used in various alternative embodiments. Each device region 514 can contain an integrated circuit package as described in any of the above specific examples. After the package is assembled onto the lead frame 524, the lead frame 524 is singulated as necessary to produce a plurality of individual integrated circuit packages ready for use in any desired application. This singulation can be configured to sacrifice the tie bars 518 and can electrically isolate the leads 512 from the die attach pads 504 of the lead frame 524.
本發明亦可用於任何適合積體電路封裝型式中。舉例而言,在圖2A至圖2D及圖3A至圖3C之具體實例中,積體電路封裝200可用作在晶粒202之相對側上具有兩列引線212之雙列直插式封裝(dual in-line package,DIP)。當然,所揭示之封裝亦適用於各種其他封裝型式,諸如四方扁平封裝(quad flat packages,QFP)及薄型小尺寸封裝(thin small outline packages,TSOP)。The invention can also be used in any suitable integrated circuit package type. For example, in the specific examples of FIGS. 2A-2D and 3A-3C, the integrated circuit package 200 can be used as a dual in-line package having two columns of leads 212 on opposite sides of the die 202 ( Dual in-line package, DIP). Of course, the disclosed package is also applicable to a variety of other package types, such as quad flat packages (QFP) and thin small outline packages (TSOP).
儘管已詳細描述本發明之僅少許具體實例,但應瞭解,可按照許多其他形式實施本發明而不脫離本發明之精神或範疇。舉例而言,除了耦接至一電接地平面之外,放大接合區亦可用以耦接至電源或信號輸入。Although only a few specific examples of the invention have been described in detail, it is understood that the invention may be embodied in many other forms without departing from the spirit or scope of the invention. For example, in addition to being coupled to an electrical ground plane, the amplifying junction can also be coupled to a power source or signal input.
在預期至連接桿之區之線接合的所說明具體實例中,晶粒附著襯墊相對於引線及連接桿之線接合區兩者而下置。然而,在一些封裝(例如,QFN或LLP封裝)中,可需要引線之底表面充當與晶粒附著襯墊之底表面共平面的接點。在此等具體實例中,可需要抬升(up-set)晶粒附著襯墊之接合區以使得引線接點與晶粒附著襯墊保持實質上共平面。因此,應將本發明具體實例視為說明性且非限制性的,且本發明不限於本文中給出之細節,而是可在隨附申請專利範圍之範疇及等效物內修改。In the illustrated embodiment where wire bonding is desired to the region of the connecting rod, the die attach pad is lowered relative to both the wire and the wire bond region of the tie bar. However, in some packages (eg, QFN or LLP packages), the bottom surface of the leads may be required to serve as a joint that is coplanar with the bottom surface of the die attach pad. In such specific examples, it may be desirable to up-set the bond pads of the die attach pads such that the wire bonds remain substantially coplanar with the die attach pads. Therefore, the present invention is to be considered as illustrative and not restrictive, and the invention is not limited to the details of the invention.
100...引線架100. . . Lead frame
102...晶粒102. . . Grain
104...接地之晶粒附著襯墊104. . . Grounded die attach pad
106...接地接合線106. . . Ground wire
108...接合線108. . . Bonding wire
110...接地I/O襯墊110. . . Ground I/O pad
112...引線112. . . lead
116...I/O襯墊116. . . I/O pad
118...連接桿118. . . Connecting rod
200...積體電路封裝200. . . Integrated circuit package
202...晶粒202. . . Grain
204...晶粒附著襯墊204. . . Die attach liner
206...接地接合線206. . . Ground wire
208...接合線208. . . Bonding wire
210...第二組I/O襯墊210. . . Second set of I/O pads
212...引線212. . . lead
214...裝置區域214. . . Device area
216...第一組I/O襯墊216. . . First set of I/O pads
218...連接桿218. . . Connecting rod
220...接合區220. . . Junction area
222...囊封物或模製材料222. . . Encapsulant or molding material
223...支撐桿223. . . Support rod
224...引線架面板224. . . Lead frame
226...晶粒安裝表面226. . . Die mounting surface
300...積體電路封裝300. . . Integrated circuit package
302...晶粒302. . . Grain
304...晶粒附著襯墊304. . . Die attach liner
306...接地接合線306. . . Ground wire
308...接合線308. . . Bonding wire
310...接地I/O襯墊310. . . Ground I/O pad
312...多條引線312. . . Multiple leads
314...引線架裝置區域314. . . Lead frame device area
316...I/O襯墊316. . . I/O pad
318...連接桿318. . . Connecting rod
320...接合區320. . . Junction area
322...囊封物或模製材料322. . . Encapsulant or molding material
324...支撐桿324. . . Support rod
326...晶粒安裝表面326. . . Die mounting surface
330...指狀部分330. . . Finger part
402...晶粒402. . . Grain
404...接地之晶粒附著襯墊404. . . Grounded die attach pad
406...接合線406. . . Bonding wire
410...接地I/O襯墊410. . . Ground I/O pad
426...晶粒安裝表面426. . . Die mounting surface
432...線接合凸塊432. . . Wire bonding bump
434...針接合434. . . Needle joint
442...初始凸塊442. . . Initial bump
446...第二焊球接合446. . . Second solder ball bonding
512...引線512. . . lead
514...裝置區域514. . . Device area
518...連接桿518. . . Connecting rod
524...引線架條帶524. . . Lead frame strip
528...陣列528. . . Array
h1...距離h 1 . . . distance
h2...距離h 2 . . . distance
圖1A說明一先前技術積體電路封裝之俯視平面圖,其中晶粒上之接地接合襯墊向下接合至一接地之晶粒附著襯墊。1A illustrates a top plan view of a prior art integrated circuit package in which a ground bond pad on a die is bonded down to a grounded die attach pad.
圖1B說明沿剖面A-A截取的圖1A中所展示之封裝之側視橫截面圖。FIG. 1B illustrates a side cross-sectional view of the package shown in FIG. 1A taken along section A-A.
圖2A說明根據本發明之一具體實例的一引線架裝置區域之俯視平面圖,該引線架裝置區域具有在連接桿上之放大接合區。2A illustrates a top plan view of a leadframe device region having an enlarged landing area on a connecting rod in accordance with an embodiment of the present invention.
圖2B說明根據本發明之一具體實例的積體電路封裝之俯視平面圖,該積體電路封裝包括附著至圖2A之引線架裝置區域之晶粒,其中該晶粒電耦接至連接桿之放大接合區。2B illustrates a top plan view of an integrated circuit package including a die attached to the leadframe device region of FIG. 2A, wherein the die is electrically coupled to the connecting rod for amplification, in accordance with an embodiment of the present invention. Junction area.
圖2C說明根據本發明之一具體實例的圖2B之具體實例的沿剖面B-B截取之側視橫截面圖,其展示電耦接至連接桿之升高接合區之接地接合線。2C illustrates a side cross-sectional view taken along section B-B of the embodiment of FIG. 2B showing a ground bond wire electrically coupled to the raised land of the tie bar, in accordance with an embodiment of the present invention.
圖2D說明根據本發明之一具體實例的圖2B之具體實例的沿剖面C-C截取之側視橫截面圖,其展示電耦接至引線之接合線。2D illustrates a side cross-sectional view taken along section C-C of the embodiment of FIG. 2B, showing a bond wire electrically coupled to the leads, in accordance with an embodiment of the present invention.
圖3A說明根據本發明之另一具體實例的一引線架裝置區域之俯視平面圖,該引線架裝置區域具有在連接桿上之放大接合區。3A illustrates a top plan view of a leadframe device region having an enlarged landing region on a connecting rod in accordance with another embodiment of the present invention.
圖3B說明根據本發明之另一具體實例的積體電路封裝之俯視平面圖,該積體電路封裝包括附著至圖3A之引線架裝置區域之晶粒,其中該晶粒電耦接至連接桿之放大的接地之區。3B illustrates a top plan view of an integrated circuit package including a die attached to the leadframe device region of FIG. 3A, wherein the die is electrically coupled to the tie bar, in accordance with another embodiment of the present invention. Amplified grounded area.
圖3C說明根據本發明之一具體實例的沿剖面F-F截取的圖3B之積體電路封裝之側視橫截面圖,其中接地I/O襯墊耦接至連接桿之放大接合區。3C illustrates a side cross-sectional view of the integrated circuit package of FIG. 3B taken along section F-F, wherein the ground I/O pad is coupled to the amplifying junction of the connecting rod, in accordance with an embodiment of the present invention.
圖4A說明一積體電路封裝之側視橫截面圖,其中一接合線經由具有壓合於焊球上之楔之焊球接合(BSOB)直接耦接至晶粒附著襯墊。。4A illustrates a side cross-sectional view of an integrated circuit package in which a bond wire is directly coupled to the die attach pad via a solder ball bond (BSOB) having a wedge that is bonded to the solder ball. .
圖4B說明一積體電路封裝之側視橫截面圖,其中一接合線經由壓合於焊球上之反向焊球(RBSOB)直接耦接至晶粒附著襯墊。。4B illustrates a side cross-sectional view of an integrated circuit package in which a bond wire is directly coupled to the die attach pad via a reverse solder ball (RBSOB) that is bonded to the solder ball. .
圖5A至圖5C以俯視平面圖說明根據本發明之一具體實例的含有多個裝置區域514之引線架條帶524。5A-5C illustrate, in a top plan view, a lead frame strip 524 having a plurality of device regions 514 in accordance with an embodiment of the present invention.
304...晶粒附著襯墊304. . . Die attach liner
312...多條引線312. . . Multiple leads
314...引線架裝置區域314. . . Lead frame device area
318...連接桿318. . . Connecting rod
320...接合區320. . . Junction area
324...支撐桿324. . . Support rod
330...指狀部分330. . . Finger part
Claims (12)
Applications Claiming Priority (1)
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| US12/581,609 US8093707B2 (en) | 2009-10-19 | 2009-10-19 | Leadframe packages having enhanced ground-bond reliability |
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| TW201125092A TW201125092A (en) | 2011-07-16 |
| TWI515855B true TWI515855B (en) | 2016-01-01 |
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| JP (1) | JP2013508974A (en) |
| CN (1) | CN102576698A (en) |
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| US20110115063A1 (en) * | 2009-11-18 | 2011-05-19 | Entropic Communications, Inc. | Integrated Circuit Packaging with Split Paddle |
| US20110140253A1 (en) * | 2009-12-14 | 2011-06-16 | National Semiconductor Corporation | Dap ground bond enhancement |
| US9337240B1 (en) * | 2010-06-18 | 2016-05-10 | Altera Corporation | Integrated circuit package with a universal lead frame |
| TWI489607B (en) * | 2010-11-23 | 2015-06-21 | 登豐微電子股份有限公司 | Package structure |
| CN102800765A (en) * | 2012-03-21 | 2012-11-28 | 深圳雷曼光电科技股份有限公司 | Light emitting diode (LED) packaging structure and packaging process for same |
| US9147656B1 (en) * | 2014-07-11 | 2015-09-29 | Freescale Semicondutor, Inc. | Semiconductor device with improved shielding |
| US9922904B2 (en) | 2015-05-26 | 2018-03-20 | Infineon Technologies Ag | Semiconductor device including lead frames with downset |
| US10249556B1 (en) * | 2018-03-06 | 2019-04-02 | Nxp B.V. | Lead frame with partially-etched connecting bar |
| US20190287918A1 (en) * | 2018-03-13 | 2019-09-19 | Texas Instruments Incorporated | Integrated circuit (ic) packages with shields and methods of producing the same |
| CN109192715B (en) * | 2018-09-20 | 2024-03-22 | 江苏长电科技股份有限公司 | Lead frame structure, packaging structure and manufacturing method thereof |
| US20240162121A1 (en) * | 2022-11-16 | 2024-05-16 | Texas Instruments Incorporated | Integrated circuit package with wire bond |
| WO2024166846A1 (en) * | 2023-02-08 | 2024-08-15 | ローム株式会社 | Semiconductor device |
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| US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
| JP3074264B2 (en) * | 1997-11-17 | 2000-08-07 | 富士通株式会社 | Semiconductor device and its manufacturing method, lead frame and its manufacturing method |
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| US6398556B1 (en) * | 1998-07-06 | 2002-06-04 | Chi Fai Ho | Inexpensive computer-aided learning methods and apparatus for learners |
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| US20110089556A1 (en) | 2011-04-21 |
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| WO2011049764A3 (en) | 2011-11-17 |
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