TWI514769B - Mixed-mode input buffer, method of operating input buffer and integrated circuit - Google Patents

Description

Mixed mode input buffer, method of operating input buffer, and integrated circuit

The present invention relates to input buffers, and more particularly to an input buffer having a mixed reference voltage.

Generally, the input buffer in the integrated circuit receives an input signal from an external signal source, and generates an output signal based on the input signal, and the output signal is used in the integrated circuit. The single-ended input circuit has a first input signal and a reference voltage. When the first input signal exceeds the reference voltage, the output of the buffer changes (from high potential to low potential or low potential). Turn into high potential). Since the reference voltage is generated externally, it may be interfered by many noises or experienced many levels of drift. Under these conditions, the output signal of the buffer may be converted incorrectly.

Since the switching point of the input buffer is closely related to the reference voltage signal, changes in the reference voltage signal may cause the input buffer to switch at the wrong time point - either too early or too late, or even Outside of the time range of a timed switch window. Timing problems may cause erroneous data to be transmitted in the integrated circuit, or cause a metastable state in the integrated circuit. In the metastable state, the output signal of the buffer will oscillate and be electrically connected to The signal of the input buffer also oscillates.

In order to solve the above drawbacks and other problems, the present invention discloses a mixed mode input buffer having a lower sensitivity, so that a reference voltage can be used to provide a more accurate conversion mode.

According to a first embodiment of the present invention, a mixed mode input buffer is disclosed, comprising an input transistor, a first reference transistor and a second reference transistor. The input transistor has at least one gate terminal, wherein the gate terminal of the input transistor is connected to an external input signal generated by an external one. The first reference transistor has at least one gate terminal, wherein the gate terminal of the first reference transistor is connected to an externally generated external reference voltage signal. The second reference transistor has at least one gate terminal, wherein the gate terminal of the second reference transistor is connected to an external reference voltage signal generated by an external one.

According to a second embodiment of the present invention, a method for operating an input buffer includes: receiving a first input signal from a first external signal source, the first external signal source being in a product Outside the body circuit, the input buffer is located inside the integrated circuit; a second external signal source receives a first reference voltage for transmission to the input buffer, and the first external signal source is located at External to the integrated circuit; receiving a second reference voltage from a first internal signal source, the first internal signal source being internal to the integrated circuit; and based at least in part on the first input signal, the first A reference voltage and the second reference voltage generate at least one output signal.

According to a third embodiment of the present invention, an integrated circuit includes a first input pad, a second input pad, an input buffer, and a third conductor. The first input pad is coupled to a first conductor. The second input pad is coupled to a second conductor. The input buffer includes at least three inputs and at least one output, the at least three inputs include a first buffer input, a second buffer input, and a third buffer input, the first guide The system is coupled to the first buffer input, and the second conductive system is coupled to the second buffer input. The third conductor is configured to connect the third buffer input terminal to a first internal reference voltage generating circuit located on the integrated circuit.

According to a fourth embodiment of the present invention, a hybrid mode input buffer capable of reducing sensitivity to an externally generated reference voltage is disclosed, including a first coupling between a first load and a ground point. Input, the first input is an externally generated reference voltage; a second input coupled between a second load and a ground point for generating an output; and coupled to the first input in parallel a third input, the third input is an internally generated reference voltage; wherein when the second input exceeds a transition point, the output switches from a high level to a low level (or from a low level to a high level) And the conversion point is an average of the first input and the third input generated according to the relative sizes of the first input and the third input.

According to a fifth embodiment of the present invention, a mixed mode input buffer system having a dynamic switching point is disclosed, comprising: an input buffer for receiving an input and generating an output according to at least two reference voltages; An input pad coupled to the input buffer for generating the input to the input pad; a reference voltage pad coupled to the input buffer for generating an external reference voltage to the input pad; and a buffer And the output is coupled to the output for generating an internal reference voltage to be returned to the input buffer; wherein when the input exceeds a transition point, the output is switched from a high level to a low level (or from a low level to a high level) Potential), and the transition point is the average of the external reference voltage and the internal reference voltage.

The following description of the present invention is set forth with reference to the accompanying drawings, which illustrate a particular embodiment of the invention. The details of the embodiments are to be understood as being readily understood by those skilled in the art, and the disclosed embodiments may be modified without departing from the spirit and scope of the invention. It is to be understood that the following embodiments are not intended to limit the scope of the invention.

The mixed mode input buffer of the present invention applies two or more reference voltages to select an appropriate switching point to the input buffer, and the switching point can be switched to the two or more reference voltages as the case may be. In order to achieve better results, in some embodiments, one of the reference voltages is averaged for comparison with an input signal, and therefore any noise in the reference voltages is averaged. .

FIG. 1 is a schematic diagram showing a mixed mode input buffer 100 having a passive load in a first embodiment of the present invention. In the embodiment shown in FIG. 1, the input buffer 100 includes four N-type field effect transistors (FETs) M1, M2, M3, and M4. For the sake of convenience, the transistors M1~M4 only show one gate extreme, one extreme and one source extreme, and the transistors M1~M4 may also include other connection ends (such as the connection end of the substrate). Those skilled in the art should readily understand that a graphic used in a transistor to indicate that the connection is "source extreme" or "deuterium extreme" can be any choice, and is therefore indicated in the subsequent paragraphs. The "source extreme" connection can also be marked as "汲 extreme" and vice versa.

As shown in FIG. 1, an input signal Input is coupled to the gate terminal of the transistor M1, a first reference voltage VR1 is coupled to the gate terminal of the transistor M2, and a second reference voltage VR2 is coupled to the gate electrode. The gate of the crystal M3 is extreme. The source terminals of the transistors M1, M2 and M3 are both connected to a first common node 121. In addition, the NMOS terminal of the transistor M4 is coupled to the first common node 121, and the source terminal of the transistor M4 is coupled to a ground point (eg, a digital ground, an analog ground point). ), a chassis ground or an earth ground. A bias generator 150 is coupled to the gate terminal G _{M4 of the} transistor M4 via a bias signal line.

The NMOS terminals of the transistors M2 and M3 are coupled to a second common node 135. Therefore, the transistors M2 and M3 are coupled in parallel with each other between the first common node 121 and the second common node 135. A reference voltage network is formed which is used to set the transition point of the output signal of the input buffer 100. The details of this reference voltage network are described in detail in subsequent paragraphs.

The input buffer 100 shown in FIG. 1 further includes a first resistor 164 and a second resistor 166. The first resistor 164 is coupled between a first voltage source 160 and a drain terminal of the transistor M1, and the second resistor 166 is coupled between the second voltage source 162 and the second common node 135. For example, each of the first resistor 164 and the second resistor 166 may represent an individual circuit component or may represent a resistor contained within a conductor or transmission line.

The input buffer 100 generates a first output signal OutF and a second output signal based on the received input signal Input (which is an externally generated signal, such as a data signal or a control signal). Out. In general, the second output signal Out represents a scaled version of the input signal Input, and the first output signal OutF represents an inverse scaled version of the input signal Input. Therefore, the first output signal OutF and the second output signal Out can form a differential signal pair for transmitting the input signal Input to other parts of an integrated circuit.

In FIG. 1, the reference voltage network including transistors M2, M3 can be designed to change the switching points of the first and second output signals OutF and Out of the input buffer 100. In some embodiments, the driving capabilities of the transistors M2, M3 and the gate (channel) width may determine the manner in which the transistors M2, M3 affect the first and second output signals OutF and Out. For example, if the gate width of the transistor M2 is about twice the gate width of the transistor M3, the transistor M2 may have about twice the driving ability of the transistor M3, and therefore, the transistor M2 determines these The conversion point of the output signal has a large influence.

In some embodiments, the sum of the gate widths of the transistors M2 and M3 is designed to match the gate width of the transistor M1 (and therefore the driving capability), however, the gate widths of the transistors M2 and M3. The design does not need to work together. For example, when the first reference voltage VR1 is expected to be a stable value, the size of the transistor M2 can be selected to be 75% of the transistor M1, and the size of the transistor M3 can be selected to be 25% of the transistor M1, thus electricity The crystal M2 has a greater influence on the switching point than the transistor M3. In another example, the transistors M2 and M3 are symmetrical to each other (i.e., the gate widths of the transistors M2 and M3 are both 50% of the transistor M1). In addition, when the first reference voltage VR1 is expected to be a one-pole stable value or a very unstable value, the transistors M2 and M3 can be ignored, respectively.

In addition, if a transistor is operated in a triode region (for a field effect transistor), the driving capability of the transistor can be adjusted by changing the signal of its gate. When a transistor operates in a three-pole region, it can be used as a variable current limiter. Although FIG. 1 only shows a general field effect transistor, other switching elements such as a bipolar junction transistor operating in a saturation region are generally available to those skilled in the art. BJT) or other suitable transistors may also be suitable for use in the application of the present invention.

Taking the operation of the input buffer 100 shown in FIG. 1 as an example, in some embodiments, the first reference voltage VR1 is a ground potential and the second reference voltage VR2 is 0.5V. Assuming that the switching point is 50% between the first reference voltage VR1 and the second reference voltage VR2 (that is, the sum of the gate width of the transistor M2 and the gate width of M3 is equal to the gate width of the transistor M1, The transistor M2 and the transistor M3 have the same gate width. Therefore, when the input signal reaches 0.25V, the output signals are immediately converted. When the first reference voltage VR1 is 0.5V and the second reference voltage VR2 is a ground potential, the above description is also true. On the other hand, if the first reference voltage VR1 and the second reference voltage VR2 are designed to have the same potential (for example, also 0.5V), the switching point will be 0.5V, and the input buffer 100 will be Works like a conventional single-ended input buffer.

The first reference voltage VR1 and the second reference voltage VR2 can be generated in many different ways. In some embodiments, the first reference voltage VR1 is generated externally, and the second reference voltage VR2 is a reference voltage generated by the inside of the chip. Such a setting can not only reduce the noise in the first reference voltage VR1. The first reference voltage VR1 and the second reference voltage VR2 are also allowed to be easily coupled together to have the same potential. Therefore, such a circuit design can also operate as a conventional single-ended input buffer when necessary. .

Figure 1 illustrates an example of a mixed mode input buffer 100 with passive loading. In this example, the reference voltage network can be designed to mix 50% of the first reference voltage VR1 and the second reference voltage VR2, respectively. However, as mentioned earlier, passive load designs can also be used to mix different ratios of reference voltages. For example, the first reference voltage VR1 may include 75% of the passive load, and the second reference voltage VR2 may include 25% of the passive load.

FIG. 2 is a schematic diagram showing a mixed mode input buffer 200 in the second embodiment of the present invention. In the embodiment of Figure 2, the input buffer 200 has a basic operational transconductance amplifier (OTA). The input buffer 200 has a similar connection design to the input buffer 100 shown in FIG. 1, however, the resistors 164 and 166 are replaced by internal loads N1 and N2. In this embodiment, the internal loads N1 and N2 are respectively It is two P-type field effect transistors. In some embodiments, the P-type field effect transistors N1 and N2 are designed such that the second reference voltage VR2 includes 25% of the sum of the reference voltages.

FIG. 3 is a schematic diagram showing one of the mixed mode input buffers 300 in the third embodiment of the present invention. In the design of the input buffer 300, it has an active load. A bias generator 350 supplies a bias signal BiasN to the gate terminal of the transistor M4 and supplies a bias signal BiasP to the loads N1 and N2. In some embodiments, transistors M2 and M3 will be designed such that the second reference voltage VR2 provides 25% of the sum of the reference voltages.

FIG. 4 is a schematic diagram showing a mixed mode input buffer 400 in the fourth embodiment of the present invention. In the embodiment illustrated in FIG. 4, the input buffer 400 is designed to have a basic operational transconductance amplifier having a self-generated bias voltage. Specifically, the internal loads N1 and N2 of the input buffer 400 are designed according to the basic operational transduction amplifier architecture shown in FIG. 2, and the difference between FIG. 2 and FIG. 4 is: FIG. The bias signal BiasN supplied to the gate terminal G _M4 of the transistor M4 is generated inside the input buffer 400. Likewise, in some embodiments, transistors M2 and M3 will be designed such that the second reference voltage VR2 provides 25% of the sum of the reference voltages.

FIG. 5 is a schematic diagram showing a mixed mode input buffer 500 having a plurality of reference voltages in a fifth embodiment of the present invention. In some embodiments, the first reference voltage VR1 is an external reference voltage signal, and the reference voltage signals other than the first reference voltage VR1 are internally generated. In some embodiments, other reference voltage signals may be generated internally and/or externally.

The input buffer 500 includes a plurality of reference voltage transistors M2, M3, ..., MN connected in parallel with each other, and the gate size of each reference voltage transistor is designed according to requirements for distributing each reference voltage transistor pair. The influence weight of the conversion point, wherein the conversion point can be set according to a weighted combination (or weighted average) of the sizes of the reference voltage transistors M2, M3, ..., MN. The input buffer 500 also includes a first normal load 564 and a second normal load 566, and the first normal load 564 and the second normal load 566 respectively contain one or more passive or active electronic components.

FIG. 6 is a schematic diagram showing a hybrid mode input buffer system 600 applying a feedback mechanism in an embodiment of the present invention. In the example of FIG. 6, input buffer 600 includes an input buffer 610 for receiving an input signal Input from an input pad 605 and from a voltage reference pad 615. A first reference voltage signal VR1.

When the input buffer 610 is in operation, the input buffer 610 generates an output signal Output, and the output signal Output is used as an input to the second buffer 620. In addition, the second buffer 620 generates an output signal. VR2 is fed back and forth to input buffer 610 as an internally generated reference voltage. Such a feedback mechanism can cause the input buffer 610 to dynamically adjust its transition point in accordance with the initial conversion speed of the input buffer 610. The negative feedback mechanism will slow down the operation speed of the input buffer 610. Therefore, the buffer 610 will perform the conversion after the conversion point. However, the positive feedback will increase the operation speed of the input buffer 610, so that the input buffer 610 will The conversion takes place before the transition point.

The input buffer 610 can be calibrated to different needs by utilizing a hysteresis effect, i.e., applying a positive feedback or negative feedback mechanism. For example, the hysteresis effect can be set via parameters of one or more circuit elements, such as the individual transistor gate widths contained in input buffer 610. Further, the moving direction of the switching point can also be set by changing the voltage input fed to the input buffer 610 (refer to FIGS. 7 to 9). Therefore, by adding a feedback mechanism, the operational characteristics of the input buffer 610 can be more conveniently adjusted in response to changes in the output.

Those having ordinary skill in the art should understand that the embodiments of Figures 1 through 4 (or other embodiments) can be applied to generate a plurality of reference voltage signals (as shown in Figure 5), or can be matched. A feedback mechanism works (as shown in Figure 6).

As described above, FIGS. 7-9 illustrate schematic diagrams of transition points of different mixed mode input buffers in various embodiments. For example, Figure 7 illustrates four transition point diagrams of four different embodiments of the input buffer in operation, wherein the first reference voltage VR1 is set to a relatively low potential. The first drawing in Fig. 7 shows the switching point of an input buffer without the second reference voltage VR2, and the second figure shows that when the second reference voltage VR2 contains the sum of the reference voltages of 25% The conversion point of an input buffer, the third figure shows the conversion point of an input buffer when the second reference voltage VR2 contains 50% of the sum of the reference voltages. Finally, the fourth figure shows that there is no A conversion point of an input buffer of reference voltage VR1.

It is worth noting that the conversion point changes with a different mixing ratio between the first reference voltage VR1 and the second reference voltage VR2 (for example, by adjusting the gate widths of the transistors M2 and M3 to achieve different ratios), Therefore, the transition point is determined by a weighted combination (or weighted average) between the transistors in the reference voltage network.

Compared to Fig. 7, Fig. 8 shows four schematic diagrams of switching points similar to each other, wherein the first reference voltage VR1 is set to a medium potential. Figure 9 also shows four schematic diagrams of switching points similar to each other, wherein the first reference voltage VR1 is set to a relatively high potential. It is worth noting that in Figures 7 to 9, the fourth drawing is kept in the same position, because the fourth drawing in Figures 7 to 9 represents an input buffer. The switching point does not have the composition of the first reference voltage VR1.

In summary, the aforementioned hybrid mode input buffer has a number of distinct advantages over prior conventional input buffers. For example, the mixed mode input buffer reduces the sensitivity to an externally generated reference voltage by mixing the internally generated reference voltage with an externally generated reference voltage, and this mixing effect can maintain the externally generated reference voltage and In the case where the outputs of the mixed mode input buffers are tracked to each other, the sensitivity of the mixed mode input buffer is reduced. In addition, in some embodiments, the mixed mode input buffer can also generate a dynamic switching point, and can further apply the output of the buffer as an internally generated reference voltage for calibration, and this feedback mechanism is very advantageous. The conversion point is dynamically calibrated at the input buffer.

Although the above-described mixed mode input buffer is illustrated by some preferred embodiments, other embodiments that are implemented by the invention disclosed in this specification include those of ordinary skill in the art. Embodiments containing only some of the features and advantages of the present invention are still within the scope of the present invention. Furthermore, embodiments that are designed and implemented using the concept of a mixed mode input buffer, including examples of stylizing and optimizing the programmable resistance, are provided without departing from the spirit of the invention. It is within the scope of the invention.

In the above embodiment, the integrated circuit may be a monolithic chip, the input buffer may be connected to a memory section of the integrated circuit, and the memory area may include a dynamic random access. Dynamic random access memory (DRAM).

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300, 500, 610. . . Input buffer

121. . . First common node

135. . . Second common node

150, 250, 350. . . Bias generator

160. . . First voltage source

162. . . Second voltage source

164. . . First resistance

166. . . Second resistance

564. . . First ordinary load

566. . . Second ordinary load

600. . . Input buffer system

605. . . Input pad

615. . . Reference voltage pad

M1, M2, M3, ..., MN, N1, N2. . . Transistor

VR1. . . First reference voltage

VR2. . . Second reference voltage

Input. . . Input signal

OutF. . . First output signal

Out. . . Second output signal

BiasN, BiasP. . . Bias signal

G _m4 . . . Gate extreme

Fig. 1 is a schematic view showing a mixed mode input buffer having a passive load in the first embodiment of the present invention.

Figure 2 is a schematic diagram showing a mixed mode input buffer in a second embodiment of the present invention.

Figure 3 is a diagram showing the mixed mode input buffer in the third embodiment of the present invention.

Figure 4 is a schematic diagram showing a mixed mode input buffer in a fourth embodiment of the present invention.

FIG. 5 is a schematic diagram showing a mixed mode input buffer having a plurality of reference voltages in a fifth embodiment of the present invention.

FIG. 6 is a schematic diagram showing a mixed mode input buffer system to which a feedback mechanism is applied in an embodiment of the present invention.

7 to 9 illustrate an input buffer having only one external reference voltage for each embodiment of the mixed mode input buffer, each mixing a first reference voltage and a second reference voltage of 50%. An input buffer, a switching point diagram of an input buffer that respectively mixes a first reference voltage with a second reference voltage of 75:25% and an input buffer that has only one internal reference voltage.

500. . . Input buffer

564. . . First ordinary load

566. . . Second ordinary load

M1, M2, M3, ..., MN. . . Transistor

VR1. . . First reference voltage

VR2. . . Second reference voltage

Input. . . Input signal

OutF. . . First output signal

Out. . . Second output signal

Claims (8)

A mixed mode input buffer includes: an input transistor having at least one gate terminal, wherein the gate terminal of the input transistor is connected to an external input signal generated by an external; a first reference transistor having at least one gate terminal, wherein the gate terminal of the first reference transistor is connected to an externally generated external reference voltage signal; and a second reference transistor having at least one gate terminal, The gate of the second reference transistor is connected to an internally generated internal reference voltage signal; wherein a first terminal of the first reference transistor is connected to a terminal of the second reference transistor, the first The sum of one gate width of the reference transistor and one gate width of the second reference transistor is equal to one gate width of the input transistor, and at least one terminal of the input transistor is used for output An output signal corresponding to the external input signal, wherein the output signal is switched between two different voltage levels and serves as an output of the input buffer. The hybrid mode input buffer of claim 1, wherein one end of the input transistor, one end of the first reference transistor, and one end of a second reference transistor are connected to a first common node. The hybrid mode input buffer of claim 1, further comprising: a first load connecting a first voltage terminal to one end of the input transistor; and a second load to a second voltage The end is connected to a second common node, the second common node is connected to one end of the first reference transistor and the second reference transistor One end of the body; and a third load connected to a third voltage terminal; wherein the first and second voltage terminals are maintained at a positive voltage with respect to the third voltage terminal; and the first voltage terminal and the second voltage The end systems are maintained at the same voltage. The hybrid mode input buffer of claim 3, wherein the first voltage terminal and the second voltage terminal are coupled to each other. The hybrid mode input buffer of claim 3, wherein the third load is a bias transistor. The hybrid mode input buffer of claim 5, wherein the bias transistor system is coupled to an externally generated external bias signal. The hybrid mode input buffer of claim 5, wherein the bias transistor system is coupled to an internally generated internal bias signal. The mixed mode input buffer of claim 7 further outputs at least one output signal, wherein the internally generated internal bias signal is generated at least in part due to the output signal.