TWI514547B - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an inductive component.

Many digital/analog components and circuits have been successfully used in semiconductor integrated circuits. The above components contain passive components such as resistors, capacitors or inductors. A typical semiconductor integrated circuit includes a germanium substrate. One or more dielectric layers are disposed on the substrate, and one or more metal layers are disposed in the dielectric layer. These metal layers can be formed into wafer built-in components by current semiconductor processing techniques, such as on-chip inductors.

The chip built-in inductor component is formed on the substrate, and the chip built-in inductor component comprises a metal layer and an interconnect structure. The metal layer is surrounded by a central region from the outside to the inside and embedded in the upper insulating layer above the substrate; and when it is closest to the central region, is then embedded in the upper insulating layer above the substrate. The interconnect structure includes an upper connection layer embedded in the upper insulation layer and a first conductive plug and a lower connection layer embedded in the lower insulation layer. The metal layer forms a current path through the first conductive plug and the upper and lower connection layers to electrically connect to the external or internal circuit of the wafer. The two ends of the metal layer are located on the outermost ring and are respectively connected to an extension portion, and the two extension portions are parallel to each other and can connect various circuit components. Furthermore, the above-mentioned chip built-in inductor component may further comprise a branch structure, and the branch junction The structure is connected to the innermost ring of the metal layer by a second conductive plug embedded in the lower insulating layer. In particular, if viewed from the top view of the built-in inductive component of the wafer, the extending direction of the branched structure will be perpendicular to the direction in which the two extensions at both ends of the metal layer extend.

The equivalent circuit formed by the two extensions and the branch structures of the above-mentioned chip built-in inductor element is a T-coil, and the circuit parameters provided include the first inductance value, the second inductance value and the coupling coefficient. The magnitude of the first inductance value and the second inductance value and the length of the wire (for example, the length of the wire between the one end of the outermost ring of the metal layer to the position where the innermost ring is connected to the branch structure has an inductance value, and the other end to the branch The length of the wire between the locations of the structures is proportional to another inductance value, and the first inductance value and the second inductance value also affect the magnitude of the coupling coefficient. The first inductance value, the second inductance value, and the coupling coefficient can usually be adjusted by changing the position of the innermost ring connecting branch structure in the metal layer.

However, since the position of the connection branch structure in the innermost layer of the metal layer is limited by the side width of the innermost layer of the metal layer, the structure of the conventional chip built-in inductance element is difficult to meet the requirements of various circuit designs. Furthermore, when the position of the branch structure is changed, the first inductance value, the second inductance value, and the coupling coefficient are simultaneously changed, so that adjustment of the circuit parameters of the built-in inductance component of the wafer is difficult.

Therefore, it is necessary to find a novel semiconductor device having an inductance element that can solve or ameliorate the above problems.

The embodiment of the invention provides a semiconductor device comprising a first insulating layer and a second insulating layer, which are sequentially disposed on a substrate, wherein the substrate has a central region. a first wire layer and a second wire layer are disposed in the first insulating layer and surround the central region, and respectively have a first end and a second end, wherein The second ends of the first wire layer and the second wire layer are coupled to each other. a first winding portion and a second winding portion are disposed in the second insulating layer and surround the central region, and respectively include a third wire layer and a fourth wire layer, the third wire layer and the fourth wire layer The fourth wire layer has a first end and a second end, respectively. a coupling portion is disposed in the first insulating layer and the second insulating layer between the first winding portion and the second winding portion, and includes a first pair of connecting layers to interlace the first end of the third wire layer Connecting to the first end of the first wire layer and the second wire layer. A second pair of connection layers alternately connects the third wire layer and the second end of the fourth wire layer. The first wire layer and the second wire layer and the third wire layer at least partially overlap.

The embodiment of the invention provides another semiconductor, comprising a first insulating layer and a second insulating layer, which are sequentially disposed on a substrate, wherein the substrate has a central region. A first winding portion and a second winding portion are disposed in the second insulating layer and surround the central region, and respectively include a first wire layer, a second wire layer and a third wire layer arranged from the inside to the outside And the first wire layer, the second wire layer and the third wire layer respectively have a first end and a second end, wherein the first ends of the first wire layer are coupled to each other. a coupling portion is disposed in the first insulating layer and the second insulating layer between the first winding portion and the second winding portion, and the coupling portion includes a first pair of connecting layers, and the first wire layer is alternately connected a second end of the second wire layer. A second pair of connection layers interleaves the first ends of the second wire layer and the third wire layer. Wherein the first wire layer and the adjacent second wire layer have a plurality of the same or different pitches, and at least one of the pitches is greater than a distance between the second wire layer and the adjacent third wire layer.

10‧‧‧ dotted line

100‧‧‧Base

200‧‧‧First insulation

201‧‧‧ third insulation layer

202‧‧‧Interconnection structure

203‧‧‧ Conductive layer

204, 515, 525, 715, 815‧‧‧ conductive plugs

210, 710, 810‧‧‧ first wire layer

211, 221, 331, 341, 351, 431, 441, 451, 711, 721, 731, 741, 811, 821, 831, 841 ‧ ‧ first end

212, 222, 332, 342, 352, 432, 442, 452, 712, 722, 732, 742, 812, 822, 832, 842‧‧‧ second end

220, 720, 820‧‧‧ second wire layer

250‧‧‧Second insulation

300, 700‧‧‧First winding department

330, 430, 730, 830‧‧‧ third wire layer

340, 440, 740, 840‧‧‧ fourth wire layer

350, 450‧‧‧ fifth wire layer

360, 460‧‧‧ sixth wire layer

400, 800‧‧‧second winding department

510, 910‧‧‧ first pair of connection layers

520, 920‧‧‧ second pair of connection layers

530, 930‧‧‧ third pair of connection layers

540‧‧‧ fourth pair of connection layers

511, 521, 531, 541, 911, 921, 931‧‧‧ upper jumper

512, 522, 532, 542, 912, 922, 932‧‧‧ lower jumper

610‧‧‧First Extension

620‧‧‧Second extension

630‧‧ Third extension

635‧‧‧Electrostatic protective components

A‧‧‧ central area

D1, D2‧‧‧ spacing

R1, R2, R3‧‧‧ adjustment range

Fig. 1A is a plan view showing a two-turn inductor element according to an embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view taken along line 1B-1B' in Fig. 1A.

Fig. 1C is a schematic cross-sectional view taken along line 1C-1C' in Fig. 1A.

2 is a plan view showing a three-turn inductor element according to an embodiment of the present invention.

Figure 3 is a plan view showing a four-turn inductor element according to an embodiment of the present invention.

Fig. 4A is a plan view showing a three-turn inductor element according to another embodiment of the present invention.

Fig. 4B is a schematic cross-sectional view taken along line 4B-4B' in Fig. 4A.

Figure 5 is a plan view showing a four-turn inductor element according to another embodiment of the present invention.

Figure 6 is a plan view showing a three-turn inductor element according to still another embodiment of the present invention.

Figure 7 is a plan view showing a four-turn inductor element according to still another embodiment of the present invention.

The making and using of the embodiments of the present invention are described below. However, it will be readily understood that the embodiments of the present invention are susceptible to many specific embodiments of the invention and can The specific embodiments disclosed are merely illustrative of The present invention is not intended to limit the scope of the invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.

Hereinafter, a semiconductor device having two turns of an inductance element according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1C. FIG. 1A is a plan view showing two turns of the inductor element, and FIG. 1B is a view showing two turns of the inductor element. A cross-sectional view taken along line 1B-1B' in FIG. 1A, and FIG. 1C is a cross-sectional view showing a two-turn inductor element along a line 1C-1C' in FIG. 1A.

The semiconductor device having two turns of the inductive component includes a substrate 100 having a central region A (as shown in FIG. 1A). A first insulating layer 200 and a second insulating layer 250 are sequentially disposed on the substrate 100. Substrate 100 includes a germanium substrate or other conventional semiconductor substrate. A variety of different components can be included in the substrate 100, such as transistors, resistors, and other conventional semiconductor components. Furthermore, the substrate 100 may also comprise other conductive layers (eg, copper, aluminum, or alloys thereof) as well as other insulating layers (eg, a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer). Here, in order to simplify the drawing, only one flat substrate is shown. Furthermore, the first insulating layer 200 and the second insulating layer 250 may be a single layer of a dielectric material (eg, a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer) or a multilayer dielectric structure.

A first wire layer 210 and a second wire layer 220 are disposed in the first insulating layer 200 and surround the central region A, and are respectively located on both sides of the broken line 10. In an embodiment, the first wire layer 210 and the second wire layer 220 are symmetrically arranged based on the dashed line 10. The first wire layer 210 has a first end 211 and a second end 212. The second wire layer 220 has a first end 221 and a second end 222, wherein the second end 212 and the second end of the first wire layer 210 The second end 222 of the wire layer 220 is disposed through The conductive layers 203 of the third insulating layer 201 are coupled to each other. The first wire layer 210 and the second wire layer 220 may be formed into a substantially circular, rectangular, hexagonal, octagonal or polygonal shape. Here, in order to simplify the drawing, a rectangle is taken as an example. Furthermore, the material of the first wire layer 210 and the second wire layer 220 may include copper, aluminum or an alloy thereof. In this embodiment, the first wire layer 210 and the second wire layer 220 have the same line width.

A first winding portion 300 and a second winding portion 400 are disposed in the second insulating layer 250 and surround the central region A, and are respectively located on both sides of the broken line 10. In the present embodiment, the first winding portion 300 includes a third wire layer 330 and a fourth wire layer 340 which are arranged from the inside to the outside. The second wire winding portion 400 includes a third wire layer 430 which is arranged from the inside to the outside. And a fourth wire layer 440. The third wire layer 330 has a first end 331 and a second end 332. The third wire layer 430 has a first end 431 and a second end 432. In an embodiment, the third wire layer 330 and the third wire layer 430 near the center area A are symmetrically arranged based on the dashed line 10. The fourth wire layer 340 has a first end 341 and a second end 342. The fourth wire layer 440 has a first end 441 and a second end 442. The third wire layers 330 and 430 or the fourth wire layers 340 and 440 may each be formed into a generally circular, rectangular, hexagonal, octagonal or polygonal shape. Here, in order to simplify the drawing, a rectangle is taken as an example. Furthermore, the materials of the third wire layers 330 and 430 and the fourth wire layers 340 and 440 may be the same as the materials of the first wire layer 210 and the second wire layer 220. In this embodiment, the third wire layers 330 and 430 and the fourth wire layers 340 and 440 may have the same line width, and the line width is the same as the line width of the first wire layer 210 and the second wire layer 220.

A coupling portion is disposed in the first insulating layer 200 and the second insulating layer 250 between the first winding portion 300 and the second winding portion 400, and the coupling portion includes a first portion A pair of connection layers 510 and a second pair of connection layers 520. The first pair of connection layers 510 includes an upper cross-connect 511 disposed in the second insulating layer 250 and a lower cross-over layer 512 disposed in the first insulating layer 200. The second pair of connection layers 520 includes an upper jumper 521 layer disposed in the second insulating layer 250 and a lower jumper layer 522 disposed in the first insulating layer 200.

The upper crossover layer 511 of the first pair of connection layers 510 connects the first end 431 of the third wire layer 430 of the second winding portion 400 to the first end 211 of the first wire layer 210, wherein the upper jumper layer 511 is connected The first end 211 is provided with at least one conductive plug 515 (shown in FIG. 1C ) to electrically connect the first conductive layer 210 disposed in the first insulating layer 200 . It should be noted that in the drawings of the present embodiment, only one conductive plug 515 is shown, but is not intended to limit the present invention. In most embodiments, a plurality of conductive plugs 515 are disposed on a side of the upper jumper layer 511 that connects the first ends 211. Furthermore, the lower crossover layer 512 of the first pair of connection layers 510 connects the first end 331 of the third wire layer 330 of the first winding portion 300 to the first end 221 of the second wire layer 220, wherein the lower bridge One side of the layer 512 connected to the first end 331 is provided with at least one conductive plug (not shown) for electrically connecting the third wire layer 330 disposed in the second insulating layer 250. Therefore, the first pair of connection layers 510 alternately connect the first ends 331 and 431 of the third wire layers 330 and 430 of the first winding portion 300 and the second winding portion 400 to the first end 211 of the first wire layer 210. And a first end 221 of the second wire layer 220.

The upper end 521 of the second pair of connection layers 520 connects the second end 332 of the third wire layer 330 of the first winding portion 300 to the second end 442 of the fourth wire layer 440 of the second winding portion 400. The lower crossover layer 522 of the second pair of connection layers 520 connects the second end 432 of the third wire layer 430 of the second winding portion 400 to the first winding The second end 342 of the fourth wire layer 340 of the portion 300, wherein the two ends of the lower bridging layer 522 are respectively provided with at least one conductive plug (for example, the conductive plug 525 shown in FIG. 1B) for respectively The third wire layer 430 of the second winding portion 400 disposed in the second insulating layer 250 and the fourth wire layer 340 of the first winding portion 300 are connected. Therefore, the second pair of connection layers 520 are alternately connected to the second ends 332 and 432 of the third wiring layers 330 and 430 and the second ends 342 and 442 of the fourth wiring layers 340 and 440. It should be noted that in the drawings of the present embodiment, only one conductive plug 525 is shown, but is not intended to limit the present invention. In most embodiments, a side of the lower jumper layer 522 that connects the second end 342 is provided with a plurality of conductive plugs 525.

The semiconductor device having the inductive component further includes a first extension portion 610 and a second extension portion 620 disposed in the second insulation layer 250. In an embodiment, the first extending portion 610 and the second extending portion 620 are correspondingly connected to the first ends 341 and 441 of the fourth wire layers 340 and 440 of the first winding portion 300 and the second winding portion 400 and are mutually parallel. In other embodiments, the first extension 610 and the second extension 620 are not parallel to each other. The first ends 341 and 441 of the fourth wire layers 340 and 440 may be disposed on the same side of the broken line 10, or may be symmetrically disposed on both sides of the broken line 10, so that the first extending portion 610 and the second extending portion 620 are adjustable positions. The side widths of the fourth wire layers 340 and 440.

Furthermore, the semiconductor device having the inductive component further includes a third extension portion 630 disposed in the first insulating layer 200 and connected to the second wiring layer 220. In the present embodiment, the third extension 630 is similar to the branching structure as proposed in the prior art. In an embodiment, the extending direction of the first extending portion 610 is perpendicular to the extending direction of the third extending portion 630 , and the extending direction of the second extending portion 620 is perpendicular to the extending direction of the third extending portion 630 . In other embodiments If the first extending portion 610 and the second extending portion 620 are not parallel to each other, the extending direction of the third extending portion 630 is different from the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. A vertical. Of course, in still another embodiment, the extending direction of the third extending portion 630 is not perpendicular to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. In other embodiments, the third extension 630 disposed within the first insulating layer 200 can be connected to the first wire layer 210. In an embodiment, the third extension 630 can be coupled to an electrostatic discharge protection device 635. In the present embodiment, the ESD protection device 635 is disposed on a side close to the first extension portion 610 and the second extension portion 620, but is not intended to limit the present invention. In other embodiments, the ESD protection device 635 can be disposed on a side away from the first extension 610 and the second extension 620. The user can adjust the position of the ESD protection device 635 according to the wiring requirements. In addition, in the present embodiment, the position of the third extension portion 630 is close to the second pair of connection layers 520, but is not intended to limit the present invention. In other embodiments, the third extension portion 630 can be disposed in the adjustment range R1 according to different requirements.

In one embodiment, the first wire layer 210 and the second wire layer 220 may at least partially overlap the third wire layers 330 and 430 and extend along the third wire layers 330 and 430 or the fourth wire layers 340 and 440. The second ends 212 and 222 of the first wire layer 210 and the second wire layer 220 are coupled to each other and at least partially overlap the third wire layers 330 and 430 or the fourth wire layers 340 and 440. In one embodiment, the first wire layer 210 and the second wire layer 220 extend along the third wire layers 330 and 430 and overlap the third wire layers 330 and 430. In another embodiment, the first wire layer 210 and the second wire layer 220 extend along the fourth wire layers 340 and 440 and overlap with the fourth wire layers 340 and 440, as shown in FIGS. 1A-1C. With the first wire layer 210 and the second wire layer 220 extending along the fourth wire layers 340 and 440, the effect of increasing the coupling coefficient is better. The second ends 212 and 222 of the first wire layer 210 and the second wire layer 220 are coupled to each other through the conductive layer 203 disposed on the third insulating layer 201 and the at least one pair of conductive plugs 204 on both sides of the conductive layer, such as Figure 1B shows.

In the process design, since the thickness of the first wire layer 210 and the second wire layer 220 (lower conductive layer) is generally smaller than the thicknesses of the third wire layers 330 and 430 and the fourth wire layers 340 and 440 (upper conductive layer), The semiconductor device with the inductive component of the present embodiment further includes a multilayer interconnect structure 202 including a dielectric layer and a conductive layer in the dielectric layer, as shown in FIGS. 1B and 1C. Show. The multilayer interconnect structure 202 is located between the first insulating layer 200 and the substrate 100, and overlaps with the first conductive layer 210 and the second conductive layer 220, and is connected to the first through at least two conductive plugs (not shown). The wire layer 210 and the second wire layer 220 maintain the quality of the inductive component.

In conventional in-chip inductor elements, the windings are typically placed in the same level and surround the central region. Furthermore, the first inductance value, the second inductance value, and the coupling coefficient are usually adjusted by changing the connection position of the innermost wire layer and the branch structure of the winding portion. However, since the position of the branch structure is limited by the side width of the innermost wire layer (for example, the width of one side in the rectangular wire layer), the structure of the conventional chip built-in inductor element is difficult to satisfy various circuit designs. Demand.

The first wire layer 210 and the second wire layer 220 of the embodiment of the present invention are disposed in the first insulating layer 200 and along the second insulating layer 250, as compared with the conventional in-line inductor element. Third wire layer 330 and 430 or The fourth wire layers 340 and 440 extend and at least partially overlap with the third wire layers 330 and 430 or the fourth wire layers 340 and 440, so that the coupling coefficient can be increased by overlapping. Furthermore, the length of the wire overlapping the first wire layer 210 and the second wire layer 220 and the fourth wire layer 340 and 440 is greater than the wire overlapping the first wire layer 210 and the second wire layer 220 and the third wire layer 330 and 430. The length, so the available inductance value and coupling coefficient are large. In this way, the first wire layer 210 and the second wire layer 220 may be selectively overlapped with the third wire layers 330 and 430 or the fourth wire layers 340 and 440 according to the required circuit design. Moreover, compared with the conventional built-in inductive component of the wafer, each conductive layer is sequentially arranged from the outside to the inside, and a plurality of pairs of connecting layers are combined to form a current path, and the present invention should be disposed inside. The first wire layer 210 and the second wire layer are modified to be outwardly disposed (ie, disposed outside the third wire layers 330 and 430 with respect to the central region A instead of the third wire layers 330 and 430), thus solving the original The position of the branching structure is limited by the problem of the width of the sides of the innermost wire layer. In other words, since the first wire layer 210 and the second wire layer 220 partially or completely overlap with the third wire layers 330 and 430 or the fourth wire layers 340 and 440, the adjustment range R1 of the position of the third extending portion 630 is increased. That is, the adjustment range of the first inductance value, the second inductance value, and the coupling coefficient can be increased, thereby improving the flexibility of the circuit design of the built-in inductance component of the wafer to obtain desired circuit characteristics. In addition, through the design of the inductor component of the present invention, when the inductor component is connected to other circuits, the bandwidth of use of other circuits can be increased.

Hereinafter, a semiconductor device having a three-turn inductor element according to another embodiment of the present invention will be described with reference to FIG. 2, wherein the same components as those in FIG. 1A are denoted by the same reference numerals and the description thereof will be omitted. In FIG. 2, the first winding portion 300 and the second winding portion 400 further include fifth wire layers 350 and 450, respectively, which are located at the fourth The outer sides of the wire layers 340 and 440 have first ends 351 and 451 and second ends 352 and 452. Similarly, the fifth wire layers 350 and 450 may have the same line width, and the line width is the same as the line width of the first wire layer 210 and the second wire layer 220, and the materials of the fifth wire layers 350 and 450 are outside. The type may be the same as the first wire layer 210 and the second wire layer 220.

Furthermore, in the embodiment, the coupling portion further includes a third pair of connection layers 530 including an upper bridging layer 531 disposed in the second insulating layer 250 and a lower portion disposed in the first insulating layer 200. Jumper layer 532. The upper crossover layer 531 of the third pair of connection layers 530 connects the first end 341 of the fourth wire layer 340 of the first winding portion 300 to the first end 451 of the fifth wire layer 450 of the second winding portion 400, The lower crossover layer 532 of the third pair of connection layers 530 connects the first end 441 of the fourth wire layer 440 of the second winding portion 400 to the first end 351 of the fifth wire layer 350 of the first winding portion 300, The two ends of the lower jumper layer 532 are respectively provided with at least one conductive plug (not shown) to electrically connect the fourth wire layer 440 and the fifth wire layer 350 disposed in the second insulating layer 250, respectively. Therefore, the third pair of connection layers 530 are alternately connected to the first ends 341 and 441 of the fourth wire layers 340 and 440 and the first ends 351 and 451 of the fifth wire layers 350 and 450.

In this embodiment, the first wire layer 210 and the second wire layer 220 may at least partially overlap the third wire layers 330 and 430, and along the third wire layers 330 and 430 and the fourth wire layers 340 and 440 or The fifth wire layers 350 and 450 extend such that the second ends 212 and 222 of the first wire layer 210 and the second wire layer 220 are coupled to each other, and to the third wire layers 330 and 430 and the fourth wire layers 340 and 440 or It is the fifth wire layers 350 and 450 that at least partially overlap. In the above plurality of embodiments, the first wire layer 210 and the second wire layer 220 are extended along the fifth wire layers 350 and 450. Stretching, the effect of increasing the coupling coefficient is better.

In the present embodiment, the first extending portion 610 and the second extending portion 620 are disposed in the second insulating layer 250 as shown in FIG. 1B or as shown in FIG. 1C. In an embodiment, the first extension portion 610 and the second extension portion 620 are correspondingly connected to the second ends 352 and 452 of the fifth wire layers 350 and 450 and are parallel to each other. In other embodiments, the first extension 610 and the second extension 620 are not parallel to each other. In an embodiment, the extending direction of the first extending portion 610 and the second extending portion 620 is perpendicular to the extending direction of the third extending portion 630. In other embodiments, if the first extending portion 610 and the second extending portion 620 are not parallel to each other, the extending direction of the third extending portion 630 is opposite to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. One of them is vertical. Of course, in still another embodiment, the extending direction of the third extending portion 630 is not perpendicular to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. In the present embodiment, the third extension portion 630 is located close to the first extension portion 610 and the second extension portion 620, but is not intended to limit the present invention. In other embodiments, the third extension portion 630 can be disposed in the adjustment range R2 according to different requirements. Furthermore, other odd-numbered symmetrical inductive elements have a structure similar to that of the inductive elements in FIG.

In a conventional in-chip inductor element, since the position of the branch structure is limited by the side width of the innermost wire layer (for example, the width of one side in the rectangular wire layer), the conventional wafer built-in The structure of the inductive component is difficult to meet the needs of various circuit designs.

The first wire layer 210 and the second wire layer 220 of the embodiment of the present invention are disposed in the first insulating layer 200 and along the second insulating layer 250, as compared with the conventional in-line inductor element. Third wire layers 330 and 430, The fourth wire layers 340 and 440 or the fifth wire layers 350 and 450 extend and at least partially overlap the third wire layers 330 and 430, the fourth wire layers 340 and 440 or the fifth wire layers 350 and 450, thereby Overlap can increase the coupling coefficient. Moreover, the longer the length of the overlapped wires, the larger the obtained inductance value and the coupling coefficient, so that the first wire layer 210 and the second wire layer 220 and the third wire layer 330 can be selected according to the required circuit design. And 430, one of the fourth wire layers 340 and 440 and the fifth wire layers 350 and 450 overlap. Furthermore, in the present invention, the first wire layer 210 and the second wire layer 220, which should be disposed inside the third wire layers 330 and 430, are disposed outside the third wire layers 330 and 430. Since the first wire layer 210 and the second wire layer 220 partially or completely overlap with the third wire layers 330 and 430, the fourth wire layers 340 and 440 or the fifth wire layers 350 and 450, the third extension 630 is added. The adjustment range of the position is R2. That is, the adjustment range of the first inductance value, the second inductance value, and the coupling coefficient can be increased, thereby improving the flexibility of the circuit design of the built-in inductance component of the wafer to obtain desired circuit characteristics.

Hereinafter, a semiconductor device having a four-turn inductor element according to another embodiment of the present invention will be described with reference to FIG. 3, wherein the same components as those in FIG. 1A are denoted by the same reference numerals and the description thereof will be omitted. In FIG. 3, the first winding portion 300 and the second winding portion 400 further include sixth wire layers 360 and 460 respectively located outside the fifth wire layers 350 and 450 and having first ends 361 and 461 And second ends 362 and 462. Similarly, the sixth wire layers 360 and 460 may have the same line width, and the line width is the same as the line width of the first wire layer 210 and the second wire layer 220, and the materials of the sixth wire layers 360 and 460 are outside. The type may be the same as the first wire layer 210 and the second wire layer 220.

Furthermore, in this embodiment, the coupling portion further includes a fourth The connection layer 540 includes an upper bridging layer 541 disposed in the second insulating layer 250 and a lower bridging layer 542 disposed in the first insulating layer 200. The upper jumper layer 541 of the fourth pair of connection layers 540 connects the second end 352 of the fifth wire layer 350 of the first winding portion 300 to the second end 462 of the sixth wire layer 460 of the second winding portion 400, The lower crossover layer 542 of the fourth pair of connection layers 540 connects the second end 452 of the fifth wire layer 450 of the second winding portion 400 to the second end 362 of the sixth wire layer 360 of the first winding portion 300, The two ends of the lower jumper layer 542 are respectively provided with at least one conductive plug (not shown) to electrically connect the fifth wire layer 450 and the sixth wire layer 360 disposed in the second insulating layer 250 respectively. Accordingly, the fourth pair of connection layers 540 alternately connect the second ends 352 and 452 of the fifth wire layers 350 and 450 with the second ends 362 and 462 of the sixth wire layers 360 and 460.

In this embodiment, the first wire layer 210 and the second wire layer 220 may at least partially overlap the third wire layers 330 and 430, and along the third wire layers 330 and 430 and the fourth wire layers 340 and 440, The five wire layers 350 and 450 or the sixth wire layers 360 and 460 extend such that the second ends 212 and 222 of the first wire layer 210 and the second wire layer 220 are coupled to each other, and to the third wire layers 330 and 430, The fourth wire layers 340 and 440, the fifth wire layers 350 and 450, or the sixth wire layers 360 and 460 at least partially overlap. In the above plurality of embodiments, the effect of increasing the coupling coefficient along the sixth wire layers 360 and 460 by the first wire layer 210 and the second wire layer 220 is preferred.

In the present embodiment, the first extending portion 610 and the second extending portion 620 are disposed in the second insulating layer 250 as shown in FIG. 1B or as shown in FIG. 1C. In an embodiment, the first extension portion 610 and the second extension portion 620 are correspondingly connected to the first ends 361 and 461 of the sixth wire layers 360 and 460 and are parallel to each other. In other embodiments, The first extension portion 610 and the second extension portion 620 are not parallel to each other. In an embodiment, the extending direction of the first extending portion 610 and the second extending portion 620 is perpendicular to the extending direction of the third extending portion 630. In other embodiments, if the first extending portion 610 and the second extending portion 620 are not parallel to each other, the extending direction of the third extending portion 630 is opposite to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. One of them is vertical. Of course, in still another embodiment, the extending direction of the third extending portion 630 is not perpendicular to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. In the present embodiment, the third extension 630 is located close to the fourth pair of connection layers 540, but is not intended to limit the invention. In other embodiments, the third extension portion 630 can be disposed in the adjustment range R3 according to different requirements. Furthermore, other even-numbered symmetrical inductance elements have a structure similar to that of the inductance elements of FIG.

In a conventional in-chip inductor element, since the position of the branch structure is limited by the side width of the innermost wire layer (for example, the width of one side in the rectangular wire layer), the conventional wafer built-in The structure of the inductive component is difficult to meet the needs of various circuit designs.

The first wire layer 210 and the second wire layer 220 of the embodiment of the present invention are disposed on the first insulating layer 200 and along the second insulating layer 250. The three wire layers 330 and 430, the fourth wire layers 340 and 440, the fifth wire layers 350 and 450 or the sixth wire layers 360 and 460 extend, and the third wire layers 330 and 430 and the fourth wire layers 340 and 440 The fifth wire layers 350 and 450 or the sixth wire layers 360 and 460 at least partially overlap, so that the coupling coefficient can be increased by overlapping. Furthermore, since the length of the overlapping wires is longer, the obtained inductance value and coupling coefficient are larger, so that the required The circuit design selects the first wire layer 210 and the second wire layer 220 and the third wire layers 330 and 430, the fourth wire layers 340 and 440, the fifth wire layers 350 and 450, and the sixth wire layers 360 and 460. One overlaps. Furthermore, in the present invention, the first wire layer 210 and the second wire layer 220, which should be disposed inside the third wire layers 330 and 430, are disposed outside the third wire layers 330 and 430. Since the first wire layer 210 and the second wire layer 220 partially or completely overlap with the third wire layers 330 and 430, the fourth wire layers 340 and 440, the fifth wire layers 350 and 450 or the sixth wire layers 360 and 460, The adjustment range R3 of the position of the third extension portion 630 is increased. That is, the adjustment range of the first inductance value, the second inductance value, and the coupling coefficient can be increased, thereby improving the flexibility of the circuit design of the built-in inductance component of the wafer to obtain desired circuit characteristics.

In addition, those skilled in the art can easily understand that the above embodiments of the present invention can be applied to other symmetric inductor elements of more than four turns, and have the same advantages.

Hereinafter, a semiconductor device having a three-turn inductor element according to another embodiment of the present invention will be described with reference to FIGS. 4A, 4B and 6 , wherein FIG. 4A is a plan view showing a three-turn inductor element, and FIG. 4B is a diagram showing three A schematic cross-sectional view of the 匝 inductor element along the line 4B-4B' in FIG. 4A, and FIG. 6 is a plan view showing a semiconductor device having a three-turn inductor element according to still another embodiment of the present invention.

A semiconductor device having a three-turn inductor element includes a substrate 100 having a central region A (as shown in FIG. 4A). A first insulating layer 200 and a second insulating layer 250 are sequentially disposed on the substrate 100. As shown in Figure 4B. Substrate 100 includes a germanium substrate or other conventional semiconductor substrate. Substrate 100 A variety of different components can be included, such as transistors, resistors, and other conventional semiconductor components. Furthermore, the substrate 100 may also comprise other conductive layers (eg, copper, aluminum, or alloys thereof) as well as other insulating layers (eg, a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer). Here, in order to simplify the drawing, only one flat substrate is shown. Furthermore, the first insulating layer 200 and the second insulating layer 250 may be a single layer of a dielectric material (eg, a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer) or a multilayer dielectric structure.

A first winding portion 700 and a second winding portion 800 are disposed in the second insulating layer 250 and surround the central region A, and are respectively located on both sides of the broken line 10. The first winding portion 700 includes a first wire layer 710, a second wire layer 720 and a third wire layer 730 arranged from the inside to the outside. The second wire portion 800 includes a first wire layer arranged from the inside to the outside. 810, a second wire layer 820 and a third wire layer 830. In the present embodiment, the first wire layers 710 and 810 are symmetrically arranged based on the broken line 10. In the present embodiment, the second wire layers 720 and 820 are symmetrically arranged based on the broken line 10. The first wire layer 710 has a first end 711 and a second end 712. The first wire layer 810 has a first end 811 and a second end 812. The second wire layer 720 has a first end 721 and a second end 722. The second wire layer 820 has a first end 821 and a second end 822. The third wire layer 730 has a first end 731 and a second end 732. The third wire layer 830 has a first end 831 and a second end 832. In the embodiment, the first end 711 of the first wire layer 710 of the first winding portion 700 and the first end 811 of the first wire layer 810 of the second winding portion 800 are coupled to each other.

The first wire layers 710 and 810, the second wire layers 720 and 820 or the third wire layers 730 and 830 of the first winding portion 700 and the second winding portion 800 may respectively form a substantially circular shape, a rectangular shape, or a hexagonal shape. , octagon or polygon shape. this In order to simplify the drawing, a rectangle is taken as an example. Furthermore, the first wire layers 710 and 810, the second wire layers 720 and 820, and the third wire layers 730 and 830 may have the same material (for example, copper, aluminum or an alloy thereof). In this embodiment, the first wire layers 710 and 810, the second wire layers 720 and 820, and the third wire layers 730 and 830 may have the same line width.

A coupling portion is disposed in the first insulating layer 200 and the second insulating layer 250 between the first winding portion 700 and the second winding portion 800, and includes a first pair of connecting layers 910 and a second pair of connections Layer 920. The first pair of connection layers 910 includes an upper bridging layer 911 disposed in the second insulating layer 250 and a lower bridging layer 912 disposed in the first insulating layer 200, and the second pair of connection layers 920 are disposed in the second An upper bridging layer 921 in the insulating layer 250 and a lower bridging layer 922 disposed in the first insulating layer 200.

The upper crossover layer 911 of the first pair of connection layers 910 connects the second end 722 of the second wire layer 720 of the first winding portion 700 to the second end 812 of the first wire layer 810 of the second winding portion 800. Furthermore, the lower crossover layer 912 of the first pair of connection layers 910 connects the second end 822 of the second wire layer 820 of the second winding portion 800 to the second of the first wire layer 710 of the first winding portion 700. The end 712, wherein the two sides of the lower bridging layer 912 are respectively provided with at least one conductive plug (for example, the conductive plug 715 shown in FIG. 4B) to electrically connect the second insulating layer 250. A wire layer 710 and a second wire layer 820. Thus, the first pair of connection layers interleaves the second ends 712 and 812 of the first wire layers 810 and 710 and the second ends 722 and 822 of the second wire layers 720 and 820. It should be noted that in the drawings of the present embodiment, only one conductive plug 715 is illustrated, but is not intended to limit the present invention. In most embodiments, one side of the lower jumper layer 912 connected to the second end 712 is provided with a plurality of conductive plugs. 715.

The upper crossover layer 921 of the second pair of connection layers 920 connects the first end 731 of the third wire layer 730 of the first winding portion 700 to the first end 821 of the second wire layer 820 of the second winding portion 800. Furthermore, the lower crossover layer 922 of the second pair of connection layers 920 connects the first end 831 of the third wire layer 830 of the second winding portion 800 to the first of the second wire layer 720 of the first winding portion 700. The second end of the lower cross-layer 922 is provided with at least one conductive plug (not shown) for electrically connecting the second wire layer 720 and the third wire layer 830 disposed in the second insulating layer 250. . Therefore, the second pair of connection layers 920 are alternately connected to the first ends 721 and 821 of the second wire layers 720 and 820 and the first ends 731 and 831 of the third wire layers 730 and 830.

The semiconductor device having the inductive component further includes a first extension portion 610 and a second extension portion 620 disposed in the second insulation layer 250. In an embodiment, the first extension portion 610 and the second extension portion 620 are correspondingly connected to the second ends 732 and 832 of the third wire layers 730 and 830 and are parallel to each other. In other embodiments, the first extension 610 and the second extension 620 are not parallel to each other. The second ends 732 and 832 of the third wire layers 730 and 830 can be disposed on the same side of the broken line 10, or can be symmetrically disposed on both sides of the broken line 10, so that the first extending portion 610 and the second extending portion 620 can be adjusted. The side widths of the third wire layers 730 and 830.

Furthermore, the semiconductor device having the inductive component further includes a third extending portion 630 disposed in the first insulating layer 200 and connected to the second winding through the at least one conductive plug 815 (shown in FIG. 4B). The first wire layer 810 of the portion 800. In the present embodiment, the third extension 630 is similar to the branching structure as proposed in the prior art. It should be noted that in the drawings of the present embodiment, only one conductive plug 815 is shown, but is not intended to limit the present invention. In most embodiments, A plurality of conductive plugs 815 are disposed on one side of the first extension layer 810 of the third extension portion 630 connected to the second winding portion 800. In addition, the extending direction of the first extending portion 610 and the second extending portion 620 is perpendicular to the extending direction of the third extending portion 630 as viewed from a top view. In other embodiments, if the first extending portion 610 and the second extending portion 620 are not parallel to each other, the extending direction of the third extending portion 630 is opposite to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. One of them is vertical. Of course, in still another embodiment, the extending direction of the third extending portion 630 is not perpendicular to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. In other embodiments, the third extension 630 can be coupled to the first wire layer 710 of the first winding portion 700 through a conductive plug. In an embodiment, the third extension 630 can be coupled to an electrostatic discharge protection device 635. In the present embodiment, the ESD protection device 635 is disposed on a side close to the first extension portion 610 and the second extension portion 620, but is not intended to limit the present invention. In other embodiments, the ESD protection device 635 can be disposed on a side away from the first extension 610 and the second extension 620. The user can adjust the position of the ESD protection device 635 according to the wiring requirements. In addition, in the present embodiment, the position of the third extending portion 630 is close to the first extending portion 610 and the second extending portion 620, but is not intended to limit the present invention. In other embodiments, the third extension 630 can be disposed in a range of side widths of the innermost wire layer (eg, the first wire layer 710 or the first wire layer 810) according to different needs.

In this embodiment, the semiconductor device having the inductive component further includes a multilayer interconnect structure 202 including a dielectric layer and a conductive layer disposed within the dielectric layer, as shown in FIG. 4B. The multilayer interconnect structure 202 is disposed between the first insulating layer 200 and the substrate 100, and overlaps with the first conductive layers 710 and 810, and is connected to the first conductive layer 710 through at least two conductive plugs (not shown). 810 to maintain electricity The quality of the sensor.

In an embodiment, the first wire layers 710 and 810 and the adjacent second wire layers 720 and 820 have a plurality of different pitches, and at least one of the pitches D1 is greater than the second wire layers 720 and 820 and adjacent ones. The spacing D2 between the third wiring layers 730 and 830 is as shown in FIG. 4A. In detail, in the case where the first winding portion 700 and the second winding portion 800 of FIG. 4A generally form a quadrilateral, only one side of the pitch D1 is larger than the second wiring layers 720 and 820 and the adjacent third wiring layer. The spacing D2 between 730 and 830. In another embodiment, the first wire layers 710 and 810 and the adjacent second wire layers 720 and 820 have a plurality of the same pitch D1, and the pitch D1 is greater than the second wire layers 720 and 820 and the adjacent third. The spacing D2 between the wire layers 730 and 830 is as shown in FIG. In detail, in the case where the first winding portion 700 and the second winding portion 800 of FIG. 6 are substantially quadrangular, the pitch D1 of the four sides is greater than the second wire layers 720 and 820 and the adjacent third wire layer 730. The distance D2 between 830 and 830.

Furthermore, other odd-numbered symmetrical inductive elements have structures similar to the inductive elements of Figures 4A, 4B, and 6.

Hereinafter, a semiconductor device having a four-turn inductor element according to another embodiment of the present invention will be described with reference to FIGS. 5 and 7, wherein the same reference numerals are given to the same components as those in FIGS. 4A, 4B, and 6 and the description thereof is omitted. In FIG. 5, the first winding portion 700 further includes a fourth wire layer 740 located outside the third wire layer 730 and having a first end 741 and a second end 742. The second winding portion 800 further includes a fourth wire layer 840 located outside the third wire layer 830 and having a first end 841 and a second end 842. Similarly, the fourth wire layers 740 and 840 of the first winding portion 700 and the second winding portion 800 may have the same line width, and the line width is The line widths of the first wire layers 710 and 810, the second wire layers 720 and 820, and the third wire layers 730 and 830 are the same, and the materials and shapes of the fourth wire layers 740 and 840 can be the same as the first wire layer 710. And 810, second wire layers 720 and 820, and third wire layers 730 and 830.

Furthermore, in the embodiment, the coupling portion further includes a third pair of connection layers 930 including an upper bridging layer 931 disposed in the second insulating layer 250 and a lower portion disposed in the first insulating layer 200. Jumper layer 932. The upper jumper layer 931 of the third pair of connection layers 930 connects the second end 742 of the fourth wire layer 740 of the first winding portion 700 to the second end 832 of the third wire layer 830 of the second winding portion 800. Furthermore, the lower crossover layer 932 of the third pair of connection layers 930 connects the second end 732 of the third wire layer 730 of the first winding portion 700 to the second of the fourth wire layer 840 of the second winding portion 800. The terminal 842, wherein the two sides of the lower jumper layer 932 are respectively provided with at least one conductive plug (not shown) for electrically connecting the third wire layer 730 and the fourth wire layer 840 disposed in the second insulating layer 250. . Accordingly, the third pair of connection layers 930 alternately connect the second ends 732 and 832 of the third wire layers 730 and 830 with the second ends 742 and 842 of the fourth wire layers 740 and 840.

In the present embodiment, the first extension portion 610 and the second extension portion 620 are disposed in the second insulation layer 250 as shown in FIG. 4B. In an embodiment, the first extension portion 610 and the second extension portion 620 are correspondingly connected to the first ends 741 and 841 of the fourth wire layers 740 and 840 and are parallel to each other. In other embodiments, the first extension 610 and the second extension 620 are not parallel to each other. In an embodiment, the extending direction of the first extending portion 610 and the second extending portion 620 is perpendicular to the extending direction of the third extending portion 630. In other embodiments, if the first extension portion 610 and the second extension portion 620 are not parallel to each other, the extension of the third extension portion 630 The direction of the line is perpendicular to one of the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. Of course, in still another embodiment, the extending direction of the third extending portion 630 is not perpendicular to the extending direction of the first extending portion 610 and the extending direction of the second extending portion 620. In other embodiments, the third extension 630 can be disposed in a range of side widths of the innermost wire layer (eg, the first wire layer 710 or the first wire layer 810) according to different needs. Furthermore, other even-numbered symmetrical inductor elements have a structure similar to that of the inductor elements of FIGS. 5 and 7.

The first wire layers 710 and 810 and the adjacent second wire layers 720 and 820 have the same or different pitches between the adjacent second wire layers 720 and 820, wherein at least one pitch D1 is compared with the conventional chip built-in inductor component. It is larger than the distance D2 between the second wire layers 720 and 820 and the adjacent third wire layers 730 and 830. In detail, in the case where the first winding portion 700 and the second winding portion 800 of FIG. 5 substantially form a quadrilateral, only one side of the pitch D1 is larger than the second wire layers 720 and 820 and the adjacent third wire layer. The spacing D2 between 730 and 830. In the case where the first winding portion 700 and the second winding portion 800 of FIG. 7 are substantially quadrangular, the four sides of the pitch D1 are larger than the second wire layers 720 and 820 and the adjacent third wire layers 730 and 830. The spacing between the two is D2. Therefore, the coupling coefficient can be reduced by increasing the pitch, and the length of the wire of the first inductor or the second inductor can be changed by adjusting the spacing between the first wire layers 710 and 810 and the adjacent second wire layers 720 and 820. Further, the first inductance value or the second inductance value can be unilaterally adjusted, so that the flexibility of the circuit design can be increased while the difficulty of adjusting the circuit parameters is reduced, so that the desired circuit characteristics can be easily obtained.

In addition, those skilled in the art can easily understand that the above embodiments of the present invention can be applied to other symmetric inductor elements of more than four turns, and have the same advantages.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

10‧‧‧ dotted line

203‧‧‧ Conductive layer

210‧‧‧First wire layer

First end of 211, 221, 331, 341, 431, 441‧‧

332, 342, 432, 442‧‧‧ second end

220‧‧‧Second wire layer

300‧‧‧First winding department

330, 430‧‧‧ third wire layer

340, 440‧‧‧4th wire layer

400‧‧‧Second winding department

510‧‧‧ first pair of connection layers

520‧‧‧Second pair of connection layers

511, 521‧‧‧ upper jumper

512, 522‧‧‧ lower jumper

610‧‧‧First Extension

620‧‧‧Second extension

630‧‧ Third extension

635‧‧‧Electrostatic protective components

A‧‧‧ central area

R1‧‧‧ adjustment range

Claims (19)

A semiconductor device comprising: a first insulating layer and a second insulating layer, sequentially disposed on a substrate, wherein the substrate has a central region; a first wire layer and a second wire layer are disposed on the first An insulating layer surrounding the central region and having a first end and a second end, wherein the second ends of the first wire layer and the second wire layer are coupled to each other; and a third extending portion Provided in the first insulating layer, connected to the first wire layer or the second wire layer; a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center And a third wire layer and a fourth wire layer respectively arranged from the inside to the outside, the third wire layer and the fourth wire layer respectively have a first end and a second end; and a coupling The first insulating layer and the second insulating layer disposed between the first winding portion and the second winding portion, including: a first pair of connecting layers, the third conductive layer The first ends of the first end are alternately connected to the first wire layer and the second wire layer And a second pair of connection layers interleaving the third wire layers and the second ends of the fourth wire layers; wherein the first wire layer and the second wire layer and the third wires The layers at least partially overlap. The semiconductor device of claim 1, wherein the first wire layer and the second wire layer extend along the third wire layer or the fourth wire layer to make the first wire layer and the second wire The second ends of the wire layer are coupled to each other And at least partially overlapping the third wire layer or the fourth wire layer. The semiconductor device of claim 1, wherein the first pair of connection layers and the second pair of connection layers comprise two jumper layers respectively disposed in the first insulating layer and the second insulating layer. The semiconductor device of claim 1, wherein the third extension is connected to an electrostatic discharge protection device. The semiconductor device of claim 1, further comprising a first extension portion and a second extension portion disposed in the second insulation layer, corresponding to the first ones connected to the fourth wire layers The ends are parallel to each other, wherein the extending directions of the first extending portion and the second extending portion are perpendicular to the extending direction of the third extending portion. The semiconductor device of claim 1, wherein the first winding portion and the second winding portion each further comprise a fifth wire layer located outside the fourth wire layer and having a first end And a second end, and wherein the coupling portion further comprises a third pair of connection layers interleaving the fourth wire layers and the first ends of the fifth wire layers. The semiconductor device of claim 6, wherein the first wire layer and the second wire layer extend along the third wire layer, the fourth wire layer or the fifth wire layer to make the first The second ends of the wire layer and the second wire layer are coupled to each other and at least partially overlap the third wire layer, the fourth wire layer or the fifth wire layer. The semiconductor device of claim 6, further comprising a first extension portion, a second extension portion and a third extension portion, wherein the first extension portion and the second extension portion are disposed on the second insulation Within the layer, correspondingly connected to the fifth conductor The second ends of the layers are parallel to each other, and the third extension portion is disposed in the first insulation layer and is connected to the first wire layer or the second wire layer, wherein the first extension portion and the second extension portion The extending direction of the portion is perpendicular to the extending direction of the third extending portion. The semiconductor device of claim 6, wherein the first winding portion and the second winding portion each further comprise a sixth wire layer located outside the fifth wire layer and having a first end And a second end, and wherein the coupling portion further comprises a fourth pair of connection layers interleaving the fifth wire layers and the second ends of the sixth wire layers. The semiconductor device of claim 9, wherein the first wire layer and the second wire layer are along the third wire layer, the fourth wire layer, the fifth wire layer or the sixth wire layer Extending such that the second ends of the first wire layer and the second wire layer are coupled to each other and to the third wire layer, the fourth wire layer, the fifth wire layer or the sixth wire layer at least partially overlapping. The semiconductor device of claim 9, further comprising a first extension portion, a second extension portion and a third extension portion, wherein the first extension portion and the second extension portion are disposed on the second insulation Correspondingly connected to the first ends of the sixth wire layers and parallel to each other, the third extending portion is disposed in the first insulating layer and connected to the first wire layer or the second wire layer. The extending direction of the first extending portion and the second extending portion is perpendicular to the extending direction of the third extending portion. The semiconductor device of claim 1, further comprising a multilayer interconnect structure between the first insulating layer and the substrate and connected to the first conductive layer via at least two conductive plugs And the second wire layer. A semiconductor device comprising: a first insulating layer and a second insulating layer, sequentially disposed on a substrate, wherein the substrate has a central region; a first winding portion and a second winding portion are disposed on The second insulating layer surrounds the central region and includes a first wire layer, a second wire layer and a third wire layer, which are arranged from the inside to the outside, and the first wire layer and the second wire layer The wire layer and the third wire layer respectively have a first end and a second end, wherein the first ends of the first wire layers are coupled to each other; and a coupling portion is disposed on the first winding The first insulating layer and the second insulating layer between the line portion and the second winding portion, and the coupling portion includes: a first pair of connecting layers, staggering the first wire layers, and the like The second ends of the second wire layer; and a second pair of connection layers interleaving the second wire layers and the first ends of the third wire layers; wherein the first wire layers are adjacent to each other The second wire layers have the same or different pitches between the second wire layers, and at least one of the pitches To such spacing between the second conductor layer and third conductive layer adjacent to these. The semiconductor device of claim 13 further comprising a third extension disposed in the first insulating layer and connected to the first wiring layer or the second wiring layer. The semiconductor device of claim 14, wherein the third extension is connected to an electrostatic discharge protection device. The semiconductor device according to claim 14, further comprising a first An extension portion and a second extension portion are disposed in the second insulation layer, and are correspondingly connected to the second ends of the third wire layers and parallel to each other, wherein the first extension portion and the second extension portion are The extending direction is perpendicular to the extending direction of the third extending portion. The semiconductor device of claim 13, wherein the first winding portion and the second winding portion each further comprise a fourth wire layer located outside the third wire layer and having a first And a second end, and wherein the coupling portion further comprises a third pair of connection layers interleaving the third wire layers and the second ends of the fourth wire layers. The semiconductor device of claim 17, further comprising a first extension portion, a second extension portion and a third extension portion, wherein the first extension portion and the second extension portion are disposed on the second insulation portion Correspondingly connected to the first ends of the fourth wire layers and parallel to each other, the third extending portion is disposed in the first insulating layer and connected to the first wire layer or the second wire layer. The extending direction of the first extending portion and the second extending portion is perpendicular to the extending direction of the third extending portion. The semiconductor device of claim 13, wherein the first pair of connection layers and the second pair of connection layers comprise two jumper layers respectively disposed in the first insulation layer and the second insulation layer.