TWI514411B - Sensing amplifier and sensing method thereof - Google Patents

Description

Sense amplifier and sensing method thereof

The present invention relates to a sense amplifier and a sensing method thereof, and more particularly to a current sense type sense amplifier and a sensing method thereof.

With the development of technology, non-volatile memory, such as flash memory, has been widely used in various electronic products. Generally, when the stored data recorded in a memory cell in the flash memory is to be read, the sensing amplifier is used to detect and determine the data content of the selected memory cell. Therefore, how to provide a sensing amplifier that can effectively sense memory cell data is one of the topics that the industry is currently working on.

The present invention relates to a sense amplifier and a sensing method thereof, which can sense data stored in a memory unit in a reverse current sensing manner, and can be applied to a threshold voltage of a memory unit. The variation is compensated.

According to an aspect of the invention, a sense amplifier is provided for sensing data stored by a memory unit, including a clamp circuit. The clamp circuit is coupled between a first node and a second node. The clamp circuit includes a first P-type transistor having a first end, a second end, and a control end receiving the first bias signal, the first end of the first P-type transistor and The second end is coupled to the first node and the second node respectively. In a sensing time segment, the sensing current from the memory unit flows into the second node via the first node.

According to another aspect of the present invention, a sensing method is provided for sensing a data stored in a memory unit, the sensing method comprising the steps of: providing a sensing amplifier, the sensing amplifier comprising a clamping circuit, The clamping circuit is coupled between the first node and the second node; and, providing a first bias signal to the control end of the first P-type transistor of the clamping circuit, the first end of the first P-type transistor And the second end is coupled to the first node and the second node respectively. In a sensing time segment, the sensing current from one of the memory units flows into the second node via the first node.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10, 30, 40, 60‧‧‧ memory
100, 300, 400, 600‧‧‧ sense amplifiers
102, 302, 402, 602‧‧‧ memory unit
104, 304, 404, 604‧‧‧ clamp circuit
106, 306, 406, 606‧‧‧ precharge sensing circuit
108, 308, 408, 608‧‧‧ latches
BL‧‧‧ bit line
CSL‧‧‧Common source line
N1, N2, N3, SENA‧‧‧ nodes
MP1~MP3‧‧‧first to third P-type transistors
MNS‧‧‧Isolated transistor
MNT‧‧‧Transmission transistor
MNL‧‧‧Limited Transistor
MN‧‧•O crystal
Csen‧‧‧Sensor Capacitor
BLS‧‧‧Isolation Control Signal
IPC‧‧‧ transmission control signal
STR‧‧‧ sense voltage signal
CLK‧‧‧ pulse signal
INV‧‧‧ control potential
BLC1~BLC3‧‧‧first to third bias signals
V(CSL), V(N1)~V(N3), V(SENA)‧‧‧ potential values
Tsen‧‧‧Sensing time section
Tset‧‧‧bias set time section
Tstr‧‧‧data judgment time section
I1, I2, I3, I6‧‧‧ sense current path

1 is a circuit diagram of a sense amplifier and a memory unit in accordance with a first embodiment of the present invention.
Figure 2 is a waveform diagram showing the operation signals of the sense amplifier.
FIG. 3 is a circuit diagram showing a sense amplifier and a memory unit according to a second embodiment of the present invention.
4 is a circuit diagram of a sense amplifier and a memory unit in accordance with a third embodiment of the present invention.
Figure 5 is a waveform diagram showing the operation signals of the sense amplifier.
Figure 6 is a circuit diagram of a sense amplifier and a memory unit in accordance with a fourth embodiment of the present invention.

First embodiment

Please refer to FIG. 1 and FIG. 2 simultaneously. FIG. 1 is a circuit diagram of the sense amplifier 100 and a memory 10 according to the first embodiment of the present invention. FIG. 2 is a waveform diagram showing the operation signals of the sense amplifier 100. The memory 10 includes a plurality of memory units 102 for storing data. The sense amplifier 100 is configured to sense data stored by the memory unit 102 via a one-bit line BL. The sense amplifier 100 includes a clamp circuit 104 and a pre-charge sensing circuit 106. The clamping circuit 104 is coupled between the first node N1 and the second node N2 for causing the potential value of the first node N1 to be higher than the potential value of the second node N2 in at least the sensing time period Tsen. The clamp circuit 104 includes a first P-type transistor MP1 having a first end, a second end, and a control terminal receiving the first bias signal BLC1. The first end and the second end of the first P-type transistor MP1 are respectively coupled to the first node N1 and the second node N2. In the sensing time segment Tsen, the sensing current from the memory unit 102 is first. The node N1 flows into the second node N2. The pre-charge sensing circuit 106 is coupled to the second node N2 for determining the data stored by the memory unit 102 according to the potential value of the second node N2 after sensing the time segment Tsen. The first P-type transistor MP1 described above is, for example, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The memory 10 is, for example, a non-volatile memory such as a NAND flash memory, and the memory unit 102 is, for example, a memory cell in a non-volatile memory.

The isolation transistor MNS is coupled between the first node N1 and the third node N3 and controlled by the isolation control signal BLS to determine whether to isolate the sense amplifier 100 from the memory unit 102.

The pre-charge sensing circuit 106 includes a sensing capacitor Csen, one end of the sensing capacitor Csen is coupled to the second node N2, and the other end receives the pulse signal CLK. The pre-charge sensing circuit 106 may further include a latch 108 and a transmission transistor MNT. In this example, the latch 108 includes two inverters connected in series to output a control potential INV. The control potential INV has two potential states of high potential and low potential, for example. The transmission transistor MNT has a first end, a second end, and a control end that receives the transmission control signal IPC. The first end and the second end of the transmission transistor MNT are coupled to the second node N2 and the latch 108, respectively.

To clearly illustrate the operation of the sense amplifier 100, the waveform diagram depicted in FIG. 2 is illustrated below.

First, in the bias setting time section Tset, the potential values of the respective nodes N1, N2, and N3 (indicated by V(N1), V(N2), and V(N3) in Fig. 2) are set to be suitable. The potential value sensed by the memory unit 102. During the bias setting time period Tset, the potential value of the common source line CSL of the memory unit 102 (indicated by V(CSL) in FIG. 2) is raised to a high potential (eg, 1.5 volts). The potential value of the first node N1 is gradually increased to a target level, and the target level is smaller than the potential value of the common source line CSL. In other words, the first node N1 is coupled to the source terminal of the memory unit 102, and the common source line CSL is coupled to the drain terminal of the memory unit 102. When the bias setting is completed, the potential value of the first end of the first P-type transistor MP1 (ie, the potential value of the first node N1) is clamped to a threshold voltage higher than the first bias signal BLC1. (Threshold Voltage) potential value. And in the bias setting time period Tset, the transmission control signal IPC is enabled to turn on the transmission transistor MNT to transmit the control potential INV having a low potential (for example, a ground potential, such as 0 volts) to the second node. N2, such that the potential value of the first node N1 is higher than the potential value of the second node N2.

Then, in the sensing time zone Tsen, the potential value of the pulse signal CLK is pulled down at the start of the sensing time zone Tsen, so that the potential of the second node N2 is pulled down at this time, and the first node is made The voltage difference between N1 and the second node N2 increases. Thereafter, in the sensing time section Tsen, it is assumed that the threshold voltage of the memory unit 102 is a low threshold voltage, so that a sensing current is generated, and the sensing current is along the third node N3, the isolated transistor MNS, and the first node. The path of the first P-type transistor MP1 and the second node N2 of the clamp circuit 104 (represented by the arrow I1 in FIG. 1) charges the second node N2. In this way, the potential difference between the first end and the second end of the first P-type transistor MP1 is compared with the fact that the potential value of the pulse signal CLK is not pulled down at the start of the sensing time period Tsen. If it is enlarged, the saturation window of the first P-type transistor MP1 is widened (that is, the voltage range in which the first P-type transistor MP1 is maintained in the saturation operation region is increased), thereby lowering the first P. The opportunity for the transistor MP1 to operate into the triode region.

On the other hand, in the sensing time period Tsen, the first node N1 is coupled to the source terminal of the memory unit 102, and the sensing current flows from the source terminal of the memory unit 102 into the sense amplifier 100. And since the transmission control signal IPC is disabled in the time period Tsen, so that the transmission transistor MNT is non-conductive, when the sensing current flows to the second node N2, the sensing capacitor Csen is charged and The sensing capacitor Csen accumulates a charge, thereby gradually increasing the potential value of the second node N2.

At the end of the sensing time segment Tsen, the first bias signal BLC1 is disabled to turn off the first P-type transistor MP1, and then the potential value of the pulse signal CLK is pulled high, so that The potential value of the two nodes N2 is then pulled up. The potential value of the second node N2 after the pull-up is used to determine the data stored in the memory unit 102 in the data determination time section Tstr. Further, in the data determination time zone Tstr, the first bias signal BLC1 is disabled, so that the first P-type transistor MP1 is not turned on. Then, the sensing voltage signal STR for controlling the reading of the memory data is enabled to conduct the crystal MN, so that the pre-charge sensing circuit 106 can determine the memory unit 102 according to the potential value of the second node N2. data.

Second embodiment

3 is a circuit diagram of a sense amplifier 300 and a memory 30 in accordance with a second embodiment of the present invention. The difference from the first embodiment is that the clamp circuit 304 of the sense amplifier 300 further includes a second P-type transistor MP2. The second P-type transistor MP2 has a first end, a second end, and a control end that receives the second bias signal BLC2. The first end of the second P-type transistor MP2 (connected to the node SENA in the figure) and the second end are respectively coupled to the second end of the first P-type transistor MP1 and the second node N2. Similar to the first P-type transistor MP1, when the bias setting is completed, the potential value of the first end of the second P-type transistor MP2 is clamped to a threshold voltage higher than the second bias signal BLC2. Potential value. The second bias signal BLC2 is smaller than the first bias signal BLC1 (for example, -0.25 volts). Within the sensing time period Tsen, the sense amplifier 300 senses the memory unit 302 and causes the sensing current from the memory unit 302 to follow the third node N3, the isolated transistor MNS, the first node N1, and the clamp. The path of the first P-type transistor MP1, the second P-type transistor MP2, and the second node N2 of the circuit 304 (represented by arrow I3 in FIG. 3) charges the second node N2.

Third embodiment

4 is a circuit diagram of a sense amplifier 400 and a memory 40 in accordance with a third embodiment of the present invention. The difference from the second embodiment is that the clamp circuit 404 of the sense amplifier 400 further includes a third P-type transistor MP3. The third P-type transistor MP3 has a first end, a second end, and a control end that receives the third bias signal BLC3. The first end of the third P-type transistor MP3 (connected to the node SENA in the figure) and the second end are respectively coupled to the second end of the first P-type transistor MP1 and the pre-charge sensing circuit 406. The first bias signal BLC1 is higher than the third bias signal BLC3 (for example, 0.25 volts), and the third bias signal BLC3 is higher than the second bias signal BLC2 (for example, 0.25 volts).

Please refer to FIG. 5 , which is a waveform diagram of the relevant operation signals of the sense amplifier 400 . As shown in FIG. 5, the bias set time period Tset further includes a precharge time period Tpre. In this pre-charging time period Tpre, the second bias signal BLC2 is disabled to isolate the first node N1 from the second node N2. At this time, the precharge sensing circuit 406 is transmitted through the latch 408, the third P-type transistor MP3, the node SENA, the first P-type transistor MP1, the first node N1, the isolated transistor MNS, and the third node N3. The path charges the third node N3 such that the potential value of the third node N3 is raised to a level slightly higher than the target level. In this way, the time required for the potential value of the third node N3 to reach the target level can be shortened. However, the present invention is not limited thereto, and the third node N3 may also increase its potential value through other bit line pre-charging methods. Alternatively, the pre-charge sensing circuit 406 may not pre-charge the third node N3, but gradually increase the potential value of the third node N3 to the target level when the circuit of the sense amplifier 400 is steady.

On the other hand, the first bias signal BLC1 can be used to determine the target level, which is sufficient for the sense current from the memory unit 402 to flow from the third node N3 to the second node N2 via the first node N1. Since the first node N1 is coupled to the source terminal of the memory unit 402, the sense amplifier 400 of the embodiment of the present invention can control the source terminal potential value of the memory unit 402 by adjusting the first bias signal BLC1. In this way, by controlling the voltage of the gate terminal and the source terminal of the memory unit 402, the sensing current change caused by the threshold voltage variation of the memory unit 402 can be effectively compensated, and the sensing current is maintained to be consistent, so that the sensing is performed. The amplifier 400 can more accurately discriminate the data stored by the memory unit 402.

At the end of the precharge time period Tpre, the control voltage INV is set to 0 volts, and then the transmission control signal IPC is enabled to turn on the transmission transistor MNT to have a low potential (for example, a ground potential such as 0 volts) The control potential INV is transmitted to the second node N2 such that the potential value of the first node N1 is higher than the potential value of the second node N2.

When the bias voltage setting is completed, the potential value of the first end of the first P-type transistor MP1 (ie, the potential value of the first node N1) is clamped to a threshold voltage higher than the first bias signal BLC1. Potential. The potential value of the first end of the second P-type transistor MP2 (i.e., the potential value of the node SEAN) is clamped to a potential value higher than the second bias signal BLC2 by a threshold voltage. And because the third bias signal BLC3 is higher than the second bias signal BLC2, when the bias setting of each node is completed, the third P-type transistor MP3 is not turned on.

Next, at the start of the sensing time zone Tsen, the potential value of the pulse signal CLK is pulled down, so that the potential value of the second node N2 is pulled down at this time. At the same time, the sense amplifier 400 senses the memory unit 402. It is assumed that the threshold voltage of the memory unit 402 is a low threshold voltage, so that a sense current is generated. At this time, the sensing current from the memory unit 402 is along the third node N3, the isolation transistor BLS, the first node N1, the first P-type transistor MP1 of the clamp circuit 404, and the second P-type transistor MP2. The path of the two nodes N2 (represented by arrow I4 in Fig. 4) charges the second node N2. During the sensing time period Tsen, the transmission control signal IPC is disabled to make the transmission transistor MNT non-conductive. In this way, when the sense current flows to the second node N2, the sensing capacitor Csen is charged and the sensing capacitor Csen is accumulated, thereby gradually increasing the potential value of the second node N2.

Since the potential value of the second node N2 rises, the potential value of the node SENA (indicated by V(SENA) in FIG. 5) may be pulled high. In this case, if the potential value of the node SENA is raised enough to make The third P-type transistor MP3 is turned on, and the turned-on third P-type transistor MP3 causes the potential value of the node SENA to be clamped to a potential value higher than the third bias signal BLC3 by a threshold voltage. In this way, the variation of the potential value of the node SENA due to the increase in the potential value of the second node N2 can be reduced.

Then, at the end of the sensing time segment Tsen, the potential value of the pulse signal CLK is pulled high, so that the potential value of the second node N2 is subsequently pulled up. Then, the sensing voltage signal STR for controlling the reading of the memory data is enabled to conduct the crystal MN, so that the pre-charging sensing circuit 406 can determine the memory unit 402 according to the potential value of the second node N2. data.

Fourth embodiment

FIG. 6 is a circuit diagram of the sense amplifier 600 and a memory unit 602 according to the fourth embodiment of the present invention. The difference from the third embodiment is that the clamp circuit 604 further includes a limiting transistor MNL. The limiting transistor MNL has a first end, a second end, and a control terminal that receives a potential value of the second node N2 (indicated by V(N2) in the figure). The first end and the second end of the limiting transistor MNL are respectively coupled to the second end of the third P-type transistor MP3 and the pre-charge sensing circuit 606. The first bias signal BLC1 is higher than the second bias signal BLC2, and the second bias signal BLC2 is substantially equal to or smaller than the third bias signal BLC3. In the sensing time segment Tsen, the sense amplifier 600 senses the memory unit 602 and causes the sensing current from the memory unit 602 to be along the third node N3, the isolated transistor MNS, the first node N1, and the clamp. The path of the first P-type transistor MP1, the second P-type transistor MP2, and the second node N2 of the circuit 304 (represented by arrow I6 in Fig. 6) charges the second node N2.

In this embodiment, if the potential value of the second node N2 is increased and the limiting transistor MNL is turned on, the potential value of the node SENA is clamped to a potential value higher than the second bias signal BLC3 by a threshold voltage. . Therefore, the clamp circuit 604 of the present embodiment can prevent the potential value of the node SENA from being affected by the increase in the potential value of the second node N2.

The embodiment of the invention further provides a sensing method of the sensing amplifier. The sensing method is used to sense one of the data stored in a memory unit. This sensing method includes the following steps. First, a sense amplifier is provided, the sense amplifier including a clamp circuit. The clamp circuit is coupled between a first node and a second node. Next, a first bias signal is provided to the control terminal of the first P-type transistor of one of the clamp circuits. The first end and the second end of the first P-type transistor are respectively coupled to the first node and the second node. Within the sensing time segment, one of the sensing currents from the memory unit flows into the second node via the first node.

In summary, the embodiment of the present invention causes the potential value of the first node to be higher than the potential value of the second node at least in the sensing time period by the clamping circuit including at least one P-type transistor, so as to be from the memory unit. The sense current can charge the second node of the sense amplifier to achieve reverse current sensing. On the other hand, based on the architecture of reverse current sensing, the sense amplifier can elastically adjust the source terminal potential value of the memory unit by changing the clamp circuit, thereby compensating for the sense current variation caused by the threshold voltage variation of the memory unit. The sense amplifier can more accurately determine the data stored in the memory unit.

While the invention has been described above in the preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧ memory

100‧‧‧Sense Amplifier

102‧‧‧ memory unit

104‧‧‧Clamp circuit

106‧‧‧Precharge sensing circuit

108‧‧‧Latch

BL‧‧‧ bit line

CSL‧‧‧Common source line

N1, N2, N3‧‧‧ nodes

MP1‧‧‧First P-type transistor

MNS‧‧‧Isolated transistor

MNT‧‧‧Transmission transistor

MN‧‧•O crystal

Csen‧‧‧Sensor Capacitor

BLS‧‧‧Isolation Control Signal

IPC‧‧‧ transmission control signal

STR‧‧‧ sense voltage signal

CLK‧‧‧ pulse signal

INV‧‧‧ control potential

BLC1‧‧‧First bias signal

I1‧‧‧Sense current path

Claims (1)

【1】

A sense amplifier for sensing a data stored in a memory unit, including:

a clamping circuit coupled between a first node and a second node, the clamping circuit comprising a first P-type transistor having a first end and a second end Receiving a control terminal of the first bias signal, the first end and the second end of the first P-type transistor are respectively coupled to the first node and the second node, in a sensing time section The sensing current from one of the memory cells flows into the second node via the first node.

【2】

The sense amplifier of claim 1, wherein the clamp circuit further comprises:

a second P-type transistor having a first end, a second end, and a control end receiving a second bias signal, wherein the first end and the second end of the second P-type transistor are respectively coupled Connected to the second end of the first P-type transistor and the second node.

[3]

The sensing amplifier of claim 2, wherein the clamping circuit further comprises a third P-type transistor coupled to the second of the first P-type transistor The terminal is controlled by a third bias signal.

[4]

The sense amplifier of claim 3, wherein the first bias signal is higher than the third bias signal, and the third bias signal is higher than the second bias signal.

[5]

The sense amplifier of claim 3, wherein the clamp circuit further comprises a limiting transistor coupled to the third P-type transistor and controlled by the second node Potential value.

[6]

A sensing method for sensing a data stored in a memory unit, the sensing method comprising:

Providing a sense amplifier, the sense amplifier includes a clamp circuit coupled between a first node and a second node;

Providing a first bias signal to one of the first P-type transistors of the clamp circuit, wherein the first end and the second end of the first P-type transistor are respectively coupled to the first node And the second node, in a sensing time segment, a sensing current from the memory unit flows into the second node via the first node.

[7]

The sensing method of claim 6, wherein the clamping circuit further comprises a second P-type transistor, the sensing method further comprising:

Providing a second bias signal to one of the control terminals of the second P-type transistor of the clamp circuit, wherein the first end and the second end of the second P-type transistor are respectively coupled to the first P The second end of the type of transistor and the second node.

【8】

The sensing method of claim 7, wherein the clamping circuit further comprises a third P-type transistor, the sensing method further comprising:

A third bias signal is provided to one of the third P-type transistors of the clamping circuit, and the third P-type transistor is coupled to the second end of the first P-type transistor.

【9】

The sensing method of claim 8, wherein the first bias signal is higher than the third bias signal, and the third bias signal is higher than the second bias signal.

[10]

The sensing method of claim 8, wherein the clamping circuit further comprises a limiting transistor, the sensing method further comprising:

And providing a potential value of the second node to a control terminal of the limiting transistor of the clamping circuit, the limiting transistor being coupled to the third P-type transistor.