TWI514480B - Method for manufacturing multi-gate transistor device - Google Patents

Description

Multi-gate polar crystal element manufacturing method

The invention relates to a method for fabricating a multi-gate transistor.

After the component has been developed to the 65 nm technology generation, it is difficult to continue to shrink using a conventional planar metal-oxide-semiconductor (MOS) transistor process. Therefore, conventional techniques are proposed to be stereo or non-planar (non -planar) A multi-gate transistor component such as a Fin Field effect transistor (FinFET) component replaces a planar transistor component.

Please refer to FIG. 1 , which is a perspective view of a conventional FinFET device. As shown in FIG. 1 , the conventional FinFET device 100 firstly patterns a single crystal germanium layer on the surface of the insulating substrate 102 by etching or the like for use in a silicon-on-insulator (SOI) substrate 102. Forming a fin-shaped germanium film (not shown), and forming an insulating layer 104 covering a portion of the germanium film on the germanium film, and the gate 106 is coated on the insulating layer 104 and the germanium film, and finally by ion The steps of the implantation process and the tempering process form a source/drain 108 in the fin-shaped germanium film not covered by the gate 106. Since the process of the FinFET device 100 can be integrated with a conventional logic device process, it has considerable process compatibility. In addition, when the FinFET element 100 is disposed on the SOI substrate 102 described above, conventional isolation techniques such as shallow trench isolation may be omitted. More importantly, since the three-dimensional structure of the FinFET element 100 increases the contact area of the gate 106 with the fin-shaped germanium substrate, the carrier control of the gate 106 for the channel region can be increased, thereby reducing the size of the small-sized component. The source induced induced drain induced barrier lowering (DIBL) effect and the short channel effect. Furthermore, since the gate 106 of the same length in the FinFET element 100 has a larger channel width, a doubled drain drive current can be obtained.

However, since the source/drain 108 of the FinFET device 100 is an elongated structure, it is often disadvantageous because the resistance is too large to facilitate the electrical performance of the FinFET device 100, and the source/drain 108 is too elongated. The alignment is not easy when the contact plug is formed later, that is, the process window of the contact plug process is damaged.

Accordingly, it is an object of the present invention to provide a method of fabricating a multi-gate transistor device that solves the above problems.

According to the patent application scope of the present invention, a method for fabricating a multi-gate transistor device is provided. The fabrication method first provides a semiconductor substrate, and a patterned semiconductor layer and a gate dielectric layer are formed on the semiconductor substrate. And a gate layer, and the gate dielectric layer and the gate layer cover a portion of the patterned semiconductor layer. Forming a composite insulating layer over the semiconductor substrate, the composite insulating layer covering the patterned semiconductor layer and the gate layer, and the composite insulating layer includes at least a first insulating layer and a second insulating layer from bottom to top. . Next, a first etching process is performed to remove a portion of the composite insulating layer to form a first sidewall around the gate layer and a second sidewall around the patterned semiconductor layer. After forming the first sidewall and the second sidewall, removing the second sidewall to expose a portion of the first insulating layer, and the first insulating layer covers a portion of the patterned semiconductor layer while removing a portion of the a first sidewall for forming a third sidewall around the gate layer. After forming the third sidewall, the exposed first insulating layer is removed to expose the patterned semiconductor layer.

According to the method of fabricating the multi-gate transistor of the present invention, the composite insulating layer is used as a protective layer, so that the patterning underneath can be ensured when the second sidewall covering the patterned semiconductor layer is removed. The semiconductor layer is not damaged. Therefore, the multi-gate transistor element provided by the present invention can be lifted before the contour of the patterned semiconductor layer is affected, and the patterned semiconductor layer is exposed on the semiconductor substrate to increase the selective epitaxial growth. , SEG) The area where the epitaxial layer can be grown in the process, and finally achieve the purpose of reducing the source/drain resistance of the FinFET. At the same time, since the epitaxial layer grows on the exposed patterned semiconductor layer, the surface area of the source/drain is increased, which is more advantageous for improving the process tolerance of the subsequent contact plug process.

Please refer to FIG. 2 to FIG. 7 . FIG. 2 to FIG. 7 are schematic diagrams showing a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention, wherein FIG. 2 is to FIG. Figure 6 is a schematic cross-sectional view taken along line A-A' in Fig. 7. As shown in FIG. 2, the preferred embodiment first provides a semiconductor substrate 200. The semiconductor substrate 200 can include a bulk silicon substrate, and the bulk substrate includes a plurality of shallow trench isolations 204. However, the semiconductor substrate 200 provided by the preferred embodiment may also be a silicon-on-insulator (SOI) substrate.

Please continue to see Figure 2. Next, a patterned hard mask (not shown) is formed on the semiconductor substrate 200 to define fin portions of at least one multi-gate transistor element. Subsequently, an etching process is performed to remove a portion of the semiconductor material on the semiconductor substrate 200, and at least one patterned semiconductor layer 206 is formed on the semiconductor substrate 200, and the patterned semiconductor layer 206 includes at least one as shown in FIG. The fin portion of the multi-gate transistor component. The fin portion has a width and a height, and the width has a ratio to the height, and the ratio may be 1:1.5 to 1:2. For example, in the preferred embodiment, the width of the fin portion may be 20 nanometers (nm); and the height may be 30 nm, but is not limited thereto.

Please still refer to Figure 2. Next, a dielectric layer (not shown), a gate forming layer (not shown), and a patterned hard mask 214 are sequentially formed on the semiconductor substrate 200. Subsequently, the dielectric layer and the gate forming layer are patterned, and a gate dielectric layer 210 and a gate layer 212 covering a portion of the patterned semiconductor layer 206 are formed on the semiconductor substrate 200. The sum of the height of the patterned hard mask 214, the gate layer 212 and the gate dielectric layer 210 is about 60 nm, but is not limited thereto. In addition, as shown in FIG. 7, the gate dielectric layer 210 and the gate layer 212 extend in a direction perpendicular to the extending direction of the patterned semiconductor layer 206, and the gate dielectric layer 210 and the gate layer 212 cover a partial pattern. The sidewalls of the semiconductor layer 206 are formed. The gate dielectric layer 210 may comprise a dielectric material such as cerium oxide (SiO), cerium nitride (SiN), cerium oxynitride (SiON) or the like. In the preferred embodiment, the gate dielectric layer 210 may further comprise a high-k material such as hafnium oxide (HfO), hafnium niobate (HfSiO) or a metal such as aluminum, zirconium or hafnium. Metal oxides or metal silicates, etc., but are not limited thereto. In addition, when the gate dielectric layer 210 of the preferred embodiment uses a high-k material, the present invention can be integrated with a metal gate process to provide sufficient control for matching the high-k gate dielectric layer. electrode. Accordingly, the gate layer 212 can be made of a different material depending on the gate-first process or the gate-last process of the metal gate. In addition, the patterned hard mask 214 may include tantalum nitride, but is not limited thereto.

In addition, after the fabrication of the gate dielectric layer 210 and the gate layer 212 is completed, the preferred embodiment can form a source/drain in the patterned semiconductor layer 206 by using oblique ion implantation or the like as needed. Source/drain extension region (not shown).

As shown in FIG. 2, after the fabrication of the source/drain extension regions is completed, the preferred embodiment forms a composite insulating layer 220 on the semiconductor substrate 200, and the composite insulating layer 220 covers the patterned semiconductor layer 206. The hard mask 214 and the gate layer 212 are patterned. In the preferred embodiment, the composite insulating layer 220 is a bi-layered structure, and the two-layer structure includes a first insulating layer 222 sequentially from bottom to top as shown in FIG. And a second insulating layer 224. The etching rate of the first insulating layer 222 is different from the etching rate of the second insulating layer 224. For example, the first insulating layer 222 may include a tantalum nitride layer; and the second insulating layer 224 includes a tantalum oxide layer. In addition, the first insulating layer 222 of the preferred embodiment is preferably a conformal tantalum nitride film layer having uniform coverage formed by an atomic layer deposition (ALD) method, and the thickness thereof is about It is 50 nm to 100 nm. The second insulating layer 224 may be a ruthenium oxide film layer formed by a chemical vapor deposition (CVD) method, and has a thickness of about 200 nm to 300 nm.

Please refer to Figure 3. Next, a portion of the composite insulating layer 220 is removed, for example, by an anisotropic dry etching method to etch the second insulating layer 224 to form a surrounding of the patterned hard mask 214 and the gate layer 212. A first sidewall 230 is formed, and a second sidewall 232 is formed around the patterned semiconductor layer 206. It should be noted that since the sum of the height of the patterned hard mask 214, the gate layer 212 and the gate dielectric layer 210 is about double that of the patterned semiconductor layer 206, the patterned semiconductor is etched according to the etching characteristics of the dry etching method. The second sidewall sub-232 around layer 206 is automatically smaller than the first sidewall sub-230 when formed. As shown in FIG. 3, the width a of the first side wall sub-230 is always greater than the width b of the second side wall sub-232. In addition, when the first sidewall spacer 230 and the second sidewall spacer 232 are formed, a portion of the composite insulating layer 220 is simultaneously exposed, that is, a portion of the first insulating layer 222 is exposed.

Please refer to Figure 4. Next, an isotropic wet etching method, for example, using dilute hydrogen fluoride (DHF) to remove the second sidewall spacer 232 to expose a portion of the composite insulating layer 220, That is, the first insulating layer 222 is exposed. In addition, the wet etching method removes a portion of the first sidewalls 230 at the same time to form a third sidewall 234 around the patterned hard mask 214 and the gate layer 212, and the third sidewall 234 is smaller than the first sidewall. 230. It should be noted that when the second sidewall spacer 232 is removed by the wet etching method, the first insulating layer 222 still covers the patterned semiconductor layer 206, the patterned hard mask 214 and the gate layer 212, thus patterning the semiconductor layer 206. The gate layer 212 is covered and protected by the first insulating layer 222, and any influence in the wet etching method can be avoided.

Please refer to Figure 5. Next, another isotropic wet etching method can be utilized, such as removing the exposed composite insulating layer 220 with hot phosphoric acid, ie removing the exposed first insulating layer 222 to expose the patterning. The semiconductor layer 206 is such that the third sidewall 234 includes a first insulating layer 222 and a second insulating layer 224. It should be noted that the outline of the third sidewall sub-234 is not affected when the first insulating layer 222 is removed due to the difference in etching rate. In addition, since the first insulating layer 222 is a thin conformal film layer, it can be easily removed without affecting the patterned semiconductor layer 206. Finally, when the first insulating layer 222 and the patterned hard mask 214 comprise the same material (for example, tantalum nitride), part of the patterned hard mask 214 can be removed in the wet etching method, thereby reducing the pattern. The sum total height of the hard mask 214 and the gate layer 212.

Please refer to Figure 6. After the first insulating layer 222 is removed to expose the patterned semiconductor layer 206, a selective epitaxial growth (SEG) process may be performed to form an epitaxial layer 208 on the surface of the patterned semiconductor layer 206. In addition, in the SEG process, a material having a lattice constant different from the lattice constant of the patterned semiconductor layer 206 may be added according to the conductivity type of the multi-gate transistor element, and may be added during, before, or after the SEG process. The conductive type dopant can be used to complete the fabrication of the source/drain of the multi-gate transistor element, and at the same time, the fabrication of the multi-gate transistor element 240 provided by the preferred embodiment.

According to the method for fabricating the multi-gate transistor of the preferred embodiment, the first insulating layer 222 can be used as a protective layer when the desired sidewall is fabricated by using different etching rates. The outline of the patterned semiconductor layer 206 is protected. Subsequently, the first insulating layer 222 is removed without affecting the outline of the patterned semiconductor layer 206, so that the sidewalls and the top of the patterned semiconductor layer 206 are exposed. In other words, the preferred embodiment can increase the exposed area of the patterned semiconductor layer 206. In the SEG process, the epitaxial layer 208 only grows along the surface of the germanium material. Therefore, in the preferred embodiment, the exposed area of the patterned semiconductor layer 206 can be increased to further increase the growth place of the epitaxial layer 208. Therefore, after the SEG process, the top and sidewalls of the patterned semiconductor layer 206 are increased by the presence of the epitaxial layer 208, that is, the source/drain is increased, so that the source of the multi-gate transistor element 240 can be reduced. The purpose of the resistance at the bungee. At the same time, because the epitaxial layer 208 grows on the surface of the exposed patterned semiconductor layer 206, the surface area of the source/drain is increased, which is more favorable for improving the process tolerance of the subsequent contact plug process.

Please refer to FIG. 8 to FIG. 12 . FIG. 8 to FIG. 12 are schematic diagrams showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention. It is to be noted that the same components as the first preferred embodiment of the second preferred embodiment are denoted by the same reference numerals, and the materials and forming methods of the same components can be referred to the first preferred embodiment. As described, it will not be repeated here. As shown in FIG. 8, the preferred embodiment first provides a semiconductor substrate 200, such as a bulk substrate having a plurality of STIs 204.

Please continue to see Figure 8. Next, a patterned hard mask (not shown) is formed on the semiconductor substrate 200, followed by an etching process for removing a portion of the semiconductor material on the semiconductor substrate 200 to form at least one pattern on the semiconductor substrate 200. The semiconductor layer 206, the patterned semiconductor layer 206 is a fin portion including at least one multi-gate transistor element as shown in FIG. The fin portion has a width and a height, and the width has a ratio to the height, and the ratio may be 1:1.5 to 1:2.

Please still refer to Figure 8. Next, a gate dielectric layer 210 and a gate layer 212 covering a portion of the patterned semiconductor layer 206 are formed on the semiconductor substrate 200 in accordance with the steps described in the foregoing embodiments. In addition, as shown in FIG. 7, the gate dielectric layer 210 and the gate layer 212 extend in a direction perpendicular to the extending direction of the patterned semiconductor layer 206, and the gate dielectric layer 210 and the gate layer 212 cover the portion. The sidewalls of the semiconductor layer 206 are patterned. In addition, after the fabrication of the gate dielectric layer 210 and the gate layer 212 is completed, the preferred embodiment forms a source/drain extension region (not shown) in the patterned semiconductor layer 206.

As shown in FIG. 8, after the fabrication of the source/drain extension regions is completed, the preferred embodiment forms a composite insulating layer 320 on the semiconductor substrate 200, and the composite insulating layer 320 covers the patterned semiconductor layer 206. The hard mask 214 and the gate layer 212 are patterned. The difference in the first preferred embodiment is that the composite insulating layer 320 is a tri-layered structure in the preferred embodiment, and is further disposed between the first insulating layer 322 and the second insulating layer 3224. A third insulating layer 326. The etching rate of the first insulating layer 322 and the second insulating layer 324 is different from the etching rate of the third insulating layer 326, and the etching rates of the first insulating layer 322 and the second insulating layer 324 may also be different. For example, the first insulating layer 322 may include a tantalum nitride layer, the third insulating layer 326 includes a tantalum oxide layer, and the second insulating layer 324 may include a tantalum nitride layer, and is preferably doped with a carbon. (carbon-doped) tantalum nitride layer. In addition, the first insulating layer 322 and the third insulating layer 326 of the preferred embodiment are preferably a conformal film layer having uniform coverage formed by an atomic layer deposition method, and the total thickness thereof is about not more than 100 nm. The second insulating layer 324 may be a tantalum nitride film layer formed by a chemical vapor deposition method, and has a thickness of about 200 nm to 300 nm. It can be seen that the composite insulating layer 320 provided by the preferred embodiment is a NON structural layer comprising tantalum nitride-yttria-yttrium nitride. However, the composite insulating layer 320 may also be an ONO structural layer comprising hafnium oxide-tantalum nitride-yttria.

Please refer to Figure 9. Removing a portion of the composite insulating layer 320, for example, etching the second insulating layer 324 by an anisotropic dry etching method to form a first sidewall spacer 330 around the patterned hard mask 214 and the gate layer 212. A second sidewall 332 is formed around the patterned semiconductor layer 206. As described above, since the sum of the height of the patterned hard mask 214, the gate layer 212, and the gate dielectric layer 210 is approximately double that of the patterned semiconductor layer 206, the patterned semiconductor is etched according to the etching characteristics of the dry etching method. The second sidewall sub-332 around the layer 206 is automatically smaller than the first sidewall sub-330 when formed. As shown in FIG. 9, the width a of the first side wall sub-330 is always greater than the width b of the second side wall sub-332. In addition, when the first sidewall spacer 330 and the second sidewall spacer 332 are formed, a portion of the composite insulating layer 320 is simultaneously exposed, that is, a portion of the third insulating layer 326 is exposed.

Please refer to Figure 10. Next, the second sidewall spacer 332 may be removed by an isotropic wet etching method to expose a portion of the composite insulating layer 320, that is, the third insulating layer 326 exposing the composite insulating layer 320. In addition, the wet etching method removes a portion of the first sidewalls 330 at the same time to form a third sidewall 334 around the patterned hard mask 214 and the gate layer 212, and the third sidewall 334 is smaller than the first sidewall. 330. It is noted that the third insulating layer 326 and the first insulating layer 322 still cover the patterned semiconductor layer 206, the patterned hard mask 214 and the gate layer 212 when the second sidewall 332 is removed by the wet etching method. Therefore, the patterned semiconductor layer 206 and the gate layer 212 are covered and protected by the third insulating layer 326 and the first insulating layer 322, and any influence in the wet etching method can be avoided.

Please refer to Figure 11. Next, the exposed composite insulating layer 320 may be removed by another isotropic wet etching method, that is, the third insulating layer 326 is removed to expose the first insulating layer 322, and the first insulating layer 322 is exposed. The partially patterned semiconductor layer 206 and the partially patterned hard mask 214 are still covered. Due to the difference in etching rate, the outline of the third sidewall sub-334 is not affected when the second insulating layer 324 is removed.

Please refer to Figure 12. Subsequently, the exposed first insulating layer 322 is removed by another isotropic wet etching method to expose the patterned semiconductor layer 206, and the third sidewall 334 includes the first insulating layer 322 and the third insulating layer. Layer 326 and second insulating layer 324. It should be noted that since the first insulating layer 322 is a thin conformal film layer and the etching rate thereof is different from the third insulating layer 326, when the first insulating layer 322 is removed, the third sidewall is removed. The effect of sub-324 contours can be minimized. In addition, since the first insulating layer 322 is a thin conformal film layer, it can be easily removed without affecting the patterned semiconductor layer 206. Finally, when the first insulating layer 322 and the patterned hard mask 214 comprise the same material (for example, tantalum nitride), part of the patterned hard mask 214 can be removed in the wet etching method, thereby reducing the pattern. The sum total height of the hard mask 214 and the gate layer 212.

After the first insulating layer 322 is removed to expose the patterned semiconductor layer 206, a selective epitaxial growth process can be performed as described in the first preferred embodiment to form an epitaxial layer on the surface of the patterned semiconductor layer 206. (shown in Figure 7) 208. In addition, in the SEG process, a material having a lattice constant different from the lattice constant of the patterned semiconductor layer 206 may be added according to the conductivity type of the multi-gate transistor element, and at the same time, the conductive is added during, before, or after the SEG process. The doping of the type can complete the fabrication of the source/drain of the multi-gate transistor element, and at the same time complete the fabrication of the multi-gate transistor element 240 provided by the preferred embodiment.

The method for fabricating the multi-gate transistor according to the preferred embodiment can be performed by the first insulating layer 322 and the third insulating layer 326 when the desired sidewalls are formed by different etching rates. As a protective layer, the outline of the semiconductor layer 206 is patterned. In addition, if the thickness of the protective layer is low, the bottom of the film layer may be etched inwardly when the composite insulating layer is removed, causing damage to the sidewalls or even the gate layer 212. Therefore, the preferred embodiment further provides a plurality of insulating layers, for example, by using the first insulating layer 322 and the third insulating layer 326 having different etching rates to reduce the inward etching of the bottom portion. Finally, the first insulating layer 322 is removed without affecting the outline of the patterned semiconductor layer 206, so that the sidewalls and the top of the patterned semiconductor layer 206 are exposed. In other words, the preferred embodiment can also increase the exposed area of the patterned semiconductor layer 206, thereby increasing the growth of the epitaxial layer 208 in the subsequent SEG process. Therefore, after the SEG process, the top and sidewalls of the patterned semiconductor layer 206 are increased by the presence of the epitaxial layer 208, that is, the source/drain is increased, so that the resistance of the source/drain of the FinFET can be reduced and improved. Subsequent contact tolerance process for process tolerance.

In addition, the method for fabricating the multi-gate transistor component provided by the present invention can be used to fabricate a tri-gate transistor component as shown in FIG. 7, but can also be used to fabricate a double gate (double). -gate) transistor component.

In summary, the multi-gate transistor device according to the present invention is fabricated by using a composite insulating layer as a protective layer, thereby ensuring the underside when removing the sidewall covering the patterned semiconductor. The patterned semiconductor layer is not damaged. Therefore, the multi-gate transistor component provided by the present invention can be removed before the patterned semiconductor profile is affected, and the patterned semiconductor layer is exposed on the semiconductor substrate to increase the subsequent selective epitaxial growth process. The area in which the crystal layer grows eventually reaches the goal of reducing the source/drain resistance of the FinFET. At the same time, since the epitaxial layer grows on the exposed patterned semiconductor layer, the surface area of the source/drain can be increased, which is more favorable for improving the process tolerance of the subsequent contact plug process.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Fin field effect transistor component

102. . . Covering the insulating substrate 102

104. . . High dielectric constant insulating layer

106. . . Gate

108. . . Source/bungee

200. . . Semiconductor substrate

202. . .矽 base

204. . . Bottom oxide layer

206. . . Patterned semiconductor layer

208. . . Epitaxial layer

210. . . Gate dielectric layer

212. . . Gate layer

214. . . Patterned hard mask

220. . . Composite insulation

222. . . First insulating layer

224. . . Second insulating layer

230. . . First side wall

232. . . Second side wall

234. . . Third side wall

240. . . Multi-gate transistor

320. . . Composite insulation

322. . . First insulating layer

324. . . Second insulating layer

326. . . Third insulating layer

330. . . First side wall

332. . . Second side wall

334. . . Third side wall

a. . . First side wall width

b. . . Second side wall width

Figure 1 is a perspective view of a conventional FinFET device.

2 to 7 are schematic views of a first preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention, wherein FIG. 2 to FIG. 6 are the edges of FIG. A section of the A-A' tangent line.

8 to 12 are schematic views showing a second preferred embodiment of a method for fabricating a multi-gate transistor device according to the present invention.

200. . . Semiconductor substrate

202. . .矽 base

204. . . Bottom oxide layer

206. . . Patterned semiconductor layer

210. . . Gate dielectric layer

212. . . Gate layer

214. . . Patterned hard mask

222. . . First insulating layer

234. . . Third side wall

Claims (15)

A method of fabricating a multi-gate transistor device, comprising: providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer formed thereon, and the gate dielectric layer and the gate dielectric layer The gate layer covers a portion of the patterned semiconductor layer; forming a composite insulating layer over the semiconductor substrate, the composite insulating layer covering the patterned semiconductor layer and the gate layer, and the composite insulating layer includes at least one from bottom to top a first insulating layer, a second insulating layer and a third insulating layer, and the third insulating layer is formed between the first insulating layer and the second insulating layer; performing a first etching process for removing a portion of the composite insulating layer, a first sidewall is formed around the gate layer, and a second sidewall is formed around the patterned semiconductor layer; and a second etching process is performed to remove the second sidewall And simultaneously removing a portion of the first sidewall to form a third sidewall around the gate layer while exposing a portion of the third insulating layer, and the third insulating layer covers the portion of the pattern semiconductor Performing a third etching process for removing the exposed third insulating layer to expose the first insulating layer of the composite insulating layer, and the first insulating layer covers a portion of the patterned semiconductor layer; The exposed first insulating layer is removed to expose the patterned semiconductor layer. The manufacturing method of claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate. The manufacturing method of claim 1, wherein the gate dielectric layer comprises a high dielectric constant material. The manufacturing method of claim 1, wherein the composite insulating layer is in the manufacturing method of the first aspect, wherein the first sidewall is larger than the second sidewall. The manufacturing method of claim 1, wherein an etching rate of the first insulating layer is different from an etching rate of the second insulating layer. The manufacturing method of claim 5, wherein the first insulating layer comprises tantalum nitride and the second insulating layer comprises tantalum oxide. The manufacturing method of claim 1, wherein one of the first insulating layers has a thickness of 50-100 angstroms. The manufacturing method of claim 1, wherein the first etching process comprises an anisotropic etching process. The manufacturing method of claim 1, wherein an etching rate of the first insulating layer and the second insulating layer is different from an etching rate of the third insulating layer. The manufacturing method of claim 9, wherein the first insulating layer and the second insulating layer comprise tantalum nitride, and the third insulating layer comprises tantalum oxide. The manufacturing method of claim 1, wherein the first insulating layer and the third insulating layer have a thickness, and the thickness is not more than 100 angstroms. The manufacturing method of claim 1, wherein the first etching process is performed to form the first sidewall and the second sidewall simultaneously exposing a portion of the second insulating layer. The manufacturing method of claim 1, wherein the second etching process and the third etching process respectively comprise an isotropic etching process. The manufacturing method of claim 1, wherein the third sidewall includes the first insulating layer, the second insulating layer and the third insulating layer. The manufacturing method of claim 1, further comprising forming an epitaxial layer in the patterned semiconductor layer after exposing the patterned semiconductor layer Source / bungee.