TWI514039B - Pixel structure - Google Patents

Description

Pixel structure

The present invention relates to a pixel structure, and more particularly to a pixel structure having a spacer.

With the advancement of technology, the huge cathode ray tube (CRT) display has gradually entered history. Therefore, a liquid crystal display (LCD), an organic light emitting diode display (OLED display), an electrophoretic display (EPD), a plasma display panel (PDP) Display panels are gradually becoming the mainstream of future displays.

The conventional liquid crystal display may include a plurality of spacers disposed between the pixel array substrate and the opposite substrate, and the active element arrangement of the corresponding pixel array substrate. Since the active component (for example, a thin film transistor) is a multi-layered structure, a part of the spacer is compressed by the active component at the contact of the spacer with the active component. Moreover, as the component size continues to shrink, the alignment between the spacer and the active component is more difficult. For example, when the spacers are disposed on the opposite substrate, the alignment of the pixel array substrate and the opposite substrate is likely to cause a registration error. When the spacer is placed in the painting When it is on the array substrate, the alignment of the yellow mask during exposure and development is also likely to cause alignment error. When there is a registration error between the spacer and the active component (for example, the spacer moves up, down, or rotates), the overlap area between the spacer and the region with the highest height of the active component changes with the offset of the spacer. Therefore, it is easy to make the compressive force received by the spacer substantially different, which leads to instability of the structure of the spacer and unevenness of the pressure resistance in different regions of the liquid crystal display.

The present invention provides a pixel structure that allows uniform regions of the display panel to have a uniform withstand voltage.

The present invention provides a pixel structure including a data line, a scan line, an active element, a pixel electrode, and a spacer. The active component is electrically connected to the data line and the scan line, and the active component includes a gate, a channel layer, a source, and a drain, wherein the gate, the channel layer, and the overlap of the source or the drain in the vertical projection direction are An area. The pixel electrode is electrically connected to the drain. The spacer corresponds to the active component arrangement, wherein the spacer covers the first region of the active component, the spacer has a first edge and a second edge disposed opposite to each other, and the first edge and the second edge are located outside the first region.

Based on the above, in the pixel structure of the present invention, when there is a registration error between the spacer and the active element, the overlapping area between the spacer of the pixel structure and the region of the highest height of the active element does not follow the spacer. When the offset is changed, the compressive force received by the spacer is substantially a fixed value, so that the structure of the spacer can be stabilized and different regions of the display panel have a uniform withstand voltage.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ pixel array substrate

12, 22‧‧‧ substrate

14‧‧‧ pixel array

20‧‧‧ opposite substrate

24‧‧‧electrode layer

30‧‧‧Display media

50‧‧‧ display panel

100, 100’‧‧‧ pixel structure

104, 106‧‧‧Insulation

108‧‧‧Contact window

110‧‧‧First area

120‧‧‧Second area

130‧‧‧ Third Area

140, 140’ ‧ ‧ spacers

140a‧‧‧ first edge

140b‧‧‧ second edge

140c, 140c’‧‧‧ third edge

140d, 140d’‧‧‧ fourth edge

CH‧‧‧ channel layer

D‧‧‧汲

D1, d2, d3, d4‧‧‧ shortest distance

DL‧‧‧ data line

G‧‧‧ gate

PE‧‧‧ pixel electrode

R‧‧‧ area

S‧‧‧ source

SL‧‧‧ scan line

T‧‧‧ active components

I-I’, II-II’‧‧‧ line

1 is a schematic cross-sectional view of a display panel in accordance with the present invention.

2A is a top plan view of a pixel structure in accordance with a first embodiment of the present invention.

Fig. 2B is an enlarged schematic view of a region R of Fig. 2A.

Figure 2C is a top plan view of the spacer of Figure 2B with a registration error between the active elements.

Figure 3 is a cross-sectional view of the active element taken along line I-I' of Figure 2B.

Figure 4 is a schematic cross-sectional view of the active element taken along line II-II' of Figure 2B.

5A and 5B are top schematic views of the pixel structure when the shape of the spacer and the channel layer are different.

Figure 6A is a top plan view of a pixel structure in accordance with a second embodiment of the present invention.

Fig. 6B is an enlarged schematic view of a region R of Fig. 6A.

Figure 7 is a cross-sectional view of the active element taken along line I-I' of Figure 6B.

Figure 8 is a cross-sectional view of the active element taken along line II-II' of Figure 6B.

1 is a schematic cross-sectional view of a display panel in accordance with the present invention. Referring to FIG. 1 , the display panel 50 includes a pixel array substrate 10 , a counter substrate 20 , and a display medium. 30. The display panel 50 is, for example, a liquid crystal display panel or other form of display panel.

The pixel array substrate 10 includes a substrate 12 and a pixel array 14. The material of the substrate 12 may be glass, quartz, organic polymer or metal or the like. The pixel array 14 is disposed on the substrate 12, and the pixel array 14 includes a plurality of pixel structures. The design of the pixel structure will be described in detail later.

The opposite substrate 20 is located on the opposite side of the pixel array substrate 10. The opposite substrate 20 includes a substrate 22 and an electrode layer 24. The material of the substrate 22 may be glass, quartz or an organic polymer or the like. The electrode layer 24 is entirely covered on the substrate 22. The electrode layer 24 is a transparent conductive layer made of a metal oxide such as indium tin oxide or indium zinc oxide.

The display medium 30 is located between the pixel array substrate 10 and the opposite substrate 20. When the display panel 50 is a liquid crystal display panel, the display medium 30 is, for example, liquid crystal molecules.

2A is a top plan view of a pixel structure in accordance with a first embodiment of the present invention, FIG. 2B is an enlarged schematic view of a region R of FIG. 2A, and FIG. 2C is a alignment error between the spacer and the active device of FIG. 2B. FIG. 3 and FIG. 4 are schematic cross-sectional views of the active elements along line II' and line II-II' in FIG. 2B, respectively. In order to clearly illustrate an embodiment of the present invention, FIGS. 2A through 4 depict only one of the pixel structures of the pixel array 14 of FIG. 1, and those skilled in the art will appreciate that the pixel array 14 of FIG. 1 is actually That is, it is composed of a plurality of pixel structures as shown in FIG. 2A to FIG.

Referring to FIG. 2A to FIG. 4 simultaneously, the pixel structure 100 includes a data line DL, a scan line SL, an active device T, a pixel electrode PE, and a spacer 140.

The data line DL and the scan line SL are located on the substrate 12. The data line DL is different from the extending direction of the scanning line SL. It is preferable that the extending direction of the data line DL is perpendicular to the extending direction of the scanning line SL. In addition, the data line DL and the scan line SL are different in the film layer, and an insulating layer (not shown) is interposed therebetween. The data line DL and the scan line SL are mainly used to transmit a driving signal for driving the pixel structure 100. The data line DL and the scan line SL are generally made of a metal material. However, the invention is not limited thereto. According to other embodiments, the data line DL and the scan line SL may also use other conductive materials such as an alloy, an oxide of a metal material, a nitride of a metal material, an oxynitride of a metal material, or a metal material and other conductive materials. Stack layers.

The active device T is located on the substrate 12, and the active device T is electrically connected to the data line DL and the scan line SL. Here, the active element T is, for example, a thin film transistor comprising a gate G, a channel layer CH, a source S and a drain D. The gate G is electrically connected to the scan line SL, and the source S is electrically connected to the data line DL. In other words, when the control signal is input to the scan line SL, the scan line SL and the gate G are electrically connected; when the control signal is input to the data line DL, the data line DL is electrically connected to the source S. The channel layer CH is located above the gate G and below the source S and the drain D. The active device T of the present embodiment is described by taking a bottom gate type thin film transistor as an example, but the present invention is not limited thereto. In other embodiments, the active device T can also be a top gate type thin film transistor.

In the present embodiment, the active device T has a first region 110, a second region 120, and a third region 130. The first region 110 is an overlapping portion of the gate G, the channel layer CH, and the source S or the drain D in the vertical projection direction. That is, the first area 110 is the highest height region of the active component T. The second region 120 is an overlapping portion of the gate G and the source S or the drain D in the vertical projection direction. The third region 130 is an overlapping portion of the gate G and the channel layer CH in the vertical projection direction.

The gate G of the active device T is further covered with an insulating layer 104, which may also be referred to as a gate insulating layer. In addition, another insulating layer 106 may be further covered on the active device T, which may also be referred to as a protective layer. The material of the insulating layer 104 and the insulating layer 106 is, for example, an inorganic material, an organic material, or a combination thereof. The inorganic material is, for example, a stacked layer including cerium oxide, cerium nitride, cerium oxynitride or at least two of the above materials.

The pixel electrode PE is electrically connected to the drain D of the active device T. In more detail, the pixel electrode PE can be electrically connected to the drain D of the active device T through the contact window 108, wherein the contact window 108 passes through the insulating layer 106. The pixel electrode PE is, for example, a transparent conductive layer comprising a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide, or other suitable oxide. Or a stacked layer of at least two of the above.

The spacer 140 is disposed between the pixel array 14 of the pixel array substrate 10 and the electrode layer 24 of the opposite substrate 20. In the embodiment, the spacers 140 are first formed on the opposite substrate 20, and then the pixel array substrate 10 and the opposite substrate 20 are assembled such that the spacers 140 are located on the pixel array substrate 10 and the opposite substrate 20. However, the invention is not limited thereto. In other embodiments, the spacers 140 may be formed on the pixel array substrate 10 first, and then the pixel array substrate 10 and the opposite substrate 20 may be assembled. Furthermore, the spacer 140 is disposed corresponding to the active device T, wherein the spacer 140 covers at least the first region 110 of the active device T. The material of the spacer 140 is, for example, a photoresist or His suitable material. In this embodiment, the spacers 140 are rectangular spacers, and the channel layer CH is a rectangular channel layer. Therefore, the spacer 140 has two short sides and two long sides. The two short sides are a first edge 140a and a second edge 140b, and the two long sides are a third edge 140c and a fourth edge 140d.

The first edge 140a and the second edge 140b extend substantially in the same direction as the data lines DL and are parallel to each other. The first edge 140a is disposed opposite the second edge 140b, and the first edge 140a and the second edge 140b are located outside the first region 110. In more detail, in the present embodiment, the first edge 140a does not overlap the source S and does not overlap the second region 120, and the second edge 140b overlaps the drain D and does not overlap the second region 120. However, the invention is not limited thereto. In other embodiments, the first edge 140a may overlap with the source S (or the data line DL) and not overlap with the second region 120, and the second edge 140b overlaps with the drain D and not with the second region 120. overlapping. Furthermore, the shortest distances d1 and d2 between the first edge 140a and the second edge 140b of the spacer 140 and the second region 120 of the active device T are each 1 μm or more. However, the invention is not limited thereto. In other embodiments, the shortest distances d1 and d2 may be other values as long as the shortest distances d1 and d2 are at least larger than the alignment error values of the spacer 140 and the active device T.

The third edge 140c and the fourth edge 140d extend along the extending direction of the scanning line SL and are parallel to each other. The third edge 140c and the fourth edge 140d are orthogonal to the long sides of the channel layer CH. The third edge 140c is disposed opposite to the fourth edge 140d, and the third edge 140c and the fourth edge 140d are located outside the first region 110. In more detail, the third edge 140c and the fourth edge 140d are located in the third region 130. The spacer 140 partially covers the channel layer CH, and the third edge 140c overlaps the fourth edge 140d with the channel layer CH. Furthermore, the shortest distances d3 and d4 between the third edge 140c and the fourth edge 140d of the spacer 140 and the first region 110 of the active device T are each 1 μm or more. However, the invention is not limited thereto. In other embodiments, the shortest distances d3 and d4 may be other values as long as the shortest distances d3 and d4 are at least larger than the alignment error values of the spacers 140 and the active device T. Further, the shortest distances d1, d2, d3, and d4 described above may be the same or different, and the present invention is not particularly limited. That is, in the present embodiment, the spacer 140 covers at least the first region 110 of the active device T (that is, the region where the height of the active device T is the highest). Moreover, the first edge 140a, the second edge 140b, the third edge 140c, and the fourth edge 140d of the spacer 140 are all located outside the first region 110, and the edge and the first region 110 have the shortest distance d1, respectively. D2, d3 and d4, wherein the shortest distances d1, d2, d3 and d4 are at least larger than the alignment error value of the spacer 140 and the active element T.

It is worth mentioning that, in this embodiment, when there is a registration error between the spacer 140 and the active device T (for example, the spacer 140 moves up, down, or rotates), the spacer 140 and the active device T The overlapping area of the first region 110 (i.e., the region of the highest height of the active device T) may substantially maintain a fixed value, wherein the overlapping area is the same as the area of the first region 110. That is, the area where the spacer 140 is compressed by the first region 110 of the active device T can substantially maintain a fixed value, wherein the area where the spacer 140 is compressed by the first region 110 of the active device T is also the overlap described above. area.

For example, FIG. 2C is the spacer 140 and the active device T of FIG. 2B. A schematic diagram of the top view with a misalignment between the two. The embodiment of FIG. 2C is similar to the embodiment of FIG. 2B described above, and thus the same or similar elements are designated by the same or similar symbols and the description is not repeated. As shown in FIG. 2C, when there is a registration error between the spacer 140 and the active device T to cause the spacer 140 to be shifted downward, the overlapping area of the spacer 140 of FIG. 2C and the first region 110 (ie, The area of the first region 110 is substantially equal to the overlap area of the spacer 140 and the first region 110 of FIG. 2B (without the alignment error) (ie, the area of the first region 110). That is, the present invention has an optimized spacer 140 design such that the overlap area between the spacer 140 of the pixel structure 100 and the region of the highest height of the active device T (i.e., the first region 110) It does not change with the offset of the spacer 140, so that the structure of the spacer 140 can be stabilized and different regions of the display panel 50 have a uniform withstand voltage.

It is also worth mentioning that the shape of the spacer 140 and the channel layer CH is not limited to a rectangle. In other embodiments, the spacers 140 and the channel layers CH may each be rectangular, square, trapezoidal, polygonal, irregular, or other suitable shape. For example, FIGS. 5A and 5B are top plan views of the pixel structure 100 when the shape of the spacer 140 and the channel layer CH are different. The embodiment of Figures 5A and 5B is similar to the embodiment of Figure 2A described above, and therefore the same or similar elements are designated by the same or similar symbols and the description is not repeated. As shown in FIG. 5A, the spacers 140 may be rectangular and the channel layer CH may be polygonal. As shown in FIG. 5B, the spacers 140 may be polygonal and the channel layer CH may be rectangular. Therefore, the shape of the spacer 140 and the shape of the channel layer CH may be the same or different various shapes as long as the overlapping area of the spacer 140 and the first region 110 when there is a registration error between the spacer 140 and the active device T essentially You can maintain a fixed value.

6A is a top plan view of a pixel structure in accordance with a second embodiment of the present invention, FIG. 6B is an enlarged schematic view of a region R of FIG. 6A, and FIGS. 7 and 8 are lines I-I' and lines along FIG. 6B, respectively. A schematic cross-sectional view of the active element of II-II'. The embodiments of Figures 6A through 8 are similar to the above-described embodiments of Figures 2A through 4, and therefore the same or similar elements are designated by the same or similar symbols and the description is not repeated.

Referring to FIG. 6A to FIG. 8 simultaneously, the embodiment of FIGS. 6A to 8 is different from the embodiment of FIG. 2A to FIG. 4 in that the third edge 140c' of the spacer 140' is located at the same time as the fourth edge 140d'. Outside the channel layer CH. In more detail, in the pixel structure 100', the spacer 140' completely covers the channel layer CH, and the third edge 140c' and the fourth edge 140d' do not overlap with the channel layer CH.

It is worth mentioning that, in this embodiment, when there is a registration error between the spacer 140' and the active device T (for example, the spacer 140' moves up, down, or rotates), the spacer 140' and the active The overlapping area of the first region 110 of the component T (i.e., the region of the highest height of the active component T) may substantially maintain a fixed value, wherein the overlapping area is the same as the area of the first region 110. That is, the area of the spacer 140' compressed by the first region 110 of the active device T can be substantially maintained at a fixed value, wherein the area of the spacer 140' compressed by the first region 110 of the active device T is also The overlapping area. That is, the present invention has an optimized spacer 140' design such that the spacer 140 of the pixel structure 100' is between the region of the highest height of the active device T (i.e., the first region 110). The overlap area does not change with the offset of the spacer 140, so that the structure of the spacer 140 can be stabilized and the display panel 50 Different areas have a uniform pressure resistance.

In summary, in the pixel structure of the present invention, the spacer covers at least the first region of the active device (ie, the region with the highest height of the active component), and the first edge and the second edge of the spacer are located at the Outside the area. Therefore, when there is a registration error between the spacer and the active element, the compressive force received by the spacer is substantially a fixed value. That is, the present invention has an optimized spacer design such that the area of overlap between the spacer of the pixel structure and the region of the highest height of the active element does not change with the offset of the spacer, and thus The structure of the spacer is stabilized and different regions of the display panel have a uniform withstand voltage.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧First area

120‧‧‧Second area

130‧‧‧ Third Area

140‧‧‧Interval

140a‧‧‧ first edge

140b‧‧‧ second edge

140c‧‧‧ third edge

140d‧‧‧ fourth edge

CH‧‧‧ channel layer

D‧‧‧汲

D1, d2, d3, d4‧‧‧ shortest distance

G‧‧‧ gate

R‧‧‧ area

S‧‧‧ source

T‧‧‧ active components

I-I’, II-II’‧‧‧ line

Claims (14)

A pixel structure includes: a data line and a scan line; an active component electrically connected to the data line and the scan line, and the active component includes a gate, a channel layer, a source, and a drain a pole, wherein the gate, the channel layer, and the overlapping portion of the source or the drain in the vertical projection direction is a first region, a pixel electrode electrically connected to the gate; and a spacer, Corresponding to the active component arrangement, wherein the spacer covers the first region of the active component, the spacer has a first edge and a second edge disposed opposite to each other, the first edge and the second edge are located at the first Outside the region, the spacer has a third edge and a fourth edge disposed opposite to each other, and the third edge and the fourth edge are located outside the first region. The pixel structure of claim 1, wherein the gate and the overlapping portion of the source and the drain in the vertical projection direction are a second region, the second edge of the spacer and the The bungee overlaps and does not overlap with the second region. The pixel structure of claim 1, wherein the gate and the overlapping portion of the channel layer in the vertical projection direction are a third region, and the third edge and the fourth edge are located at the third region. In the area. The pixel structure of claim 3, wherein the spacer partially covers the channel layer, and the third edge and the fourth edge overlap the channel layer. The pixel structure as described in claim 1, wherein the third edge Simultaneously with the fourth edge is located outside the channel layer. The pixel structure of claim 5, wherein the spacer completely covers the channel layer, and the third edge and the fourth edge do not overlap the channel layer. The pixel structure of claim 1, wherein the first edge of the spacer and the shortest distance between the second edge and the second region of the active device are respectively 1 μm or more. The pixel structure of claim 1, wherein the third edge of the spacer and the shortest distance between the fourth edge and the first region of the active device are each 1 μm or more. The pixel structure of claim 1, wherein the spacer and the channel layer are each rectangular, square, trapezoidal, polygonal or irregular. The pixel structure of claim 1, wherein the spacer comprises at least one long side, and the long side of the spacer and one long side of the channel layer are orthogonal to each other. The pixel structure of claim 10, wherein the spacer has two long sides, and the two long sides are substantially parallel to each other. The pixel structure of claim 11, wherein the spacer is a rectangular spacer, and the channel layer is a rectangular channel layer. The pixel structure of claim 1, wherein the spacer comprises at least one long side, the at least one long side extending along a direction in which the scan line extends. The pixel structure as described in claim 1, wherein the first side The edge and the second edge extend substantially in the same direction as the data line.