TWI511456B - Input buffer - Google Patents
Input buffer Download PDFInfo
- Publication number
- TWI511456B TWI511456B TW103101533A TW103101533A TWI511456B TW I511456 B TWI511456 B TW I511456B TW 103101533 A TW103101533 A TW 103101533A TW 103101533 A TW103101533 A TW 103101533A TW I511456 B TWI511456 B TW I511456B
- Authority
- TW
- Taiwan
- Prior art keywords
- transistor
- electrically connected
- pull
- circuit
- driving circuit
- Prior art date
Links
- 239000000872 buffer Substances 0.000 title claims description 34
- 101000631701 Homo sapiens Secretin receptor Proteins 0.000 description 4
- 102100028927 Secretin receptor Human genes 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Description
本發明係關於一種輸入緩衝器。The present invention is directed to an input buffer.
輸入緩衝器普遍地應用在各式各樣的數位電路中。輸入緩衝器有許多種類，其中單端輸入緩衝器具有一單端輸入信號，當該輸入信號傳送時若越過一預定電壓位準，則該輸入緩衝器會觸發。換言之，單端輸入緩衝器會比較該單端輸入信號和該預定電壓位準，因此當該輸入信號越過該預定電壓位準時，該輸入緩衝器的輸出端會產生一狀態變遷。其他種類的輸入緩衝器包含一互補輸入緩衝器，該互補輸入緩衝器接收一對互補輸入信號，當該對互補輸入信號的其中一者傳送時若越過該對互補輸入信號中的另一者時，則該輸入緩衝器的輸出端會產生一狀態變遷。Input buffers are commonly used in a wide variety of digital circuits. There are many types of input buffers, where the single-ended input buffer has a single-ended input signal that is triggered when a predetermined voltage level is crossed when the input signal is transmitted. In other words, the single-ended input buffer compares the single-ended input signal with the predetermined voltage level, so that when the input signal crosses the predetermined voltage level, the output of the input buffer produces a state transition. Other types of input buffers include a complementary input buffer that receives a pair of complementary input signals that pass over the other of the pair of complementary input signals when one of the pair of complementary input signals is transmitted , the output of the input buffer will produce a state transition.
輸入緩衝器經常使用於數位電路中以執行信號緩衝功能，例如提供高輸入阻抗以防止過大的負載耦接至輸入端。輸入緩衝器也可提供施加至內部電路之有條件的輸入信號，讓該等信號具有適當界定的邏輯位準和狀態變遷特 性。雖然有這些特質，輸入緩衝器也無法避免一些邊際效應。例如，輸入緩衝器用來做為延遲胞(delay cell)以在高速數位電路中傳遞信號時，當穿越點傾斜(skew)發生時，會有大電流發生。Input buffers are often used in digital circuits to perform signal buffering functions, such as providing high input impedance to prevent excessive loads from coupling to the input. The input buffer also provides conditional input signals that are applied to the internal circuitry to have appropriately defined logic levels and state transitions. Sex. Despite these qualities, the input buffer cannot avoid some marginal effects. For example, when an input buffer is used as a delay cell to transmit a signal in a high speed digital circuit, a large current occurs when a crossing point skew occurs.
據此，有必要提供一改良的輸入緩衝器以解決上述問題。Accordingly, it is necessary to provide an improved input buffer to solve the above problems.
本發明係提供一種輸入緩衝器。該輸入緩衝器包含一第一驅動電路，一第二驅動電路，一上拉電路以及一下拉電路。該第一驅動電路用以接收一第一輸入信號，藉以產生一輸出信號。該第二驅動電路用以驅動該輸出信號。該上拉電路用以選擇性地控制該第二驅動電路，藉以根據該第一輸入信號和一第二輸入信號以上拉該輸出信號。該下拉電路用以選擇性地控制該第二驅動電路，藉以根據該第一輸入信號和該第二輸入信號以下拉該輸出信號。當該上拉電路控制該第二驅動電路以上拉該輸出信號時，該下拉電路不會控制該第二驅動電路以下拉該輸出信號，而當該下拉電路控制該第二驅動電路以下拉該輸出信號時，該上拉電路不會控制該第二驅動電路以上拉該輸出信號。The present invention provides an input buffer. The input buffer includes a first driving circuit, a second driving circuit, a pull-up circuit and a pull-down circuit. The first driving circuit is configured to receive a first input signal to generate an output signal. The second driving circuit is configured to drive the output signal. The pull-up circuit is configured to selectively control the second driving circuit to pull the output signal according to the first input signal and a second input signal. The pull-down circuit is configured to selectively control the second driving circuit to pull the output signal according to the first input signal and the second input signal. When the pull-up circuit controls the second driving circuit to pull the output signal, the pull-down circuit does not control the second driving circuit to pull the output signal, and when the pull-down circuit controls the second driving circuit to pull the output During the signal, the pull-up circuit does not control the second driver circuit to pull the output signal.
100‧‧‧輸入緩衝器100‧‧‧Input buffer
102‧‧‧第一驅動電路102‧‧‧First drive circuit
1022‧‧‧P型電晶體1022‧‧‧P type transistor
1024‧‧‧N型電晶體1024‧‧‧N type transistor
104‧‧‧第二驅動電路104‧‧‧Second drive circuit
1042‧‧‧P型電晶體1042‧‧‧P type transistor
1044‧‧‧N型電晶體1044‧‧‧N type transistor
106‧‧‧上拉電路106‧‧‧ Pull-up circuit
1062‧‧‧P型電晶體1062‧‧‧P type transistor
1064‧‧‧N型電晶體1064‧‧‧N type transistor
108‧‧‧下拉電路108‧‧‧ Pulldown circuit
1082‧‧‧N型電晶體1082‧‧‧N type transistor
1084‧‧‧P型電晶體1084‧‧‧P type transistor
109‧‧‧控制電晶體109‧‧‧Control transistor
110‧‧‧反向器110‧‧‧ reverser
圖1顯示結合本發明一實施例之一輸入緩衝器的電路圖。1 shows a circuit diagram of an input buffer in conjunction with an embodiment of the present invention.
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有通常知識者應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。另外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those of ordinary skill in the art that manufacturers may refer to the same elements by different nouns. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
圖1顯示結合本發明一實施例之一輸入緩衝器100的電路圖。參照圖1，該輸入緩衝器100包括一第一驅動電路102，一第二驅動電路104，一上拉電路106，一下拉電路108，一控制電晶體109以及一反向器110。1 shows a circuit diagram of an input buffer 100 in accordance with one embodiment of the present invention. Referring to FIG. 1, the input buffer 100 includes a first driving circuit 102, a second driving circuit 104, a pull-up circuit 106, a pull-down circuit 108, a control transistor 109, and an inverter 110.
該第一驅動電路102係用以驅動一第一輸入信號SIN，藉以產生一輸出信號/SOUT，其中該信號/SOUT與該第一輸入信號SIN之相位相反。該第一驅動電路102根據該第一輸入信號SIN的電壓位準，以驅動該第一輸入信號SIN至一供應電源電壓Vdd或是一接地電壓GND。參照圖1，該第一驅動電路102包含一P型電晶體1022和一N型電晶體1024。該P型電 晶體1022具有電性連接至該供應電源電壓Vdd的源極，電性連接至該第一輸入信號SIN的閘極，和電性連接至該輸出信號/SOUT的汲極。該N型電晶體1024具有電性連接至該控制電晶體109之汲極的源極，電性連接至該第一輸入信號SIN的閘極，和電性連接至該輸出信號/SOUT的汲極。The first driving circuit 102 is configured to drive a first input signal SIN to generate an output signal /SOUT, wherein the signal /SOUT is opposite to the phase of the first input signal SIN. The first driving circuit 102 drives the first input signal SIN to a supply voltage Vdd or a ground voltage GND according to the voltage level of the first input signal SIN. Referring to FIG. 1, the first driving circuit 102 includes a P-type transistor 1022 and an N-type transistor 1024. The P type The crystal 1022 has a source electrically connected to the supply voltage Vdd, a gate electrically connected to the first input signal SIN, and a drain electrically connected to the output signal /SOUT. The N-type transistor 1024 has a source electrically connected to the drain of the control transistor 109, a gate electrically connected to the first input signal SIN, and a drain electrically connected to the output signal /SOUT .
在本實施例中，該控制電晶體109為一N型電晶體。該控制電晶體109具有電性連接至該接地電壓GND的源極，和電性連接至一控制信號SCTR的閘極，其中該控制電晶體109會由該控制信號SCTR所激發。該控制電晶體109負責控制該輸入緩衝器100中之該第一驅動電路102和該第二驅動電路104的激發。舉例而言，在本實施例中，一旦該控制信號SCTR由邏輯0位準轉換至邏輯1位準時，該第一驅動電路102和該第二驅動電路104會被激發，一旦該控制信號SCTR由邏輯1位準轉換至邏輯0位準時，該第一驅動電路102和該第二驅動電路104不會被激發。請注意該控制電晶體109僅用來例示本發明之一實施例，該控制電晶體109不應造成本發明不必要之限制。在本發明其他實施例中，該控制電晶體109可省略。在此狀況下，該N型電晶體1024的源極電性連接至該接地電壓GND。In this embodiment, the control transistor 109 is an N-type transistor. The control transistor 109 has a source electrically connected to the ground voltage GND, and a gate electrically connected to a control signal SCTR, wherein the control transistor 109 is excited by the control signal SCTR. The control transistor 109 is responsible for controlling the excitation of the first driver circuit 102 and the second driver circuit 104 in the input buffer 100. For example, in the embodiment, once the control signal SCTR is switched from the logic 0 level to the logic 1 level, the first driving circuit 102 and the second driving circuit 104 are excited, once the control signal SCTR is When the logic 1 bit transitions to the logic 0 bit, the first driver circuit 102 and the second driver circuit 104 are not activated. Please note that the control transistor 109 is only used to illustrate one embodiment of the present invention, and the control transistor 109 should not be unnecessarily limited by the present invention. In other embodiments of the invention, the control transistor 109 can be omitted. In this case, the source of the N-type transistor 1024 is electrically connected to the ground voltage GND.
此外，該反向器110係用以反向該輸出信號/SOUT，以獲得一非反向的輸出信號SOUT。請注意該反向器110僅用來例示本發明之一實施例，該反向器110係提供一反 向功能。在本發明其他實施例中，該反向器110可省略，或是以其他不背離本發明精神之元件替換。In addition, the inverter 110 is for reversing the output signal /SOUT to obtain a non-inverted output signal SOUT. Please note that the inverter 110 is only used to illustrate an embodiment of the present invention, and the inverter 110 provides an inverse To function. In other embodiments of the invention, the inverter 110 may be omitted or replaced with other components that do not depart from the spirit of the invention.
該第二驅動電路104係用以根據該上拉電路106和該下拉電路108的控制而驅動該輸出信號/SOUT至該供應電源電壓Vdd或是該接地電壓GND。該第二驅動電路104包含一P型電晶體1042和一N型電晶體1044。該P型電晶體1042具有電性連接至該供應電源電壓Vdd的源極，電性連接至該上拉電路106的閘極，和電性連接至該輸出信號/SOUT的汲極。該N型電晶體1044具有電性連接至該接地電壓GND的源極(如果該控制電晶體109導通)，電性連接至該下拉電路108的閘極，和電性連接至該輸出信號/SOUT的汲極。The second driving circuit 104 is configured to drive the output signal /SOUT to the supply power voltage Vdd or the ground voltage GND according to the control of the pull-up circuit 106 and the pull-down circuit 108. The second driving circuit 104 includes a P-type transistor 1042 and an N-type transistor 1044. The P-type transistor 1042 has a source electrically connected to the supply voltage Vdd, a gate electrically connected to the pull-up circuit 106, and a drain electrically connected to the output signal /SOUT. The N-type transistor 1044 has a source electrically connected to the ground voltage GND (if the control transistor 109 is turned on), is electrically connected to the gate of the pull-down circuit 108, and is electrically connected to the output signal /SOUT Bungee jumping.
該上拉電路106包含一P型電晶體1062和一N型電晶體1064。該P型電晶體1062具有電性連接至該供應電源電壓Vdd的源極，電性連接至一第二輸入信號/SIN的閘極，和電性連接至該第二驅動電路104中之該PMOS電晶體1042的汲極，其中，該第二輸入信號/SIN是由該輸入緩衝器100的外部所接收，且該第二輸入信號/SIN是由反向該第二輸入信號SIN得來。然而，由於電路不匹配或是一些非理想特性，該第二輸入信號/SIN並不完全是該第一輸入信號SIN的反向圖樣。亦即，可能有穿越點傾斜產生。該N型電晶體1064具有電性連接至該第二驅動電路104中之該PMOS電晶體1042的源極，電性連接至該第二輸入信號/SIN的閘極，和電性連接至該第一輸 入信號SIN的汲極。The pull-up circuit 106 includes a P-type transistor 1062 and an N-type transistor 1064. The P-type transistor 1062 has a source electrically connected to the supply voltage Vdd, is electrically connected to a gate of a second input signal /SIN, and is electrically connected to the PMOS in the second driver circuit 104. The drain of the transistor 1042, wherein the second input signal /SIN is received by the outside of the input buffer 100, and the second input signal /SIN is derived by reversing the second input signal SIN. However, due to circuit mismatch or some non-ideal characteristics, the second input signal /SIN is not exactly the reverse pattern of the first input signal SIN. That is, there may be a crossing point tilt. The N-type transistor 1064 has a source electrically connected to the PMOS transistor 1042 of the second driving circuit 104, is electrically connected to the gate of the second input signal /SIN, and is electrically connected to the first One lose Enter the drain of the signal SIN.
該下拉電路108包含一N型電晶體1082和一P型電晶體1084。該N型電晶體1082具有電性連接至該接地電壓GND的源極，電性連接至該第二輸入信號/SIN的閘極，和電性連接至該第二驅動電路104中之該NMOS電晶體1044的汲極。該P型電晶體1084具有電性連接至該第二驅動電路104中之該NMOS電晶體1044的汲極，電性連接至該第二輸入信號/SIN的閘極，和電性連接至該第一輸入信號SIN的源極。The pull-down circuit 108 includes an N-type transistor 1082 and a P-type transistor 1084. The N-type transistor 1082 has a source electrically connected to the ground voltage GND, is electrically connected to the gate of the second input signal /SIN, and is electrically connected to the NMOS device in the second driving circuit 104. The drain of the crystal 1044. The P-type transistor 1084 has a drain electrically connected to the NMOS transistor 1044 of the second driving circuit 104, is electrically connected to the gate of the second input signal /SIN, and is electrically connected to the first The source of an input signal SIN.
以下參照圖1描述本發明之該輸入緩衝器100之運作。在運作期間，當該上拉電路106控制該第二驅動電路104以上拉該輸出信號/SOUT時，該下拉電路108不會控制該第二驅動電路104以下拉該輸出信號/SOUT；而當該下拉電路108控制該第二驅動電路104以下拉該輸出信號/SOUT時，該上拉電路106不會控制該第二驅動電路104以上拉該輸出信號/SOUT。換言之，該上拉電路106和該下拉電路108之結合係確保該PMOS電晶體1042和該NMOS電晶體1044兩者一次僅有一者會觸發。因此，可避免該PMOS電晶體1042和該NMOS電晶體1044因同時導通所產生的大電流。The operation of the input buffer 100 of the present invention will be described below with reference to FIG. During operation, when the pull-up circuit 106 controls the second driving circuit 104 to pull the output signal /SOUT, the pull-down circuit 108 does not control the second driving circuit 104 to pull down the output signal /SOUT; When the pull-down circuit 108 controls the second driving circuit 104 to pull down the output signal /SOUT, the pull-up circuit 106 does not control the second driving circuit 104 to pull the output signal /SOUT. In other words, the combination of the pull-up circuit 106 and the pull-down circuit 108 ensures that only one of the PMOS transistor 1042 and the NMOS transistor 1044 can be triggered at a time. Therefore, the large current generated by the PMOS transistor 1042 and the NMOS transistor 1044 due to simultaneous conduction can be avoided.
請注意上述實施例中PMOS電晶體和NMOS電晶體之型態僅作為例示用，PMOS電晶體和NMOS電晶體之型態不應造成本發明不必要之限制。在本發明其他實施例中，其他型態的電晶體也可以使用以達成相同目的。Please note that the types of PMOS transistors and NMOS transistors in the above embodiments are for illustrative purposes only, and the types of PMOS transistors and NMOS transistors should not be unnecessarily limited by the present invention. In other embodiments of the invention, other types of transistors may be used to achieve the same purpose.
本發明之技術內容及技術特點已揭示如上，然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此，本發明之保護範圍應不限於實施例所揭示者，而應包括各種不背離本發明之替換及修飾，並為隨後之申請專利範圍所涵蓋。The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be
100‧‧‧輸入緩衝器100‧‧‧Input buffer
102‧‧‧第一驅動電路102‧‧‧First drive circuit
1022‧‧‧P型電晶體1022‧‧‧P type transistor
1024‧‧‧N型電晶體1024‧‧‧N type transistor
104‧‧‧第二驅動電路104‧‧‧Second drive circuit
1042‧‧‧P型電晶體1042‧‧‧P type transistor
1044‧‧‧N型電晶體1044‧‧‧N type transistor
106‧‧‧上拉電路106‧‧‧ Pull-up circuit
1062‧‧‧P型電晶體1062‧‧‧P type transistor
1064‧‧‧N型電晶體1064‧‧‧N type transistor
108‧‧‧下拉電路108‧‧‧ Pulldown circuit
1082‧‧‧N型電晶體1082‧‧‧N type transistor
1084‧‧‧P型電晶體1084‧‧‧P type transistor
109‧‧‧控制電晶體109‧‧‧Control transistor
110‧‧‧反向器110‧‧‧ reverser
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103101533A TWI511456B (en) | 2014-01-15 | 2014-01-15 | Input buffer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103101533A TWI511456B (en) | 2014-01-15 | 2014-01-15 | Input buffer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201528686A TW201528686A (en) | 2015-07-16 |
| TWI511456B true TWI511456B (en) | 2015-12-01 |
Family
ID=54198459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103101533A TWI511456B (en) | 2014-01-15 | 2014-01-15 | Input buffer |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI511456B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5377149A (en) * | 1992-07-24 | 1994-12-27 | Sgs-Thomson Microelectronics S.A. | Output precharge circuit for memory |
| US5698994A (en) * | 1994-07-29 | 1997-12-16 | Nkk Corporation | Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit |
| US6559678B1 (en) * | 2001-12-24 | 2003-05-06 | Nanoamp Solutions, Inc. | Node predisposition circuit |
| TWI285998B (en) * | 2002-06-27 | 2007-08-21 | Samsung Electronics Co Ltd | Data transmission circuit and method for reducing leakage current |
-
2014
- 2014-01-15 TW TW103101533A patent/TWI511456B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5377149A (en) * | 1992-07-24 | 1994-12-27 | Sgs-Thomson Microelectronics S.A. | Output precharge circuit for memory |
| US5698994A (en) * | 1994-07-29 | 1997-12-16 | Nkk Corporation | Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit |
| US6559678B1 (en) * | 2001-12-24 | 2003-05-06 | Nanoamp Solutions, Inc. | Node predisposition circuit |
| TWI285998B (en) * | 2002-06-27 | 2007-08-21 | Samsung Electronics Co Ltd | Data transmission circuit and method for reducing leakage current |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201528686A (en) | 2015-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101200452B1 (en) | Level shifter having low duty cycle distortion | |
| KR101290080B1 (en) | A pre-emphasis circuit and differential current signaling system having the same | |
| CN105049025A (en) | Low voltage differential signal drive circuit | |
| US20160285453A1 (en) | Driver using pull-up nmos transistor | |
| TWI815374B (en) | Level shifter | |
| JP2010283453A5 (en) | ||
| CN108604898A (en) | Input/Output (I/O) Drivers Implementing Dynamic Gate Biasing of Buffer Transistors | |
| KR102409872B1 (en) | Transmitter and Semiconductor Apparatus | |
| WO2019033340A1 (en) | Level translator capable of outputting positive and negative voltages | |
| CN105703761A (en) | Input/output driving circuit | |
| TWI511456B (en) | Input buffer | |
| TWI751363B (en) | Buffer circuit | |
| US7301386B2 (en) | Apparatus for improved delay voltage level shifting for large voltage differentials | |
| US9407243B1 (en) | Receiver circuit | |
| CN105306043B (en) | input buffer | |
| US9118320B2 (en) | Input buffer with current control mechanism | |
| KR20100133610A (en) | Voltage level shifter | |
| TWI630794B (en) | Level shifting circuit and integrated circuit | |
| US20120039134A1 (en) | Data output circuit in a semiconductor memory apparatus | |
| US9685952B2 (en) | Transmitter | |
| TWI907050B (en) | Voltage level shifter | |
| TWI475806B (en) | Off-chip driver | |
| JP2014168131A (en) | CMOS inverter circuit | |
| JP6697521B2 (en) | Memory device | |
| KR100604658B1 (en) | Voltage level shifter |