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TWI511291B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI511291B
TWI511291B TW101128723A TW101128723A TWI511291B TW I511291 B TWI511291 B TW I511291B TW 101128723 A TW101128723 A TW 101128723A TW 101128723 A TW101128723 A TW 101128723A TW I511291 B TWI511291 B TW I511291B
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semiconductor
epitaxial
region
strips
gate stack
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TW201338166A (zh
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林文傑
婁經雄
曾仁洲
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本發明係關於半導體製作，且特別是關於一種半導體裝置及其製造方法，以應用於靜電放電保護之相關應用。
由於靜電(static charges)的累積，於積體電路附近會產生極高電壓。於積體電路之一輸入端或一輸出端處便產生了一高勢能(high potential)。如此之高勢能可能由於某人觸摸了電性連結於上述輸出端或輸入端之一封裝接腳(package pin)而產生。當上述之靜電於放電時，將於此積體電路之封裝節點(package nodes)處產生了高電流。如此之現象稱為靜電放電(electrostatic discharge，ESD)。對於半導體裝置而言，靜電放電為一嚴重問題，其可能會毀壞整個積體電路。
由於靜電放電之瞬間電流時間非常短，通常約為幾個奈秒，而傳統之電路保護器無法快速地反應並提供適當保護。基於上述理由，便需要於積體電路內應用靜電放電保護元件(ESD device)。一般來說，可於封裝接腳之間耦接雙向二極體(bi-directional diode)以保護各個電路。亦可使用如電晶體之其他靜電放電保護元件。此些靜電放電保護元件亦廣泛地應用於電源導線(power line)之間，以保護耦接於此些電源導線之間的內部線路，並將靜電放電之電流釋放至接地端(ground)。
鰭型場效電晶體(FinFET)結構可作為靜電放電保護元件之用。為了使得形成靜電放電保護元件之製程可適用於 形成鰭型場效電晶體結構，可連結鰭型場效電晶體以形成靜電放電保護電路，其中靜電放電保護作用之鰭型場效電晶體的通道(channel)可用於傳導靜電放電電流之用。然而，上述方法面臨了眾多設計與製程問題。為了提供高的靜電放電保護能力，需要使用大量之鰭型場效電晶體，有時需要並聯多於10000個以上之鰭型場效電晶體。如此意謂著，當此些鰭型場效電晶體中之任一者崩潰(breakdown)時，便可能造成整個靜電放電保護電路的故障。故需使得所使用之此些場效電晶體的表現為一致(uniform)。
依據一實施例，本發明提供了一種半導體裝置，包括：複數個淺溝槽隔離區；複數個半導體條狀物，位於該些淺溝槽隔離區之間且相互平行；複數個半導體鰭狀物，位於該些半導體條狀物之上；一閘堆疊物，位於該些半導體鰭狀物之上並跨越該些半導體鰭狀物；以及一汲極磊晶半導體區，位於該閘堆疊物之一側且連結於該些半導體鰭狀物。於一實施例中，該汲極磊晶半導體區包括：一第一部，鄰接於該些半導體鰭狀物，其中該第一部為跨越並準直於該些第一半導體條狀物之一連續區；以及複數個第二部，較該第一部遠離該閘堆疊物，其中該些第二部分別位於該些半導體條狀物之上並準直於該些半導體條狀物，且其中該些第二部為相互平行的並為一介電材料所相分隔。
依據另一實施例，本發明提供了一種半導體裝置，包括：複數個淺溝槽隔離區；複數個半導體條狀物，位於該 些淺溝槽隔離區之間且相互平行；複數個半導體鰭狀物，位於該些半導體條狀物之上；一第一閘堆疊物以及一第二閘堆疊物，位於該些半導體鰭狀物之上並跨越該些半導體鰭狀物；以及一汲極磊晶半導體區，位於該第一閘堆疊物與該第二閘堆疊物之間，其中該汲極磊晶半導體區於鄰近該第一閘堆疊物與該第二閘堆疊物之複數個區域內形成連續之複數個汲極區，並於鄰近該第閘堆疊物一與該第二閘堆疊物之一中央部之一區內分成數個磊晶條狀物。
依據又一實施例，本發明提供了一種半導體裝置之製造方法，包括：施行一磊晶成長，以自複數個淺溝槽隔離區之間之複數個半導體條狀物處成長出複數個磊晶區；繼續施行該磊晶成長，其中鄰近於一閘堆疊物之該些磊晶區之數個第一部聚合成為一連續汲極磊晶區，而其中較該些第一區遠離該閘堆疊物之該些磊晶區之數個第二部則為相互分隔的；以及於該些磊晶區之該些第二部相互分隔時，形成一接觸插栓以電性連結該些磊晶區之該些第二部。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
於下文中揭示了依據本發明之適用於靜電放電保護應用之半導體裝置及其製造方法。於多個實施例中，主要揭示了應用鰭型場效電晶體(FinFET)之靜電放電保護(ESD)元件及其製造方法，以及繪示了靜電放電保護元件於製造 過程中之中間階段。於下文中亦討論了此些實施例之變化情形。於不同圖式與所繪示之實施例中，相同標號係代表了相同元件。
第1-5F圖為一系列立體圖、上視圖以及剖面圖，顯示了依據本發明之一實施例之一種靜電放電保護元件於其不同階段中之製造情形。第1圖繪示了一基板20之立體圖。於部份實施例中，基板20包括塊狀矽(bulk silicon)。或者，基板20包括塊狀矽鍺(bulk silicon germanium)或其他之半導體材料。基板20可摻雜有n型或p型摻質以形成一井區，其中上述井區之導電形態則依照所形成之鰭型場效電晶體以及靜電放電保護元件之類型而定。
於基板20內形成有複數個淺溝槽隔離(shallow trench isolation，STI)區22。於部份實施例中，此些淺溝槽隔離區22係藉由蝕刻基板20以形成數個凹口於其內，並接著於此些凹口內填入如高密度電漿氧化物(HDP oxides)、四乙基矽烷氧化物(TEOS oxide)或相似物等介電材料所形成。接著施行一化學機械研磨(CMP)製程，以移除介電材料之突出部份，而剩餘部份即為此些淺溝槽隔離區。介於淺溝槽隔離區22之間的基板20之數個部份於下文中將稱為半導體條狀物(semiconductor strips)24。接著，凹蝕此些淺溝槽隔離區22，使得此些淺溝槽隔離區22的頂面低於半導體條狀物24之頂面。半導體條狀物24之此些部分便高於淺溝槽隔離區22之頂面，因此形成了複數個半導體鰭狀物(semiconductor fins)26。
第2圖繪示了閘堆疊物(gate stack)30與32的形成，其 為相互平行的。此些閘堆疊物30與32分別形成於此些半導體鰭狀物26之數個側壁與頂面之上。此些閘堆疊物30與32分別包括一閘介電層34以及一閘電極35(未顯示於第2圖中，請參照第4B圖)。閘介電層34可包括常用之介電材料，例如為氧化物、氮化物、氮氧化物、如氧化鉭(Ta2 O5 )、氧化鋁(Al2 O3 )、氧化鉿(HfO)、氧化矽鈦(SiTiO3 )、氧化矽鉿(HfSiO)、氮氧矽鉿(HfSiON)、氮氧矽鋯(ZrSiON)之高介電常數介電材料，以及上述材料之組合。於某些實施例中，閘電極35可由多晶矽形成。或者，閘電極35可由其他常用之導電材料所形成，包括鎳、鈦、鉭、鉿或其組合、如矽化鎳、矽化鉬、矽化鉿、及其組合之金屬矽化物，以及如氮化鈦、氮化鉭、氮化鉿、氮鋁化鉿、氮化鉬、氮鋁化鎳、及其組合之金屬氮化物。
請繼續參照第2圖，閘堆疊物30之間之一距離D1係大於一距離D2，而此距離D2係為此些閘堆疊物30之一與其鄰近之閘堆疊物32之間的距離。於部份實施例中，D1/D2之比率可約大於7。於部份實施例中，此距離D1亦可大於約1微米。可以理解的是，於本文中所描述之尺寸僅做為範例之用，而其可為一任意值。
請參照第3圖，接著蝕刻未為閘堆疊物30與32所覆蓋之此些半導體鰭狀物26之數個部份。為閘堆疊物30與32所覆蓋之此些半導體鰭狀物26之數個部份則受到保護並大體並未被蝕刻。於部份實施例中，大體整個的移除了半導體鰭狀物26之未受到覆蓋之數個部份，而半導體條狀物24則未受到蝕刻。於其他實施例中，半導體鰭狀物26 之未覆蓋之數個部份之頂部經過蝕刻，而半導體鰭狀物26之未覆蓋部份之底部則未經過蝕刻，並接著自未經過蝕刻之半導體鰭狀物26之部份處施行磊晶成長。
接著，如第4A-4D圖所示，施行一選擇性磊晶成長以形成磊晶之半導體材料36，其自於半導體鰭狀物26或半導體條狀物24之露出表面處成長形成。第4A圖顯示了所形成結構之一立體圖。於本文中，介於每一閘堆疊物30及其鄰近之一閘堆疊物32之間的半導體材料36之一部係稱為源極磊晶區36A。而介於閘堆疊物30間之半導體材料36之一部則稱為汲極磊晶區36B。於部份實施例中，半導體材料36係由相同於基板20之材料所形成。於其他實施例中，半導體材料36係由不同於基板20之材料所形成。舉例來說，於p型鰭型場效電晶體之一種鰭型場效電晶體實施例中，半導體材料36可包括矽鍺(SiGe)。或者，於一n型鰭型場效電晶體之鰭型場效電晶體實施例中，半導體材料36可包括碳化矽(SiC)。
由於距離D1具有一較大數值，而如圖所示之介於閘堆疊物30間之元件區域佔據了相對大之晶片區域，因此汲極磊晶區36B之不同部份的成長速率(growth rate)之間存在有明顯差異。第4B圖繪示了沿第4A圖內線段4B-4B所示平面之一剖面圖。值得注意的是，雖然於第4A圖中所繪示之磊晶區36B之頂面具有步階情形(steps)，而於實際輪廓中，此些磊晶區36B之頂面的高度則逐漸地改變，如第4B圖所示。汲極磊晶區36B可具有碟狀輪廓(dishing profile)之一頂面，即為具有低於鄰近閘堆疊物30之其他部 之一中間部(其臨近於此些閘堆疊物30之中間部)。換句話，如第4B圖所示之剖面圖中，此些汲極磊晶部36B之第一部36B1具有一高度H1，其高於此些汲極磊晶部36B之第二部36B2所具有之一高度H2。此些第一部36B1鄰近於此些閘堆疊物30，而此些第二部36B2則位於此些閘堆疊物30之中間。從閘堆疊物30至此些閘堆疊物30之中心處，汲極磊晶區36B之頂面逐漸且持續地降低。
第4C與4D圖為第4A圖內所示結構之一系列剖面圖，分別顯示了橫跨第4A圖內線段4C-4C與4D-4D之一平面之剖面情形。請參照第4C圖，由於磊晶成長包括了垂直成長與水平成長，因此自各半導體鰭狀物/條狀物24/26處成長之汲極磊晶區36B之一部最終與自其鄰近之半導體鰭狀物/條狀物24/26處所成長之汲極磊晶區36B相聚合。如此之聚合情形發生於鄰近此些閘堆疊物30之區域處(例如第一部36B1處)。再者，自此些半導體鰭狀物/條狀物24/26處成長之源極磊晶區36A之部份與自鄰近之半導體鰭狀物/條狀物26處成長之源極磊晶區36A之部份相聚合。源極磊晶區36A之各輪廓亦相似於如第4C圖所示情形。
請參照第4D圖，由於於接近閘堆疊物30之中央處之區域(如36B2)的成長較為緩慢，故來自於各條狀物36B2處之汲極磊晶區36B之間則彼此不會相聚合。
第5A-5F圖則為一系列立體圖、上視圖與剖面圖，顯示了源極接觸插拴38、汲極接觸插拴40與下方之矽化物區42(未見於第5A圖，請參照第5C-5F圖)的形成。請參 照第5A圖，源極接觸插拴38係形成於相對應之下方之源極磊晶區36A之上並電性耦接之。汲極接觸插拴40則形成於汲極磊晶區36B之上並電性耦接之。源極接觸插拴38與汲極接觸插拴40可為一條狀物(strip)，其具有平行於閘堆疊物30與32之長度方向之一長度方向。
第5B圖繪示了第5A圖內所示結構之一上視圖。於此上視圖中，汲極磊晶區36B2包括形成於其內之數個孔洞(voids)43。此些孔洞43分隔了自不同之半導體鰭狀物/條狀物24/26處成長形成之半導體材料36之部份36B2。此些孔洞43內之數個部份內則為汲極接觸插拴40所填入，而此些孔洞43之其餘部份則於後續步驟中為介電材料所填滿。再者，汲極接觸插拴40則跨越了汲極磊晶區36B之未聚合部份36B2。於部份實施例中，汲極接觸插拴40並未覆蓋汲極磊晶區36B之聚合部份36B1。此些孔洞可延伸至汲極接觸插拴40之相對側。
第5C圖繪示了如第5A圖內所示結構之一剖面圖，其中此剖面圖係顯示了橫跨如第5A圖內之5C/5D-5C/5D之平面。矽化物區42係形成於汲極磊晶區36B之頂面上。於部份實施例中，汲極接觸插拴40具有大體水平於閘電極35之頂面35A(請參照第4B圖)之頂面40A。每一汲極接觸插拴40有時可稱為一M0OD。於其他實施例中，如第5D圖所示，可形成有複數個汲極接觸插拴40，此些汲極接觸插拴40之頂面接觸於金屬導線45之底面。金屬導線45則可為一底部金屬層M1。
第5E與5F圖繪示了如第5A圖內所示結構之一剖面 圖，其中此剖面圖係顯示了橫跨如第5A圖內之5E/5F-5E/5F之平面。如第5E圖所示，於部份實施例中，使用了矽化物最後方法(silicide-last approach)以形成矽化物區42。於此矽化物最後方法中，先形成介電層44。藉由形成一開口於介電層44內以露出汲極磊晶區36B之部份，並接著於汲極磊晶區36B之露出部份施行自對準矽化情形而形成矽化物區42。如此，此些矽化物區42具有對準於汲極接觸插拴40之各別邊緣之邊緣。然而，汲極磊晶區36B之其他部可不具有矽化物區形成於其上。如此有助於增加其汲極電阻值(drain resistance)，因而可調整依據本發明之實施例之靜電放電保護裝置的表現至較為一致的。
請參照第5F圖，則可使用矽化物最先方法(silicide-first approach)以形成矽化物區42。於此矽化物最先方法之中，形成阻抗保護氧化物(resist protective oxide，RPO)46，其中阻抗保護氧化物46至少覆蓋了未聚合之汲極磊晶區36B2之數個部份。第5B圖與第5F圖則示意地繪示了形成有阻抗保護氧化物之區域48。如第5圖之再次顯示，於形成阻抗保護氧化物46之後，矽化物區可形成於沒有存在有阻抗保護氧化物46之區域處。於此些實施例中，矽化物區42可稍微延伸至超越汲極接觸插拴40之各邊之處。於如第5E與5F圖中，源極矽化物區42’係於形成汲極矽化物區42時同時形成。源極矽化物區42’可形成於整個源極磊晶區36A的表面上。
請再次參照第5A圖，如第5A-5F圖所示之結構形成了靜電放電保護元件50，其包括了共用了汲極磊晶區36B 之兩個鰭型場效電晶體52。各鰭型場效電晶體52更包括了源極磊晶區36A。於部份實施例中，汲極接觸插栓40係連結於一輸入/輸出接墊(I/O pad)或一電源節點(power supply node)VDD，而源極接觸插拴38則連結於一電源節點VSS，電源節點VSS可為電性接地的。於其他實施例中，當鰭型場效電晶體52為n型鰭型場效電晶體(n-type FinFETs)時，汲極接觸插拴40可連接於一電路之一輸出接墊，而源極接觸插拴38則可連結於一電源節點VSS，以及閘堆疊物30之閘電極35(見於第4B圖)則可連結於一內部電路或一電源節點VSS。相反地，當鰭型場效電晶體52為p型鰭型場效電晶體(p-type FinFETs)時，源極接觸插拴40可連接於一電路之一輸出接墊，源極接觸插拴38則可連結於一電源節點VDD，而閘堆疊物30之閘電極35則可連結於一內部電路或一電源節點VDD，而閘堆疊物32之電極35則可為電性浮置(electrically floating)的。
於本實施例中，藉由形成非聚合之汲極磊晶區，因而可增加靜電放電保護元件50之汲極電阻值(drain resistance)。因而可調整數個靜電放電保護元件50的表現至較為一致的。此些實施例並不需要額外製程步驟與微影光罩的使用。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
20‧‧‧基板
22‧‧‧淺溝槽隔離區
24‧‧‧半導體條狀物
26‧‧‧半導體鰭狀物
30、32‧‧‧閘堆疊物
34‧‧‧閘介電層
35‧‧‧閘電極
35A‧‧‧頂面
36‧‧‧半導體材料
36A‧‧‧源極磊晶區
36B‧‧‧汲極磊晶區
36B1‧‧‧汲極磊晶區之第一部/聚合部份
36B2‧‧‧汲極磊晶區之第二部/未聚合部份
38‧‧‧源極接觸插拴
40‧‧‧汲極接觸插拴
40A‧‧‧頂面
42‧‧‧矽化物區
42’‧‧‧源極矽化物區
43‧‧‧孔洞
44‧‧‧介電層
45‧‧‧金屬導線
46‧‧‧阻抗保護氧化物
48‧‧‧形成有阻抗保護氧化物之區域
50‧‧‧靜電放電保護元件
52‧‧‧鰭型場效電晶體
D1、D2‧‧‧距離
H1、H2‧‧‧高度
VSS、VDD‧‧‧電源節點
第1-3、4A-4D、5A-5F圖為一系列剖面圖、立體圖以及上視圖，分別顯示了依據本發明之一實施例之一種靜電放電保護元件於不同階段中的製造情形。
20‧‧‧基板
22‧‧‧淺溝槽隔離區
30、32‧‧‧閘堆疊物
36‧‧‧半導體材料
36A‧‧‧源極磊晶區
36B‧‧‧汲極磊晶區
43‧‧‧孔洞

Claims (10)

  1. 一種半導體裝置，包括：複數個淺溝槽隔離區；複數個半導體條狀物，位於該些淺溝槽隔離區之間且相互平行；複數個半導體鰭狀物，位於該些半導體條狀物之上；一閘堆疊物，位於該些半導體鰭狀物之上並跨越該些半導體鰭狀物；以及一汲極磊晶半導體區，位於該閘堆疊物之一側且連結於該些半導體鰭狀物，其中該汲極磊晶半導體區包括：一第一部，鄰接於該些半導體鰭狀物，其中該第一部為跨越並準直於該些半導體條狀物之一連續區；以及複數個第二部，較該第一部遠離該閘堆疊物，其中該些第二部分別位於該些半導體條狀物之上並準直於該些半導體條狀物，且其中該些第二部為相互平行的並為一介電材料所相分隔。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括一源極磊晶半導體區，其中該汲極磊晶半導體區與該源極磊晶半導體區係位於該閘堆疊物之相對側，而其中該源極磊晶半導體區係為覆蓋並準直於該些半導體條狀物之一連續區。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括一汲極接觸插栓，位於該汲極磊晶半導體區之該些第二部上並電性連結該些第二部。
  4. 如申請專利範圍第1項所述之半導體裝置，其中該 些第二部之頂面係低於該汲極磊晶半導體區之該第一部之頂面。
  5. 一種半導體裝置，包括：複數個淺溝槽隔離區；複數個半導體條狀物，位於該些淺溝槽隔離區之間且相互平行；複數個半導體鰭狀物，位於該些半導體條狀物之上；一第一閘堆疊物以及一第二閘堆疊物，位於該些半導體鰭狀物之上並跨越該些半導體鰭狀物；以及一汲極磊晶半導體區，位於該第一閘堆疊物與該第二閘堆疊物之間，其中該汲極磊晶半導體區於鄰近該第一閘堆疊物與該第二閘堆疊物之複數個區域內形成連續之複數個汲極區，並於鄰近該第一閘堆疊物與該第二閘堆疊物之一中央部之一區內分成數個磊晶條狀物。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括：一第一源極磊晶半導體區，其中該第一源極磊晶半導體區與該汲極磊晶半導體區係位於該第一閘堆疊物之相對側；以及一第二源極磊晶半導體區，其中該第二源極磊晶半導體區與該汲極磊晶半導體區係位於該第二閘堆疊物之相對側，且其中該第一源極磊晶半導體區與該第二源極磊晶半導體區係為覆蓋並準直於該些半導體條狀物之一連續區。
  7. 如申請專利範圍第5項所述之半導體裝置，更包括一汲極接觸插栓，位於該汲極磊晶半導體區之複數個磊晶條狀物之上並電性偶接該些磊晶條狀物，其中該汲極接觸 插栓並未覆蓋該汲極磊晶半導體區之連續之該些汲極區，而該些磊晶條狀物之一頂面係低於連續之該些汲極區之一頂面。
  8. 一種半導體裝置之製造方法，包括：施行一磊晶成長，以自複數個淺溝槽隔離區之間之複數個半導體條狀物處成長出複數個磊晶區；繼續施行該磊晶成長，其中鄰近於一閘堆疊物之該些磊晶區之數個第一部聚合成為一連續汲極磊晶區，而其中較該些第一部遠離該閘堆疊物之該些磊晶區之數個第二部則為相互分隔的；以及於該些磊晶區之該些第二部相互分隔時，形成一接觸插栓以電性連結該些磊晶區之該些第二部。
  9. 如申請專利範圍第8項所述之半導體裝置之製造方法，更包括：形成位於複數個半導體鰭狀物上並跨越該些半導體鰭狀物之該閘堆疊物，其中該些半導體鰭狀物分別位於該些半導體條狀物之一之上並準直之；以及蝕刻未為該閘堆疊物所覆蓋之該些半導體鰭狀物之數個部份，其中該些半導體條狀物係為露出的，且其中該些磊晶區係自該些半導體條狀物之數個露出部處成長形成。
  10. 如申請專利範圍第8項所述之半導體裝置之製造方法，其中於施行該磊晶成長以及繼續施行該磊晶成長時，亦形成了一源極磊晶區，其中該源極磊晶區與該連續汲極磊晶區係位於該閘堆疊物之相對側，而其中該源極磊晶區為覆蓋該些半導體條狀物之一連續半導體區。
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