TWI511136B - Memory system and associated access method - Google Patents

Description

Memory system and access method thereof

The present invention relates to a memory system and an access method thereof, and more particularly to a flash memory system and an access method thereof.

Flash memory is a fairly common non-volatile memory. In short, the flash memory is implemented by storing a charge between a gate and a substrate of a transistor memory cell, and depending on the amount of charge stored. The amount of threshold voltage (referred to as Vt) of the transistor is changed. Among them, the threshold voltage size represents different stored data content.

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) flash memory is a structure of flash memory, which is characterized by the fact that charges are not easily moved between layers of oxygen, nitrogen and oxygen (ONO). The trap is in a fixed position. The SONOS flash memory is composed of a SONOS transistor array, and is controlled by an access circuit to write data and read data.

Please refer to FIG. 1A, which is a schematic diagram of a SONOS transistor. The SONOS transistor has a source, a gate, and a drain. Among them, the position between the source and the drain for storing the charge is not a conductor but a nitride. Therefore, the charges stored on both sides do not easily flow with each other. For convenience of explanation, between the gate and the drain (the right side of the gate) and the gate and the source (the left side) are defined as a first storage element and a second storage element, respectively. As described above, the charge R stored by the first storage element is not easily moved to the second storage element; the charge L stored by the second storage element is also not easily moved to the first storage element.

Please refer to Figure 1B, which is a storage element of the SONOS transistor. A schematic diagram of the threshold voltage distribution when a single data bit is stored. The higher the position of the curve, the greater the probability of occurrence, and it can also represent that the more storage elements in the SONOS transistor array have corresponding threshold voltages.

Figure 1B also illustrates the relationship between the number of storage elements of the SONOS transistor array and the data bits represented. This pattern contains two threshold voltages (V1, V2). The first level V1 with a lower threshold voltage represents a data bit of 1. The second level V2 with a higher threshold voltage represents a data bit of zero. Wherein, when the SONOS transistor programs a storage element or reads a storage element, a reference voltage level Vc is used as a criterion.

For example, when the storage element is read, when the threshold voltage of the storage element is judged to be higher than the reference voltage Vc, it means that the read data bit is "0"; and when the storage element is read, the threshold voltage of the storage element is determined to be low. At the reference voltage Vc, it means that the read data bit is "1".

When the data bit to be written is "0", the charge must be stored in the oxygen-oxygen (ONO) layer by a program flow so that the threshold voltage is higher than the reference voltage Vc. On the other hand, if the data bit to be written is "1", the equivalent charge must be removed from the oxygen-oxygen (ONO) layer by an erase process to make the threshold voltage lower than the reference voltage Vc.

Figures 1A, 1B represent the case where the storage element is only used to store a single data bit. With the substantial increase in the amount of data that needs to be stored, SONOS transistors are bound to provide more efficient access to larger storage capacities and to ensure correct access to data bits.

According to a first aspect of the present invention, a memory system is provided, comprising: a plurality of memory cells, each of the memory cells representing N data bits using M threshold voltages, wherein the M threshold voltage systems comprise at least one a threshold voltage of high interference immunity, and a threshold voltage of at least one low interference immunity capability, where M and N are integers and M is greater than N; a conversion circuit Providing these threshold voltages a correspondence between the data bits, and replacing the data corresponding to the threshold voltage of the at least one lower anti-interference ability in the correspondence relationship with the threshold voltage of the at least one higher anti-interference capability And an access circuit that accesses the memory cells according to the replaced correspondence.

According to a second aspect of the present invention, an access method is provided for a memory system including a plurality of memory cells, a conversion circuit, and an access circuit, the access method comprising the steps of: The memory cell provides a correspondence between M threshold voltages and N data bits, wherein the M threshold voltages comprise at least one threshold voltage with higher anti-interference capability, and at least one lower anti-interference capability a threshold voltage, wherein M and N are integers, and M is greater than N; the conversion circuit replaces the at least one lower interference immunity with the threshold voltage of the at least one higher interference immunity The threshold voltage corresponds to a combination of data bits; and the access circuit accesses the memory cells according to the replaced correspondence.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

71‧‧‧Access circuit

73‧‧‧Transition circuit

75‧‧‧Voltage generation circuit

77‧‧‧Memory array

Figure 1A is a schematic diagram of a SONOS transistor.

Figure 1B is a schematic diagram of the number of storage elements and the threshold voltage distribution when a single data bit is stored in a storage element of a SONOS transistor.

Figure 2A is a storage element on both sides of a SONOS transistor for storing two data bits.

Figure 2B is a schematic diagram of the number of storage elements and the threshold voltage distribution when two data bits are stored in a storage element of a SONOS transistor.

Figure 3 is a schematic diagram showing the threshold voltage of a storage element of a SONOS transistor, which is affected by adjacent storage elements.

Figure 4 is a combination of threshold voltages when the storage elements on both sides of the SONOS transistor store two data bits.

Figure 5 is a schematic diagram showing the supply of five threshold voltages representing two data bits.

Figure 6, which is a combination of threshold voltages for five storage elements on both sides of the SONOS transistor.

Figure 7 is a schematic illustration of the memory circuit of the present invention.

Figure 8, which is an embodiment of the present invention, corresponds to a fifth level V5 corresponding to a data bit of "10".

FIG. 9A is a schematic diagram of a manner in which the present invention is susceptible to a change in the confusion situation when the five levels are combined.

Figure 9B is a schematic diagram showing the correspondence between the level combination and the data bit in Figure 9A.

In order to store more information, the SONOS transistor can further change the correspondence between the charge stored in the storage element and the threshold voltage. For example: Suppose each storage element can be used to store two data bits.

Please refer to FIG. 2A, which is a storage element on both sides of the SONOS transistor, respectively for storing two data bits. The storage element on the left side can store the data bits L1 and L2, and the storage element on the right side is used to store the data bits R1 and R2. Hereinafter, the correspondence between the data bit and the threshold voltage will be described by taking a storage element on one side as an example.

Please refer to FIG. 2B, which is a schematic diagram of the number of storage elements and the threshold voltage distribution when two data bits are stored in the storage element of the SONOS transistor. This pattern contains four levels, which represent different threshold voltages. From left to right: the first level V1 representing the data bit is "11", the second level V2 representing the data bit being "10", and the third level representing the data bit being "00" V3, the fourth level V4 representing the data bit is "01".

When a storage element is used to store two data bits, multiple voltages need to be referenced. Wherein, the initial reference voltage Vc0 corresponds to the high-order data of the storage element. The first reference voltage Vc1 and the second reference voltage Vc2 correspond to the low-order data of the storage element. The following describes the manner of reading, and then explains how to write.

For the distribution of Figure 2B, when the storage element is read, if the threshold voltage is lower than the initial reference voltage Vc0, it can be confirmed that the high bit of the data bit is "1", otherwise it is "0".

First, the reading result is a case where the threshold voltage is higher than the initial reference voltage Vc0. As described above, when the threshold voltage is higher than the initial reference voltage Vc0, it corresponds to the high bit of the data bit being "0". Next, it is further determined whether the threshold voltage is lower than the second reference voltage Vc2.

If the threshold voltage is indeed lower than the second reference voltage Vc2, it can be confirmed that the lower bit of the data bit is "0". Accordingly, it can be known that the combination of the data bits is "00" as a result of the previous judgment that the high order bit is "0".

On the other hand, if the threshold voltage is higher than the second reference voltage Vc2, it can be confirmed that the lower bit of the data bit is "1". Accordingly, it can be known that the combination of the data bits is "01" as a result of the previous judgment that the high bit is "0".

According to the above, after the high bit is determined to be 0 according to the initial reference voltage Vc0, the lower bit of the data bit is determined according to the comparison between the threshold voltage and the second reference voltage Vc2. If the read threshold voltage is between the initial reference voltage Vc0 and the second reference voltage Vc2, the content of the data bit is determined to be "00"; and if the read is higher than the second reference voltage Vc2, the data is judged The content of the bit is "01".

Next, the reading result is a case where the threshold voltage is lower than the initial reference voltage Vc0. As described above, when the threshold voltage is lower than the initial reference voltage Vc0, it corresponds to the high bit of the data bit being "1". Next, it is further determined whether the threshold voltage is lower than the first reference voltage Vc1.

If the threshold voltage is indeed lower than the first reference voltage Vc1, it can be confirmed that the lower bit of the data bit is "1". Accordingly, it can be known that the combination of the data bits is "11" with the result of the previous judgment that the high bit is "1".

On the other hand, if the threshold voltage is higher than the first reference voltage Vc1, it can be confirmed that the lower bit of the data bit is "0". According to this, the high-order element obtained by the previous judgment is As a result of "1", it can be known that the combination of the data bits is "10".

According to the above, after the high bit is determined to be "1" according to the initial reference voltage Vc0, the lower bit of the data bit is determined according to the comparison between the threshold voltage and the first reference voltage Vc1. If the read threshold voltage is between the initial reference voltage Vc0 and the first reference voltage Vc1, the content of the data bit is judged as "10"; and if the read threshold voltage is lower than the first reference voltage Vc1 , the content of the data bit is judged as "11".

On the other hand, if data is to be written to the storage component, the storage component is programmed with a different threshold voltage depending on the content of the data bit to be written, or the threshold voltage of the storage component is lowered by the erase process.

First, if the high order bit of the data bit to be written is "0" (ie, the written data bit is "0x"), the storage element threshold voltage must be programmed to a position higher than the initial reference voltage Vc0 ( V3). Then, if the lower bit of the data bit to be written is "1" (ie, the written data bit is "01"), the storage element threshold voltage must be stylized to a position higher than the second reference voltage Vc2. (V4).

Conversely, if the high order bit of the data bit to be written is "1" (ie, the written data bit is "1x"), then the erase process must be used to make the threshold voltage of the storage element lower than the initial reference. Voltage Vc0. Then, if the lower bit of the data bit to be written is "1" (ie, the written data bit is "11"), the erase process must be used to make the threshold voltage of the storage element lower than the first reference. The position of the voltage Vc1 (V1).

For convenience of explanation, the voltage distribution of FIG. 2B is divided into four levels here. From left to right respectively: the first level V1 whose threshold voltage is lower than the first reference voltage Vc1; the threshold voltage is between the first reference voltage Vc1 and the second level V2 between the initial reference voltage Vc0; the threshold voltage is between The third level V3 between the initial reference voltage Vc0 and the second reference voltage Vc2; and the threshold voltage is higher than the fourth level V4 of the second reference voltage Vc2.

In other words, if the obtained threshold voltage belongs to the first level V1, the data bit stored on behalf of the storage element is "11"; if the obtained threshold voltage belongs to the second level V2, it represents the data bit stored by the storage element. Yuan is "10"; if it is When the threshold voltage belongs to the third level V3, the data bit stored on behalf of the storage element is "00"; and, if the obtained threshold voltage belongs to the fourth level V4, the data bit stored on behalf of the storage element is "01" ".

Furthermore, if a data bit is to be written, the threshold voltage of the storage element is controlled through a stylization and erasing process. That is, if the data bit to be written is "11", the control threshold voltage belongs to the first level V1; if the data bit to be written is "10", the control threshold voltage belongs to the second V2; When the written data bit is "00", the control threshold voltage belongs to the third level V3; and, if the data bit to be written is "01", the control threshold voltage belongs to the fourth level V4.

As a result, the threshold voltage of the storage component affects the interpretation of the data bit. Therefore, it is very important to correctly interpret the threshold voltage when storing the same data bit in the same storage element. As the process progresses, the size of the memory cell (SONOS transistor) is also smaller, and the situation in which the storage elements interfere with each other is more likely to occur. That is, in the same SONOS transistor, the charges of adjacent storage elements may affect each other, causing the judgment of the threshold voltage to be disturbed. That is, each of the threshold voltage distributions may be overlapped.

As previously mentioned, the charge within the storage element may interfere with each other. Therefore, the actual threshold voltage distribution is not as ideal as Figure 2B, but may be as shown in Figure 3. Please refer to FIG. 3, which is a schematic diagram of the threshold voltage of the storage element of the SONOS transistor, which is affected by the adjacent storage elements. This figure represents a storage element (second storage element) located on the left side of the SONOS transistor. If the threshold voltage is the first level V1, and the threshold voltage of the storage element (first storage element) on the right side is programmed to When the third level V3 or the fourth level V4, the threshold voltage of the left storage element (second storage element) is susceptible to the stylization of the right storage element.

As can be seen from Fig. 3, when the first storage element is programmed, the second storage element is severely disturbed. Even the case where the second storage element should be at the threshold voltage of the first level V1 also produces a situation in which the second level V2 overlaps with each other. If the first level V1 is regarded as an interference source threshold voltage, the second level V2 belongs to a threshold voltage with a lower anti-interference ability. Associated with the second storage element When the threshold voltage of the piece belongs to the first level V1 or the second level V2, a false positive may occur. That is, for the case where the threshold voltage of the second storage element is between the first reference voltage Vc1 and the initial reference voltage Vc0, it will be impossible to read whether the data bit in the second storage element is 11 or 10.

Such interference situations are particularly prone to occur when the threshold voltage of the storage element is lower, but the threshold voltage for the adjacent storage elements to be programmed is higher, and the threshold voltage corresponding to the data bits of the two storage elements The situation is too big. Therefore, if the original threshold voltage of the first storage element is the first level V1, but the second storage element is to be programmed into the third level V3 or the fourth level V4, the first storage element is similarly influences.

Please refer to FIG. 4, which is a combination of threshold voltages when the storage elements on both sides of the SONOS transistor store two data bits respectively. The first column of this figure represents the threshold voltage at the first storage element (the storage element on the right side of the SONOS transistor) is the first level V1, the second level V2, the third level V3, and the fourth level V4. The situation. The first column of this figure represents the threshold voltage at the first storage element (the storage element on the left side of the SONOS transistor) is the first level V1, the second level V2, the third level V3, and the fourth level V4. The situation. Wherein, it is assumed that the first level V1 represents a data bit (1, 1), the second level V2 represents a data bit (1, 0), and the third level V3 represents a data bit (0, 0). The fourth level V4 represents the data bit (0, 1).

For ease of explanation, the other fields in the table represent different types of threshold voltage combinations in Vx-Vy format. Where Vx represents the threshold voltage corresponding to the second storage element (left storage element) and Vy represents the threshold voltage corresponding to the first storage element (right storage element).

In the upper right corner of the table in Figure 4, the threshold voltage combinations (V1-V3) and (V1-V4) are indicated by the bottom of the net. That is, when the threshold voltage of the second storage element is the first level V1, and the first storage element is to be programmed into the third level V3 and the fourth level V4. Such a combination of threshold voltages is a condition in which the second storage element is susceptible to the first storage element. At this time, the threshold voltage of the second storage element may appear as the third The situation of the figure.

In the lower left corner of the table in Figure 4, the threshold voltage combinations (V3-V1) and (V4-V1) are indicated by the bottom of the net. That is, when the threshold voltage of the first storage element is the first level V1, and the second storage element is to be programmed into the third level V3 and the fourth level V4. Such a combination of threshold voltages is a condition in which the first storage element is susceptible to the second storage element. At this time, the threshold voltage of the first storage element may appear as in the case of FIG.

In the case where the combination of the threshold voltages of the second storage element and the first storage element is (V1-V3), (V1-V4), (V3-V1), (V4-V1), it is easy to generate stylized interference. situation. Wherein, the combination of the threshold voltages (V1-V3) corresponds to the case where the data bit is (11, 00), the voltage combination (V1-V4) corresponds to the case where the data bit is (11, 01), and the combination of the threshold voltages. (V3-V1) corresponds to the case where the data bit is (00, 11), and the combination of the threshold voltages (V4-V1) corresponds to the case where the data bit is (01, 11).

In order to avoid that the threshold voltage of the storage element is disturbed by adjacent storage elements, the present invention proposes a method of combining more threshold voltages with more data bits. For example, if each storage element can store 2 data bits, the combination type of data bits that can be provided by each storage element can be four. At this time, if the storage element can provide five kinds of threshold voltages. In this way, when the storage elements on both sides of the SONOS transistor use the threshold voltage for data bit interpretation, the combination of threshold voltages that may be formed by the storage elements on both sides will also increase.

Please refer to FIG. 5, which is a schematic diagram of the storage element providing five threshold voltages representing two data bits. In this illustration, the threshold voltage is divided into five levels: a first level V1, a second level V2, a third level V3, a fourth level V4, and a fifth level V5. Wherein, it is assumed that the first level V1 represents that the data bit in the storage element is (1, 1), the second level V2 represents that the data bit in the storage element is (1, 0), and the third level V3 represents storage. The data bit in the component is (0, 0), and the fourth bit V4 represents that the data bit in the storage element is (0, 1). In addition, the fifth level V5 is a threshold voltage with high anti-interference ability. The fifth level V5 can be used to provide a flexible definition, and therefore, the data bit corresponding to the fifth level V5 does not need to be defined. When the threshold voltage interpretation mode of FIG. 5 is adopted, the combination type of the threshold voltage of the first storage element and the second storage element may be 5*5=25.

Please refer to Fig. 6, which is a schematic diagram of five levels of storage elements on both sides of the SONOS transistor. As described above, the threshold voltage combinations (V1-V3), (V1-V4), (V3-V1), and (V4-V1) are combinations in which the first storage element and the second storage element easily form interference with each other. Here, the confusing critical voltage combination frame is further selected together. For example, the threshold voltage combination (V1-V3) easily interferes with the threshold voltage combination (V2-V3); the threshold voltage combination (V1-V4) easily interferes with the threshold voltage combination (V2-V4); the threshold voltage combination (V3- V1) easily interferes with the threshold voltage combination (V3-V2); and the threshold voltage combination (V4-V1) easily interferes with the threshold voltage combination (V4-V2).

When the threshold voltage of the storage element is the first level V1, it is easy to be pulled up because the adjacent storage elements are affected by the relatively high level (V3, V4), thereby affecting the phenomenon that the threshold voltage is V2. In other words, when the threshold voltage of the storage element is the second level V2, it belongs to a threshold voltage with a lower anti-interference ability. If the threshold voltage combination contains the second level V2, the chance of being disturbed is higher.

However, compared with Fig. 4, the sixth figure adds a fifth quasi-V5 case, and therefore, there are many types of voltage combinations that may be generated. Wherein, when the threshold voltage is the fifth level V5, it belongs to a threshold voltage with high anti-interference ability. That is, several combinations of threshold voltages (V1-V5), (V2-V5), (V3-V5), (V4-V5), (V5-V1), (V5-V2), ( V5-V3), (V5-V4), (V5-V5). Therefore, these new combinations of threshold voltages can be used to replace the combination of threshold voltages that are prone to confusion.

Please refer to FIG. 7, which is a schematic diagram of the memory circuit of the present invention. According to the concept of the present invention, when accessing the stylized memory array 77, the access circuit 71 must convert the data content of the N data bits to be written into the corresponding M threshold voltages by the conversion circuit 73. According to it, as a reference for accessing memory cells. In the foregoing embodiment, it is assumed that M=5 and N=4, but the actual application is not limited thereto. That is, if M and N are integers and M is greater than N, the concept of the present invention can be applied. among them, The conversion circuit 73 is equivalent to providing a correspondence relationship between the threshold voltage combination and the data bits. In practical applications, such correspondence can be converted by means of mapping, table lookup, or using an algorithm. Furthermore, voltage generation circuit 75 is used to generate the dynamic operating voltage combination required to read and write the memory array for M threshold voltages.

Referring to FIG. 8, which is an embodiment of the present invention, the fifth level V5 corresponds to a schematic diagram in which the data bit is "10". Here, the data represented by the fifth level of the first storage element and the second storage element is uniformly defined as "10". This embodiment utilizes a threshold voltage (fifth level V5) with a higher anti-interference ability, and replaces a threshold voltage (second level V2) with a lower anti-interference capability.

In short, the practice of this embodiment is: when the data bit of the second storage element is "10", and the first storage element is to be programmed into the third level V3 because it corresponds to the data bit "00". Or, if it is to be programmed into the fourth level V4 corresponding to the data bit "01", in the second storage element, the second level V2 is not used corresponding to the data bit "10", but The fifth level V5 corresponds to the data bit "10".

Furthermore, when the data bit of the first storage element is "10", and the second storage element is to be programmed into the third level V3 because it corresponds to the data bit "00", or because it corresponds to the data bit When "01" is to be programmed into the fourth level V4, in the first storage element, the second level V2 is not used corresponding to the data bit "10", but the fifth level V5 is corresponding to the data. Bit "10".

Figure 9A illustrates how the present invention replaces several situations that are susceptible to stylized interference with a new combination of fifth level formations. Please refer to Fig. 9A, which is a schematic diagram of the combination of threshold voltages on both sides of the SONOS transistor when the storage element provides five threshold voltages representing two data bits. For ease of explanation, the threshold voltage is labeled here with the representative data bits. It can be seen from Fig. 8 that when the threshold voltage combination is (V1-V2), it means that the left storage element is the first level V1 and the right storage element is the second level V2. The first level of the left storage element corresponds to a data bit of "11" and a second level of the right storage element corresponding to a data bit of "10". Therefore, column 4 of column 3 of the figure indicates that the threshold voltage combination is (V1-V2). At the time, the left side storage element and the data element of the right storage element (11, 10). The correspondence between the remaining threshold voltage combinations and the data bits is also similarly labeled.

Since there are 4 data bits on both sides of the SONOS transistor, the number of combinations of these four data bits is 16 kinds. Therefore, it is necessary to correspond to 16 kinds of threshold voltage combinations. However, when five threshold voltages are defined for each of the storage elements, there are a total of 25 combinations of threshold voltages on both sides of the SONOS transistor. Therefore, it is possible to exclude situations in which the characteristics are less than ideal and may cause confusion.

As mentioned above, the second level V2 belongs to a threshold voltage with a lower anti-interference ability and, therefore, is susceptible to interference from the first level V1. Therefore, this embodiment replaces the combination of data bits represented by the second level V2 with a threshold voltage (fifth level V5) having a higher anti-interference capability.

The first is that the critical voltage combination (V1-V3) and (V2-V3) are easily confused, and the correspondence between the threshold voltage (V2-V3) and the data bit (10,00) is deleted and changed to critical. The voltage combination (V5-V3) corresponds to the data bit (10, 00). According to the embodiment of FIG. 9A, the second storage element may be further configured as the first level V1 or the second level V2, and the first storage element is in the third level V3, that is, (V1/V2-V3) The combination of threshold voltages corresponds to the data bit (11, 00).

In this way, even if the second storage element is affected by the first storage element being programmed into the third level V3, the threshold voltage of the second storage element is changed from the first level V1 to the second level V2. When the second storage element is read, the data bit stored by the second storage element can still be correctly interpreted as "11". In this way, when the second storage element is at a lower threshold voltage (V1/V2), and the first storage element is to be programmed into the third level V3, the data bit of the second storage element may be generated. The case of misjudgment.

The second is that for the case where the threshold voltage combination (V1-V4) and (V2-V4) are easily confused, the correspondence between the threshold voltage combination (V2-V4) and the data bit (10, 01) is deleted, and The threshold voltage combination (V5-V4) corresponds to the data bit (10, 01). According to the embodiment of FIG. 9A, the second storage element may further be the first level V1 or the second level V2, and the first storage element is the fourth level V4. The combination of the threshold voltages, ie (V1/V2-V4), corresponds in common to the data bits (11, 01).

In this way, even if the second storage element is affected by the first storage element being programmed into the fourth level V4, the threshold voltage of the second storage element is changed from the first level V1 to the second level V2. The data bit stored in the second storage element can be correctly interpreted as "11". In this way, when the second storage element is at a lower level (V1/V2), and the first storage element is to be programmed into the fourth level V4, the data bit of the second storage element may be generated. The case of misjudgment.

The third is that the voltage combination (V3-V1) and (V3-V2) are easily confused, and the correspondence between the threshold voltage combination (V3-V2) and the data bit (00, 10) is deleted and changed to critical. The voltage combination (V3-V5) corresponds to the data bit (00, 10). According to the embodiment of FIG. 9A, the threshold voltage of the first storage element may be further the first level V1 or the second level V2, and the second storage element is the third level V3, that is, (V3-V1) The threshold voltage combination of /V2) corresponds to the data bit (00, 11).

In this way, even if the first storage element is affected by the second storage element being programmed into the third level V3, the threshold voltage of the first storage element is changed from the first level V1 to the second level V2. The data bit stored in the first storage element can be correctly interpreted as "11". In this way, when the threshold voltage of the first storage element is a lower voltage (V1/V2) and the second storage element is to be programmed into the third level V3, the data of the first storage element may be avoided. The bit is misjudged.

The fourth is that for the case where the threshold voltage combination (V4-V1) and (V4-V2) are easily confused, the correspondence between the threshold voltage combination (V4-V2) and the data bit (01, 10) is deleted, and The threshold voltage combination (V4-V5) corresponds to the data bit (01, 10). According to the embodiment of FIG. 9A, the first storage element may be V1 or V2, and the second storage element is V4, that is, the threshold voltage combination of (V4-V1/V2) corresponds to the data bit ( 01, 11).

In this way, even if the first storage element is affected by the second storage element being programmed into the fourth level V4, the threshold voltage of the first storage element is caused by When the first quasi-V1 is changed to the second level V2, the data bit stored in the first storage element can still be correctly interpreted as "11". In this way, when the threshold voltage of the first storage element is lower (V1/V2) and the second storage element is to be programmed into the fourth level V4, the data of the first storage element may be avoided. The bit is misjudged.

In addition, since only 16 combinations of threshold voltages are required, several threshold voltage combinations of relatively borders can be deleted here. Therefore, the case where the combination of the threshold voltages is (V1 - V5), (V2 - V5), (V5 - V1), (V5 - V2), (V5 - V5) is not used. In the corresponding relationship defined in FIG. 9A, the first storage element may further have a higher threshold voltage (third level V3 or fourth level V4), and the second storage element has a lower threshold voltage ( The case of the first quasi-V1 or the second quasi-V2) is distinguished. And, the second storage element is a higher threshold voltage (the third level V3 or the fourth level V4), and the first storage element is a lower threshold voltage (the first level V1 or the second level V2) The situation is divided. Even if the threshold voltage of the storage element changes the distribution of the threshold voltage because the adjacent storage elements are programmed, the data bit that may be misjudged has been previously separated, thereby preventing the misjudgment.

In order to further clarify the correspondence between the data bit and the threshold voltage combination, Figure 9B further summarizes the correspondence between the level combination and the data bit in Figure 9A. Figure 9B divides the threshold voltage combinations into three categories in a circled manner. That is: the first case where each circle contains four combinations of threshold voltages, the second case where each circle contains two combinations of threshold voltages, and the third case where each circle contains only one combination of threshold voltages.

The first case refers to a circle in the upper left corner that contains four combinations of threshold voltages, and a circle in the lower right corner that contains four combinations of threshold voltages. That is, the threshold voltage combination (V1-V1), (V1-V2), (V2-V1), (V2-V2), (V3-V3), (V3-V4), (V4-V3), (V4- V4). When the threshold voltage in the storage element falls into this category, it means that the type of the data bit can be directly interpreted according to the threshold voltage. This situation represents the determination of the threshold voltage and data according to the preset correspondence. The correspondence of the bits. The combination of these types of threshold voltages, the first level V1 represents the data bit "11", the second level V2 represents the data bit "10", and the third level V3 represents the data bit "00", The fourth bit V4 represents the data bit "01".

The second case refers to a circle in the lower left corner that contains two combinations of threshold voltages, and a circle in the upper right corner of the figure that contains two combinations of threshold voltages. That is, the threshold voltage is combined (V3-V1/V2), (V4-V1/V2), (V1/V2-V3), and (V1/V2-V4). When the threshold voltage in the storage element falls into this category, it means that the threshold voltages (V1, V2) of the low level are treated equally, and it is not necessary to distinguish the first level V1 from the second level V2. This situation is based on a threshold voltage with a lower immunity to interference (second level V2), corresponding to the interference source threshold voltage that interferes with the threshold voltage (second level V2) with lower immunity to interference (p. A data combination corresponding to V1) is "11". Among them, the threshold voltage with lower anti-interference ability is the threshold voltage with the second lowest level; and the threshold voltage of the interference source is the threshold voltage with the lowest level. Therefore, the first level V1/second level V2 represents the data bit "11", the third level V3 represents the data bit "00", and the fourth level V4 represents the data bit "01".

The third case refers to the circle on the lower side and the right side in the figure. When the threshold voltage in the storage element falls into these two circles, it represents the case where the fifth level V5 is used. That is, the threshold voltages are combined (V3-V5), (V4-V5), (V5-V3), and (V5-V4). In this case, the threshold voltage with higher anti-interference ability (for example, the fifth level V5) is substituted, and the substitution corresponds to the threshold voltage (second level V2) with lower anti-interference ability in the corresponding relationship. The data bit "10". Among them, the third level V3 represents the data bit "00", the fourth level V4 represents the data bit "01", and the fifth level V5 represents the data bit "10".

The conversion circuit of FIG. 7 can be used for the conversion of data bits and threshold voltages when the access circuit reads and writes the memory array for the foregoing several cases. According to the above, the SONOS transistor (memory cell) of the present invention can more accurately change the threshold voltage and the data bit represented by the threshold voltage for the application of a plurality of data bits. Among them, the original and the lower level and lower the anti-interference ability The corresponding relationship between the voltage (eg, the second level V2) and the data bit "10" is replaced by the threshold voltage with the highest level and high anti-interference ability (eg, the fifth level V5). This method can avoid the interference of the lower threshold level voltage when the adjacent storage elements are programmed to a high level, and improve the reading effect of the data.

In practical applications, the data bit corresponding to the fifth level V5 is not limited to "10". Even the fifth level V5 of the first storage element and the fifth level V5 of the second storage element do not necessarily have the same data bits.

The conventional approach is to determine the corresponding threshold voltage combination for the number of bits. For example, when the number of data bits provided for the SONOS transistor is 4, a combination of 2^4=16 threshold voltages is provided. The present invention further provides a plurality of threshold voltage combinations (5*5=25), thereby eliminating those in which the critical voltage characteristics are easily affected. The foregoing embodiments illustrate that the present invention can avoid false positives due to charge disturbances between adjacent storage elements. Accordingly, the reliability of the SONOS memory when storing data can be improved.

In practical applications, no matter which correspondence is used, it is relatively simple to change the comparison table or conversion formula in the conversion circuit 63. Further, the present invention can also be applied to the case where the number of threshold voltages is larger and the number of data bits is larger.

In this embodiment, a larger number of voltage levels are used, and appropriate coding and conversion can be used to avoid stylized interference, read interference, and other types of critical voltage distribution problems of adjacent storage elements. In addition, in other applications, the range of the threshold voltage, the degree of interference, and the demand for reading and writing speed are further considered. Or, with parameters such as threshold voltage change, current change, voltage change, power change, electric field change, resistance change, capacitance change, magnetic field change, heat change, shininess, transmittance, pressure change, position change, etc. The conversion circuit is used as a reference for encoding/mapping.

In addition to the SONOS memory, the concept of mapping conversion employed by the present invention can also be applied to other types of memory. For example: Resister Memory, Ferroelectric Memory, Magnetoresistance Magnetic memory (Magnetoresistive Memory), phase change memory (Phase-change Memory) and so on. The conversion circuit of the present invention uses the coding method to redefine the correspondence between the data bit and the threshold voltage, so as to achieve an effect of easier identification, greater margin, easier implementation and manufacture.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

71‧‧‧Access circuit

73‧‧‧Transition circuit

75‧‧‧Voltage generation circuit

77‧‧‧Memory array

Claims (10)

A memory system comprising: a plurality of memory cells, each of the memory cells representing M data bits using M threshold voltages, wherein the M threshold voltage systems comprise at least one threshold voltage having a high anti-interference capability, And a threshold voltage having at least one lower anti-interference capability, wherein M and N are integers, and M is greater than N; a conversion circuit providing a correspondence between the threshold voltages and the data bits, and Substituting the at least one higher anti-interference ability threshold voltage for the data combination corresponding to the at least one lower anti-interference ability threshold voltage in the correspondence relationship; and, an access circuit, according to the The memory cells are accessed by the corresponding correspondence after the substitution. The memory system of claim 1, further comprising: a voltage generating circuit that generates the M threshold voltages. The memory system of claim 1, wherein each of the memory cell systems comprises a first storage element and a second storage element, and the first and second storage elements respectively use the M threshold voltages And store N/2 data bits. The memory system of claim 1, wherein the at least one higher threshold voltage is a threshold voltage having the highest level among the threshold voltages; and the at least one The threshold voltage of the lower anti-interference ability is the threshold voltage of the second lowest level among the threshold voltages. The memory system of claim 1, wherein the conversion circuit is configured to generate at least one threshold voltage having a lower anti-interference capability, corresponding to a threshold voltage generated for the at least one lower anti-interference capability One of the interferences is the combination of data corresponding to the threshold voltage of the interference source. An access method is applied to a memory system including a plurality of memory cells, a conversion circuit and an access circuit, the access method comprising the steps of: providing the M threshold voltages to each of the memory cells a correspondence between N data bits, wherein the M threshold voltage systems comprise at least one higher a threshold voltage of anti-interference ability, and at least one threshold voltage with low anti-interference ability, wherein M and N are integers, and M is greater than N; the conversion circuit is replaced by the threshold voltage of the at least one higher anti-interference ability And converting, in the correspondence, a combination of data bits corresponding to the at least one lower anti-interference ability threshold voltage; and the access circuit accessing the memory cells according to the replaced correspondence. The access method of claim 6, wherein the memory system comprises a voltage generating circuit, and the access method further comprises the step of: generating, by the voltage generating circuit, the M threshold voltages. The access method of claim 6, wherein each of the memory cell systems comprises a first storage element and a second storage element, and the first and second storage elements respectively use the M threshold voltages And store N/2 data bits. The access method of claim 6, wherein the at least one higher threshold voltage is a threshold voltage having the highest level among the threshold voltages; and the at least one The threshold voltage of the lower anti-interference ability is the threshold voltage of the second lowest level among the threshold voltages. The access method of claim 6, further comprising the step of: the conversion circuit corresponding to the at least one lower anti-interference ability threshold voltage corresponding to the at least one lower anti-interference capability The threshold voltage produces a combination of data corresponding to one of the interference source threshold voltages.