TWI511141B - Nonvolatile semiconductor memory device - Google Patents

Description

Non-volatile semiconductor memory component

The present invention relates to a non-volatile semiconductor memory component and a method of stylizing the same.

A semiconductor memory component is a component in which data from which data can be stored and stored can be read. Semiconductor memory components can be classified into volatile memory components and non-volatile memory components. Volatile memory components require a supply of power to persist to preserve data, while non-volatile memory components retain data when the power supply disappears. Therefore, non-volatile memory components are widely used in applications where the power supply may be suddenly disturbed.

The non-volatile memory component comprises an electrically erasable and programmable mable (EEPROM) cell, such as a flash EEPROM cell. Figure 1 shows a vertical cross-sectional view of a flash EEPROM cell 10. Referring to FIG. 1, a deep n-type well 12 is formed on a P-type substrate 11 or a body region, and a P-type well 13 is formed on the N-well 12. An N-type source region 14 and an N-type drain region 15 are formed in the P-well 13. A P-type channel region (not shown) is formed between the source region 14 and the drain region 15. A floating gate 17 isolated by an insulating layer 16 is formed over the P-type channel region. A control gate 19 isolated by another insulating layer 18 is formed over the floating gate 17.

Figure 2 shows the threshold voltage range of the flash EEPROM cell 10 during staging and erase operations. Referring to Figure 2, the flash EEPROM cell 10 has a higher threshold voltage range during program operation (approximately 6 to 7V) with a lower threshold voltage range (approximately 1 to 3V) during erase operation.

Referring to Figures 1 and 2, during the stylization operation, hot electrons must be injected from the channel region adjacent to the drain region 15 to the floating gate electrode, so that the threshold voltage range of the EEPROM cell increases. Conversely, the hot electrons injected into the floating gate 17 during the staging operation must be removed during the erase operation, so the threshold voltage range of the EEPROM cell will decrease. Accordingly, the threshold voltage value of the EEPROM cell changes after the staging and erasing operations.

FIG. 3 shows a block diagram of a conventional non-volatile semiconductor memory device 30. Referring to FIG. 3, the memory component 30 includes a memory array 32, a row of decoding and level conversion circuits 34, a column of decoding and level conversion circuits 36, an input/output circuit 38, and a pump circuit 39.

4 shows a partial schematic view of the memory array 32 shown in FIG. Referring to FIG. 4, the memory array 32 includes a plurality of word lines WL0 to WL2, a plurality of bit lines BL0 to BL7, and a plurality of memory cell transistors MX, Y arranged in a matrix, wherein X and Y are individually Represents the position of the transistor in the horizontal direction and the position in the vertical direction. The memory cell transistors MX, Y are connected to the word line in the horizontal direction and the bit line in the vertical direction. For example, the gate of the cell transistor M1,1 is connected to the first word line WL0, and the drain is connected to the first bit line BL0; the gate of the cell transistor M1,2 is connected to the One word line WL0, and the drain is connected to the second bit line BL1.

Referring to FIG. 3, the input/output circuit 38 receives a plurality of address signals ADDRESS from a processor or a memory controller (not shown), and a plurality of The data signal DATA and a clock signal XCLK. The row decode and level conversion circuit 34 receives a row of address signals AC from the input/output circuit 38 to select a bit line in the memory array 32. The column decode and level conversion circuit 36 receives a column of address signals AR from the input/output circuit 38 to select a word line in the memory array 32.

During operation, the pump circuit 39 receives a mode signal PGM from the input/output circuit 38 to generate a pump output voltage VC to circuits 34 and 36. The circuit 34 is responsive to the row address signal AC to provide a pump output voltage VC to the selected bit line. The circuit 36 is responsive to the column address signal AR to provide a pump output voltage VC to the selected word line.

Figure 5 is a diagram showing the waveforms of voltage and current of a unit cell transistor in a conventional stylized operation. Referring to Figures 4 and 5, four unit cell transistors M1,1, M1,2, M1,3 and M1,4 are selectively programmed in response to the row address signal AC and the column address signal AR. At time t0, the pump circuit 39 generates a pump output voltage VC having a higher level than the power supply voltage VDD (eg, 1.8 VDC) and provides the high level voltage VC (eg, 4 VDC) to the bit line to Cellular transistor. After receiving the pump output voltage VC, the total current IC flowing through the cell transistors M1, 1, M1, 2, M1, 3 and M1, 4 is increased to 220 μA. This voltage VC maintains a high level until time t1. At time t1, the total current flowing through the cell transistors M1, 1, M1, 2, M1, 3 and M1, 4 is reduced to about 50 μA. After time t1, the pump circuit 39 stops operating and the level of the pump output voltage VC is reduced to the power supply voltage VDD. The time interval to to t1 in Fig. 5 is a pulse width which is an effective time interval for a stylized operation. In this example, to to t1 is about 1 μS.

As shown in FIG. 5, the four unit cell transistors are selectively programmed between time intervals t1 and t1, so an instantaneous current of 220 μA is required to perform the operation. In recent years, the trend of semiconductor memory components has been highly integrated. Therefore, tens of thousands of cells will be integrated into a single memory component to store more data. In order to program a 16K bit memory element, which consists of an array of 128 x 128 cells, a considerable amount of current is required and the total programmed time can be long. Accordingly, it is necessary to propose an improved stylized method to solve the above problems.

It is an object of the present invention to provide a method of stabilizing a plurality of memory cells in a non-volatile semiconductor memory device. By the method disclosed by the present invention, the total time and total instantaneous power loss of the memory cells can be greatly reduced.

In order to achieve the above object, an embodiment of the method of the present invention comprises the steps of: dividing the memory cells into M groups of memory, wherein M is an integer; continuously selecting one of the M groups of memory groups; M sets of overlapping pulse wave signals are continuously generated; and memory cells of each of the M sets of memory sets are individually programmed in response to each of the M sets of overlapping pulse wave signals.

Another object of the present invention is to provide a non-volatile semiconductor memory component. With the component configuration disclosed in the present invention, the total time and total instantaneous power loss of a plurality of memory cells in the non-volatile semiconductor memory device can be greatly reduced.

To achieve the above object, an embodiment of the non-volatile semiconductor memory device of the present invention comprises a plurality of memory cells divided into M groups of memory groups ( Where M is an integer), a decoder, and a sequential circuit. The decoder is configured to continuously select one of the M sets of memory groups. The sequential circuit is configured to continuously generate M sets of overlapping pulse signals. The memory cells of each of the M sets of memory sets are programmed in response to corresponding overlapping pulse signals.

In order to clarify the method of stabilizing a plurality of memory cells in a semiconductor memory device disclosed in the present invention, the architecture of the semiconductor memory device in the present invention for performing the method will first be described. Figure 6 shows a block diagram of a semiconductor memory device 60 incorporating one embodiment of the present invention. Referring to FIG. 6, the memory device 60 includes the memory array 32 shown in FIG. 3, the row decoding and level conversion circuit 34, the column decoding and level conversion circuit 36, the input/output circuit 38, and a control circuit. 64.

FIG. 7 shows a partial schematic view of the memory array 32 shown in FIG. For the sake of brevity, the memory array 32 in FIG. 7 shows only a single word line WL0, first to sixteenth bit lines BL0 to BL15, and first to sixteenth memory cell transistors. M1, 1 to M1, 16. However, the invention should not be limited thereto. Referring to FIG. 7, the memory cell transistors M1, 1 to M1, 16 are arranged in a matrix, and each transistor is connected to one of the word line WL0 and the bit lines BL0 to BL15. As shown in FIG. 7, the unit cell transistors M1,1 to M1,16 are classified into first to fourth groups GROUP1, GROUP2, GROUP3, and GROUP4. Therefore, in this embodiment each group consists of four unit cell transistors.

Referring now to Figure 6, to program a plurality of memory cell transistors in the memory array 32, the control circuit 64 is responsive to the input/output circuit 38. The output of a mode signal PGM produces a pump output voltage VH to the row decode and level conversion circuit 34. During the staging operation, the column decode and level conversion circuit 36 is responsive to a column of address signals AR output by the input/output circuit 38 to select a word line in the memory array 32. In this manner, the unit cell transistors in the first to fourth groups GROUP1, GROUP2, GROUP3, and GROUP4 are continuously selected. The pump output voltage VH is applied to the cell transistors in the selected group by the selected bit line.

FIG. 8 shows a block diagram of the control circuit 64 in conjunction with an embodiment of the present invention. Referring to FIG. 8, the control circuit 64 includes a timing circuit 642 and a pump circuit 644. The timing circuit 642 receives the mode signal PGM and an internal clock signal CLK synchronized to an external clock signal XCLK to generate a plurality of consecutive overlapping pulse signals PH1, PH2, PH3, and PH4 during the stylizing operation. The pump circuit 644 is responsive to the overlapping pulse signals PH1, PH2, PH3, and PH4 to generate the pump output voltage VH, wherein the pump output voltage VH is at a higher level than the power supply voltage VDD. In the present embodiment, the pump circuit 644 is an internal circuit. In other embodiments of the invention, the pump circuit 644 is disposed external to the memory element 60 to minimize the area and complexity of the interior of the wafer.

FIG. 9 shows a circuit diagram of one embodiment of the sequential circuit 642 shown in FIG. Referring to FIG. 9, the timing circuit 642 includes a logic circuit 6422 and a delay circuit 6424. The logic circuit 6422 receives the mode signal PGM and the clock signal CLK to generate the first pulse signal PH1. The delay circuit 6424 is composed of three serially connected D-type flip-flops D1, D2 and D3. The delay circuit 6424 is configured to generate a plurality of delayed signals of the input signal PH1 having a specific delay as continuous overlapping pulse signals.

FIG. 10 shows a possible timing diagram of one of the timing circuits 642 shown in FIG. Referring to FIG. 10, when the mode signal PGM is activated, the first pulse signal PH1 is enabled in response to the rising edge of the clock signal CLK at time t1. In the present embodiment, the pulse wave width of the pulse wave signal PH1 is 2 × T, where T is the pulse width of the clock signal CLK.

Referring to FIG. 9 and FIG. 10, after receiving the pulse wave signal PH1, the D-type flip-flop D1 in the delay circuit 6424 generates a delay signal PH2 of the input signal PH1 at time t2, wherein the signal PH2 and the signal PH1 have a Specific delay T. Next, the D-type flip-flop D2 receives the signal PH2 to generate a delayed signal PH3 of the input signal PH2 at time t3, wherein the signal PH3 has a specific delay T with the signal PH2. Next, the D-type flip-flop D3 receives the signal PH3 to generate a delayed signal PH4 of the input signal PH3 at time t4, wherein the signal PH4 has a specific delay T with the signal PH3. In this manner, the timing circuit 642 can generate successive overlapping pulse signals PH1, PH2, PH3, and PH4 having the same pulse wave overlap amount T as shown in FIG.

In the above embodiment, the pulse signals PH1 to PH4 have the same pulse width 2 × T, and the pulse signals have the same pulse wave overlap amount T. However, the pulse width and amount of overlap of the pulse wave signal can be varied in other embodiments. For example, the pulse widths of the pulse signals PH1 to PH4 can be designed to be any multiple of the period T, and the amount of pulse wave overlap between the two consecutive pulse signals can also be adjusted.

Figure 11 shows a possible timing diagram of the memory component 60 during a stylized operation. Please refer to FIG. 6 to FIG. 11 below for details of the operation. Referring to Figures 6 and 11, the first set of GROUP1 in memory array 32 between time t1 and t3 is first selected by circuits 32 and 34. Therefore, the pump output voltage VH is applied to the cell transistors M1,1, M1,2, M1,3 and M1,4 of the first group of GROUP1 by the bit lines BL0, BL1, BL2 and BL3 of FIG. Next, the second set of GROUP2 will be selected by circuits 32 and 34 between times t2 and t4. Therefore, the pump output voltage VH is applied to the cell transistors M1, 5, M1, 6, M1, 7 and M1, 8 of the second group GROUP2 via the bit lines BL4, BL5, BL6 and BL7. The third set of GROUP3 will be selected by circuits 32 and 34 between times t3 and t5. Therefore, the pump output voltage VH is applied to the cell transistors M1, 9, M1, 10, M1, 11 and M1, 12 of the third group GROUP3 via the bit lines BL8, BL9, BL10 and BL11. In this manner, the first to fourth groups of memory elements 60 are sequentially selected, and the pump output voltage VH is applied to the selected group of unit cell transistors during the staging operation.

Referring to FIG. 11, since the unit cell transistors M1,1 to M1,16 shown in FIG. 7 are divided into groups, and the stylized operation is sequentially performed on different groups, the instantaneous power loss of the overall operation is greatly reduced. . In addition, since the pulse signals of each group of unit cell transistors are programmed to overlap each other, the stylized method of the present invention can greatly reduce the total stylization time.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

10‧‧‧flash EEPROM cell

11‧‧‧P type substrate

12‧‧‧Deep N well

13‧‧‧P type well

14‧‧‧N-type source region

15‧‧‧N type bungee area

16‧‧‧Insulation

17‧‧‧Floating gate

18‧‧‧Insulation

19‧‧‧Control gate

30‧‧‧Non-volatile semiconductor memory components

32‧‧‧Memory array

34‧‧‧ row decoding and level conversion circuits

36‧‧‧ column decoding and level conversion circuit

38‧‧‧Input/output circuits

39‧‧‧ pump circuit

60‧‧‧ memory components

64‧‧‧Control circuit

642‧‧‧Sequence Circuit

6422‧‧‧Logical Circuit

6424‧‧‧Delay circuit

644‧‧‧ pump circuit

Figure 1 shows a vertical cross-sectional view of a flash EEPROM cell; Figure 2 shows the flash EEPROM cell in stylized operation and erase FIG. 3 shows a block diagram of a conventional non-volatile semiconductor memory device; FIG. 4 shows a partial schematic view of the memory array shown in FIG. 3; FIG. 5 shows a conventional stylized operation. FIG. 6 is a block diagram showing a semiconductor memory device in accordance with an embodiment of the present invention; FIG. 7 is a partial schematic view showing the memory array shown in FIG. 6; A block diagram of the control circuit of an embodiment of the present invention; FIG. 9 is a circuit diagram of an embodiment of the sequential circuit shown in FIG. 6; FIG. 10 shows a possible timing diagram of the sequential circuit shown in FIG. 9; A possible timing diagram of the memory component during the stylization operation is displayed.

60‧‧‧ memory components

32‧‧‧Memory array

34‧‧‧ row decoding and level conversion circuits

36‧‧‧ column decoding and level conversion circuit

38‧‧‧Input/output circuits

64‧‧‧Control circuit

Claims (5)

A non-volatile semiconductor memory component comprising: a plurality of memory cells divided into M groups of memory groups, wherein M is an integer; a decoder for continuously selecting one of the M groups of memory groups; a logic circuit for receiving a mode signal and an internal clock signal synchronized to an external clock signal to generate a first pulse signal; and a delay circuit for receiving the first pulse signal in response to the M sets of overlapping pulse signals are continuously generated by internal clock signals; wherein memory cells of each of the M memory groups are programmed in response to corresponding overlapping pulse signals; and wherein the M groups overlap The pulse wave overlap amount and the pulse wave width of the wave signal are adjusted by the pulse width of the internal clock signal. The non-volatile semiconductor memory component of claim 1, further comprising: a pump circuit responsive to the M sets of overlapping pulse signals to generate a pump output voltage, wherein the pump output voltage is higher than a power source The voltage level is supplied; wherein the memory cells of each of the M memory groups are programmed by the pump output voltage. According to claim 1, the non-volatile semiconductor memory device, wherein when the pulse width of the internal clock signal is T, each of the M sets of overlapping pulse signals has the same pulse width 2×T, and The pulse wave overlap amount of each of the M sets of overlapping pulse wave signals is T. A non-volatile semiconductor memory device according to claim 1, wherein the delay circuit comprises a plurality of series-connected D-type flip-flops. The non-volatile semiconductor memory device of claim 1, wherein the M sets of overlapping pulse wave signals are generated in response to a rising edge and a falling edge of the internal clock signal.