TWI509708B - Method for fabricating mos transistor - Google Patents

Description

Method for fabricating a MOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a MOS transistor, and more particularly to a method of driving platinum metal on the surface of a metal halide into the metal ruthenium by a rapid thermal processing process.

In the process of semiconductor integrated circuit, metal-oxide-semiconductor (MOS) transistor is a very important electronic component, and as the size of semiconductor component becomes smaller and smaller, the manufacturing process of MOS transistor also has Many improvements have been made to produce small, high quality MOS transistors.

The conventional MOS transistor process is to form a lightly doped drain (LDD) in a substrate on opposite sides of the gate structure after forming a gate structure on the semiconductor substrate. Then, a spacer is formed on the side of the gate structure, and the gate structure and the sidewall are used as a mask, and then an ion implantation step is performed to form a source/drain region in the semiconductor substrate. In order to properly electrically connect the gate and source/drain regions of the transistor to the circuit, it is necessary to form a contact plug for conduction. Generally, the material of the contact plug is a metal conductor such as tungsten (W), aluminum or copper, but direct conduction between a material such as a gate structure, a source/drain region, or a single crystal germanium is not preferable; Therefore, in order to improve the Ohmic contact between the metal plug and the gate structure and the source/drain region, a metal telluride is usually formed on the surface of the gate structure and the source/drain region. ).

At present, most of the self-aligned silicide (salicide) processes are used to form metal halides; that is, after the source/drain regions are formed, cobalt (Co) and nickel are sequentially formed. a metal layer composed of Ni) and the like, covering the source/drain region and the gate structure, and then performing a first rapid thermal process (hereinafter referred to as RTP) to make a part of the nickel metal layer and the lower portion thereof The ruthenium atoms in the gate and source/drain regions react to form a transition metal halide. Next, the unreacted nickel in the first RTP process is removed by a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning method. A second RTP process is then performed to convert the transition metal halide into a metal halide having a lower resistance.

However, the cleaning process between the first RTP and the second RTP described above typically removes the unreacted metal completely. Even if some of the metal remains, it will concentrate on the surface of the metal halide and will not enter the junction between the metal halide and the semiconductor substrate. As a result, the distance between the PN junction between the source/drain region and the germanium substrate and the germanium metal layer is too close to induce junction leakage andpiping. Therefore, how to simplify and improve the current metal telluride process to solve the above problems is an important issue today.

Therefore, the present invention provides a method of fabricating a MOS semiconductor transistor to solve the problem that the junction leakage current is easily induced in the above-described metal telluride process.

A preferred embodiment of the invention discloses a method of fabricating a MOS transistor. Firstly, a semiconductor substrate is provided, the metal substrate is provided with a metal halide, and then a first rapid thermal processing process is performed to drive the platinum metal on the surface of the metal halide into the metal halide, and then the first rapid heat treatment process is removed. Unreacted platinum metal.

Another embodiment of the invention discloses a method of fabricating a MOS transistor. First, a semiconductor substrate is provided. The semiconductor substrate is provided with a source/drain region, and then a nickel-platinum metal layer and a barrier layer are formed on the surface of the source/drain region to perform a first rapid thermal processing process. The nickel-platinum metal layer reacts with the source/drain region to form a metal halide, removes the unreacted nickel metal and the barrier layer in the first rapid thermal processing process, and performs a second rapid heat treatment process to form a surface of the nickel-platinum metal layer The platinum metal is driven into the metal halide, the unreacted platinum metal in the second rapid thermal processing process is removed, and a third rapid thermal processing process is performed to reduce the resistance of the metal halide.

Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are schematic diagrams showing a process for fabricating a MOS transistor according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 100, such as a wafer or a silicon-on-insulator (SOI) substrate, is provided first, and the gate may be included in the substrate or in the substrate for different product requirements and process designs. a germanium-containing structure such as an electrode, a source/drain region, an insulating region, a word line, a diode, a thermal fuse or a resistor, and in the preferred embodiment of the first to fifth embodiments of the present invention, MOS is used. The gate structure 106, the source/drain region 112, and the insulating region 128 of the crystal will be described. As shown in FIG. 1, the gate structure 106 includes a gate dielectric layer 102 and a gate electrode 104. The gate dielectric layer 102 may be composed of one or more of a silicon oxide compound, a nitrogen compound, a nitrogen oxide compound, a metal oxide, etc., and the gate electrode 104 is doped polysilicon, metal deuteration. A conductive material such as a substance, a metal compound or a metal.

Subsequently, a lightly doped ion implantation process is performed, and a lightly doped material (not shown) is implanted into the semiconductor substrate 100 on opposite sides of the gate electrode 104 by using the gate electrode 104 as a mask. A source/drain extension (SDE) or a lightly doped source/drain 110 is formed. The type of impurity implanted is related to the type of MOS; if the NMOS is implanted with N-type impurities such as phosphorus or arsenic, if the PMOS is implanted with P-type impurities such as boron. It should be noted that prior to the source/drain extension or lightly doped source/drain formation, selective sidewalls may be formed on the surrounding sidewalls of the gate structure 106 using thermal oxidation or deposition and etching processes (not shown). Therefore, when performing the lightly doped ion implantation process, the gate electrode 104 and the selective sidewall are used as masks to implant impurities.

Next, a selective liner layer 107, such as an oxygen layer, and a single sidewall or a plurality of sidewalls 108 composed of a nitrogen ruthenium compound are formed on the sidewalls of the gate structure 106 by a deposition and etching process. The material of the backing layer 107 and the sidewall spacers 108 may be any insulating material. Then, a heavily doped ion implantation process is performed, and a gate electrode 108 and the sidewall spacers 108 are used as a mask, and a heavily doped substance (not shown) is implanted into the semiconductor substrate 100 to form an impurity in the semiconductor substrate 100. A source/drain region 112 having a higher impurity concentration. Similar to the implantation type of the lightly doped source and the drain 110, the NMOS is implanted with an N-type impurity such as phosphorus or arsenic, and the PMOS is implanted with a P-type impurity such as boron. A high temperature tempering process is then performed to activate the doping in the semiconductor substrate 100 using a high temperature of 1000 to 1050 ° C, and simultaneously repair the crystal on the surface of the semiconductor substrate 100 damaged in each ion implantation process. Grid structure.

It should be understood by those skilled in the art that although the above aspects of the present invention describe in detail the formation of the sidewall, lightly doped source/drain, source/drain, the invention is not limited thereto. All manufacturing methods and fabrication processes capable of forming sidewalls, lightly doped source/drain, source/drain are included in the scope of the present invention. For example, the order in which the sidewalls, the lightly doped source/drain, and the source/drain are formed may vary. In one embodiment, a single or a plurality of sidewalls may be formed first, followed by source/drain formation, and finally the outermost layer of the single sidewall or plurality of sidewalls may be removed for implantation of the lightly doped source/drain. In another embodiment, in addition to the original sidewall, lightly doped source/drain, source/drain formation, the strain-clamp process can be integrated to precede the gate/drain formation. A groove is formed on both sides of the pole structure and a material required for each of the NMOS and PMOS, such as tantalum carbide (SiC), germanium telluride (SiGe), or the like, is grown in the trench in an epitaxial manner.

A self-aligned silicide (salicide) process is then performed to form the metal telluride. As shown in FIG. 2, a cleaning step is first performed to remove the native oxide or other impurities on the surface of the gate structure 106 and the source/drain region 112, and then a thin film deposition process is performed. The gate structure 106 and the source/drain region 112 are sequentially formed with a metal layer 114 having a thickness of about 150 to 200 angstroms and a barrier layer composed of titanium nitride (TiN) having a thickness of about 100 to 200 angstroms. Layer) 116. The metal layer 114 mainly comprises a first metal such as nickel (Ni), cobalt (Co), titanium (Ti) or an alloy thereof, which is useful for forming a metal telluride, and at the same time contains a low concentration of a second metal such as platinum (Pt). ), cobalt (Co), palladium (Pd), manganese (Mo), tantalum (Ta), ruthenium (Ru) or alloys thereof. The addition of the second metal is caused by the occurrence of agglomeration when the first metal forms a metal telluride, and the generation of agglomerates causes an increase in the contact resistance of the contact plug and leakage of the junction. The problem of junction leakage is to add 3 to 8% of the thermally stable second metal to the metal layer 114 to increase the thermal stability of the metal telluride and to avoid agglomeration in the high temperature at which the metal telluride is formed. In this embodiment, the first metal is, for example, nickel, and the second metal is platinum. Of course, in other variations of the embodiment, the first metal may also be cobalt or titanium, and the second metal may also be palladium. , manganese, strontium, barium, etc. Next, as shown in FIG. 3, a first Rapid Thermal Process (hereinafter referred to as RTP) is performed to cover the metal layer 114 and the germanium over the gate structure 106 and the source/drain region 112. The reaction produces a transition metal halide 118 and simultaneously defines the thickness of the metal halide 118. These steps are well known to those skilled in the art and those of ordinary skill in the art, and thus will not be described again.

Please refer to FIG. 4 and FIG. 5 to FIG. 7 simultaneously. FIG. 4 is a flow chart of the first RTP process according to the preferred embodiment of the present invention, and FIG. 5 to FIG. 7 are With the process diagram of Figure 4. As shown in the figure, step 132 is first performed, that is, the first RTP process described above, to react the nickel and platinum metal layers with ruthenium into a transition metal ruthenium. In this embodiment, the implementation temperature of the first RTP process is less than 300 ° C, preferably between 240 ° C and 290 ° C; and the implementation time is preferably between 30 seconds and 120 seconds.

Then, in step 134, the barrier layer 116 composed of titanium nitride and the unreacted in the first RTP process are removed by a sulfuric acid-hydrogen peroxide mixture (SPM) cleaning process. Nickel metal, but as shown in Fig. 5, at this time, a part of the unreacted platinum metal 117 remains on the surface of the transition metal halide 118. In this embodiment, the execution time of the cleaning process is preferably from 500 seconds to 700 seconds, and preferably 600 seconds; the implementation temperature is preferably 95 ° C; and the volume percentage of sulfuric acid and hydrogen peroxide is preferably 800:200. .

Next, in step 136, a second RTP process, platinum metal remaining on the surface of the metal telluride 118 is driven into the metal halide 118, such as the junction of the metal halide 118 and the source/drain region 112. By the barrier formed by the platinum metal at this junction, the present invention can block the nickel atoms in the metal telluride 118 from being drilled into the semiconductor substrate 100 to induce junction leakage and cause a conduction effect. In this embodiment, the process parameters used in the second RTP process are preferably equivalent to those used in the first RTP process, for example, the implementation temperature is preferably between 240 ° C and 290 ° C; and the implementation time is preferably between 30 seconds to 120 seconds.

Then, in step 138, a hydrogen chloride-hydrogen peroxide mixture (HPM) cleaning process is used to remove the platinum metal remaining unreacted in the second RTP process. It should be noted that the cleaning process preferably removes the platinum metal remaining on the surface of the transition metal halide 118, but does not affect any platinum metal that has been driven into the transition metal halide 118, and the thickness of the transition metal halide 118. Substantially will not change. In this embodiment, the implementation time of the HPM cleaning process is between 210 seconds and 410 seconds, and preferably 310 seconds; the implementation temperature is preferably 50 ° C; and the volume percentage of the mixture of hydrogen chloride and hydrogen peroxide is preferably 800. :600. A further cleaning process can then be selectively performed to remove the remaining barrier layer 116 and unreacted nickel metal again using SPM.

Then, an ammonia hydrogen peroxide mixture (APM) cleaning process may be selectively performed to remove residues on the surface of the semiconductor substrate 100. In this embodiment, the implementation time of the APM cleaning process is between 20 seconds and 220 seconds, and preferably 120 seconds; the implementation temperature is preferably 60 ° C; and the volume percentage of ammonia water, hydrogen peroxide and water is preferably 60:120:2400.

Then, step 140, a third RTP process, is performed to convert the transition metal halide 118 into a metal halide having a lower resistance. In this embodiment, the third RTP process may be a spike anneal process, and the implementation temperature is greater than 300 ° C, and preferably between 400 ° C and 500 ° C.

After the third RTP process is completed, as shown in FIG. 7, a contact etch stop layer (CESL) 120 may be directly formed and overlaid on the metal telluride 118. The contact hole etch stop layer 120 can selectively form the contact hole etch stop layer 120 having a compressive stress or a tensile stress depending on the NMOS and PMOS characteristics.

As shown in FIG. 8, an interlayer dielectric (ILD) 122 mainly composed of an oxide is formed on the semiconductor substrate 100 and covers the contact hole etch stop layer 120. The interlayer dielectric layer 122 may comprise one or more of a nitride, an oxide, a carbide, and a low-k material.

Then, a contact plug process is performed, and a patterned photoresist (not shown) is used as a mask in the interlayer dielectric layer 122 and the contact hole etch stop layer 120 to etch a plurality of contact holes 124 and expose the gate. The metal structure 118 on the gate structure 106 and the source/drain region 112. A metal material consisting of titanium nitride (TiN), tungsten or other conductors is then implanted in the contact holes 124 to form a plurality of metal germanium gates 118 electrically connected to the gate electrode 104 and the source/drain regions 112. Contact plug 126. Thus, the preferred embodiment of the present invention has been completed to fabricate a metal oxide semiconductor crystal structure having a metal telluride.

It should be noted that this embodiment can also be integrated into the gate-last for high-k first and the post-high dielectric constant before the contact plug process. The dielectric layer is gate-last for high-k last, and a metal oxide semiconductor transistor having a metal gate of a high dielectric constant dielectric layer is formed. Furthermore, the present invention is also applicable to other various types of semiconductor elements, such as non-planar self-aligned silicides (salicides) such as fin-FETs. ) in the process.

It is conventionally known that the cleaning process between the two RTP processes described above generally consumes the platinum metal, and even if some of the platinum metal remains, it will concentrate on the surface of the metal halide and cannot enter the metal halide and the semiconductor substrate. At the junction between the two, the present invention mainly performs an RTP process after removing the nickel metal in the barrier layer and the metal telluride, and drives the platinum metal on the surface of the metal halide to the boundary between the bottom of the metal halide and the semiconductor substrate. After that, the platinum metal on the surface of the metal halide is removed and another RTP process is performed to convert the transition metal halide into a metal halide having a lower resistance. By the above RTP process, the present invention can utilize the driven platinum metal to form a barrier at the interface between the metal telluride and the semiconductor substrate, thereby blocking the nickel atoms in the metal telluride from being drilled into the semiconductor substrate to induce junction leakage. The conduction effect and improve the quality of the entire metal halide.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Semiconductor substrate

102. . . Gate dielectric layer

104. . . Gate electrode

106. . . Gate structure

107. . . Liner layer

108. . . Side wall

110. . . Lightly doped source/drain

112. . . Source/drain region

114. . . Metal layer

116. . . Barrier layer

117. . . Platinum metal

118. . . Metal telluride

120. . . Contact hole etch stop layer

122. . . Interlayer dielectric layer

124. . . Contact hole

126. . . Contact plug

128. . . Insulated area

1 to 3 are schematic views showing a process for fabricating a MOS transistor according to a preferred embodiment of the present invention.

Figure 4 is a flow chart of the preferred embodiment of the present invention after the first RTP process.

Figure 5 to Figure 8 are schematic diagrams of the process performed after the first RTP process.

100. . . Semiconductor substrate

107. . . Liner layer

108. . . Side wall

110. . . Lightly doped source/drain

112. . . Source/drain region

118. . . Metal telluride

120. . . Contact hole etch stop layer

122. . . Interlayer dielectric layer

124. . . Contact hole

126. . . Contact plug

128. . . Insulated area

Claims (14)

A method of fabricating a MOS transistor, comprising the steps of: providing a semiconductor substrate having a metal ruthenide thereon; performing a first rapid thermal processing process after forming the metal ruthenium, the metal telluride Platinum metal on the surface is driven into the metal halide; and unreacted platinum metal in the first rapid thermal processing process is removed. The method of claim 1, wherein the semiconductor substrate has a source/drain region, and the source/drain region is provided with the metal telluride, and further comprises: forming a nickel-platinum metal Layered on the surface of the source/drain region; forming a barrier layer on the surface of the nickel-platinum metal layer; and performing a second rapid thermal processing process to react a portion of the source/drain region to the metal halide. The method of claim 2, wherein the temperature of the first rapid thermal processing process and the second rapid thermal processing is between 240 ° C and 290 ° C. The method of claim 2, wherein the first rapid thermal processing process and the second rapid thermal processing time are between 30 seconds and 120 second. The method of claim 1, wherein the removing the unreacted platinum metal further comprises performing a third rapid thermal processing to reduce the resistance of the metal halide. The method of claim 5, wherein the temperature of the third rapid thermal processing process is greater than 300 °C. The method of claim 1, wherein the barrier layer comprises titanium nitride (TiN). The method of claim 2, further comprising: removing a non-reactive nickel metal in the second rapid thermal processing process by using a sulfuric acid-hydrogen peroxide mixture (SPM) and the a barrier layer; and a hydrochloric acid-hydrogen peroxide mixture (HPM) to remove unreacted platinum metal in the first rapid thermal processing. A method of fabricating a MOS transistor, comprising the steps of: providing a semiconductor substrate having a source/drain region disposed thereon; Forming a nickel-platinum metal layer and a barrier layer on the surface of the source/drain region; performing a first rapid thermal processing process to react a portion of the nickel-platinum metal layer with the source/drain region to form a metal halide; Removing the unreacted nickel metal and the barrier layer in the first rapid thermal processing process; performing a second rapid thermal processing process, driving the platinum metal on the surface of the nickel platinum metal layer into the metal halide; removing the second The unreacted platinum metal in the rapid heat treatment process; and a third rapid heat treatment process to reduce the resistance value of the metal telluride. The method of claim 9, wherein the first rapid thermal processing process and the second rapid thermal processing temperature are between 240 ° C and 290 ° C. The method of claim 9, wherein the first rapid thermal processing process and the second rapid thermal processing time are between 30 seconds and 120 seconds. The method of claim 9, wherein the temperature of the third rapid thermal processing process is greater than 300 °C. The method of claim 9, wherein the barrier layer comprises titanium nitride (TiN). The method of claim 9, further comprising: removing the unreacted nickel metal and the barrier layer in the first rapid thermal processing process by using a mixture of monosulfuric acid and hydrogen peroxide (SPM); and utilizing hydrogen chloride A mixture of hydrogen peroxide (HPM) is used to remove unreacted platinum metal in the second rapid thermal processing.