TWI508190B - Thin film transistor and method for manufacturing the same - Google Patents

Description

Thin film transistor and method of manufacturing same

The present invention relates to a thin film transistor of an oxide semiconductor and a method of manufacturing the same.

The liquid crystal display is mainly composed of a thin film transistor substrate, a color filter substrate, and a liquid crystal molecular layer between the two substrates. A plurality of thin film transistors are disposed on the thin film transistor substrate, and each of the thin film transistors is mainly composed of a gate, a gate dielectric layer, a semiconductor layer, a source, and a drain. The material of the semiconductor layer may include, for example, an amorphous germanium, a polycrystalline germanium, a microcrystalline germanium, a single crystal germanium, an organic semiconductor, an oxide semiconductor, or other suitable material.

However, the oxide semiconductor thin film transistor has higher carrier mobility (Mobility) than the amorphous germanium thin film transistor, and has better electrical performance. Oxide semiconductors usually require an annealing process to stabilize the electrical properties of the thin film transistor. In general, the temperature of the annealing process needs to be higher than 350 ° C.

However, in the annealing process, if the metal is exposed to the high temperature furnace, the metal will be oxidized, causing the impedance to rise, which seriously affects the signal transmission. In view of the above, there is a need for an improved method of fabricating a thin film transistor to solve the above problems.

An object of the present invention is to provide a method for manufacturing a thin film transistor, It can avoid the problem of increased impedance caused by oxidation of the source and the drain during the annealing process.

One aspect of the present invention provides a method of producing a thin film transistor comprising the following steps. Source and bungee are available. Forming a patterned insulating layer partially covers the source and drain electrodes and exposes a portion of the source and a portion of the drain. The oxide semiconductor layer is formed to contact the portion of the source and the portion of the drain. Provide a gate. A gate dielectric layer is provided between the oxide semiconductor layer and the gate.

According to an embodiment of the present invention, after the step of forming the oxide semiconductor layer, an annealing step is performed.

According to an embodiment of the invention, the step of providing a gate dielectric layer is performed prior to the step of providing a source and a drain.

According to an embodiment of the invention, the step of providing a gate dielectric layer is performed after the step of providing a source and a drain.

According to an embodiment of the invention, the step of forming the pattern insulating layer comprises: forming an insulating layer covering the source and the drain in a comprehensive manner; and forming at least one opening in the insulating layer to expose the portion of the source and the portion of the drain.

According to an embodiment of the invention, the step of forming the pattern insulating layer comprises: forming an insulating layer covering the source and the drain in a comprehensive manner; forming a first opening and a second opening in the insulating layer respectively exposing the portion of the source and the 汲This part of the pole.

Another aspect of the present invention provides a thin film transistor comprising a source and a drain, a pattern insulating layer, an oxide semiconductor layer, a gate and a gate dielectric layer. The patterned insulating layer partially covers the source and the drain, wherein the patterned insulating layer has at least one opening exposing a portion of the source and a portion of the drain. Oxide semiconductor The bulk layer contacts the portion of the source and the portion of the drain. The gate dielectric layer is between the oxide semiconductor layer and the gate.

According to an embodiment of the invention, the opening is substantially aligned with the gate.

According to an embodiment of the invention, the pattern insulating layer has only one opening, and the length of the opening is greater than a distance between the source and the drain.

According to an embodiment of the invention, the gate dielectric layer is under the source and the drain. According to an embodiment of the invention, the opening includes a first opening and a second opening respectively exposing the portion of the source and the portion of the drain.

According to an embodiment of the invention, the gate dielectric layer is above the source and drain.

In the embodiment of the present invention, a pattern insulating layer is partially formed to cover the source and the drain, and then a portion of the source and a portion of the drain exposed by the oxide semiconductor layer are sequentially formed, and an annealing process is performed. In this way, when the annealing process is performed, the source and the drain are covered by the pattern insulating layer and the oxide semiconductor layer, and are not exposed at all, so that oxidation of the source and the drain can be avoided.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

1 is a view showing a thin film transistor substrate according to an embodiment of the present invention. Flow chart of the manufacturing method. 2A is a top plan view showing a thin film transistor substrate in accordance with an embodiment of the present invention. The circuit layout of the thin film transistor substrate can be appropriately changed, and is not limited to the example of FIG. 2A. Fig. 2B is a schematic cross-sectional view showing the thin film transistor along line 2B-2B' of Fig. 2A. In general, the type of thin film transistor is, for example, a top gate type or a bottom gate type. In the type of bottom gate type thin film transistor, the gate is located below the semiconductor layer; in the type of top gate type thin film transistor, the gate is located above the semiconductor layer. 2A-2B is an example of a bottom gate type thin film transistor, but is not limited thereto.

In step 10, a substrate 110 is provided, as shown in Figure 2B. The substrate 110 needs to have sufficient mechanical strength, which may be, for example, glass, quartz, a transparent polymer material, or other suitable material.

In step 20, a gate 120 is formed on the substrate 110 as shown in Figures 2A-2B. As shown in FIG. 2A, when the gate 120 is formed, a plurality of mutually parallel scanning lines SL can be simultaneously formed on the substrate 110. Of course, a common electrode line (not shown) may be simultaneously formed on the substrate 110. The common electrode line may be parallel to the extending direction of the scanning line SL. For example, a metal layer (not shown) may be formed on the substrate 110 by sputtering, evaporation, or other thin film deposition techniques, and the gate 120 and the scan line SL are formed by a photolithography process. .

In step 30, gate dielectric layer 130 is formed to cover gate 120, as shown in FIG. 2B. Of course, the gate dielectric layer 130 can also cover a plurality of scan lines SL. The gate dielectric layer 130 may be a single layer or a multilayer structure, and the material thereof may include an organic dielectric material, an inorganic dielectric material, or a combination thereof. The organic dielectric material is, for example, Polyimide (PI), other suitable materials or a combination thereof; inorganic The dielectric material is, for example, yttria, tantalum nitride, ytterbium oxynitride, other suitable materials, or a combination thereof. The gate dielectric layer 130 can be formed using chemical vapor deposition (CVD) or other suitable thin film deposition techniques.

In step 40, source 140a and drain 140b are formed on gate dielectric layer 130 as shown in FIG. 2A-2B. As shown in FIG. 2A, when the source 140a and the drain 140b are formed, a plurality of mutually parallel data lines DL can be simultaneously formed. The data line DL and the scan line SL are vertically interdigitated to define a plurality of sub-pixel regions of the substrate 110. For example, a metal layer (not shown) may be formed on the gate dielectric layer 130 by sputtering, evaporation, or other thin film deposition techniques, and the source 140a may be formed by a photolithography process. The pole 140b and the data line DL. The gate 120, the source 140a, and the drain 140b may be a single layer or a multilayer structure, and the material may be a metal or a metal compound. The metal material includes molybdenum (Mo), chromium (Cr), aluminum (Al), niobium (Nd), titanium (Ti), copper (Cu), silver (Ag), gold (Au), zinc (Zn), indium ( In), gallium (Ga), other suitable materials, or a combination of the above. The metal compound material comprises a metal alloy, a metal oxide, a metal nitride, a metal oxynitride, other suitable materials, or a combination thereof.

In step 50, the patterned insulating layer 150 is partially covered with the source 140a and the drain 140b, and a portion of the source 140a and a portion of the drain 140b are exposed, as shown in FIG. 2B. Of course, the graphic insulating layer 150 can completely cover the data lines DL in the same layer as the source 140a and the drain 140b. The patterned insulating layer 150 is used to protect the source 140a, the drain 140b, and other components of the same layer (such as the data line DL) from oxidation by the subsequent annealing process (ie, step 70). Therefore, the contact resistance of the drain electrode 140b and the transparent electrode, the data line DL The impedance etc. will not be affected by the annealing process. The material of the graphic insulating layer 150 may be a single layer or a multilayer structure, and the material thereof may include a high temperature resistant organic dielectric material, an inorganic dielectric material, or a combination thereof. The organic dielectric material is, for example, Polyimide (PI), other suitable materials, or a combination thereof; the inorganic dielectric material is, for example, cerium oxide, cerium nitride, cerium oxynitride, other suitable materials, or a combination thereof. .

In one embodiment, the step of forming the pattern insulating layer 150 includes forming an insulating layer (not shown) to completely cover the source 140a and the drain 140b, and forming at least one opening 150' in the insulating layer to expose a portion of the source 140a. And part of the drain 140b, as shown in Figure 2B. The position of the opening 150' is a region where the oxide semiconductor is intended to be in contact with the source 140a and the drain 140b. For example, an insulating layer (not shown) may be formed by chemical vapor deposition (CVD) or other suitable thin film deposition technique, and the opening 150' may be formed by a photolithography process.

In another embodiment, as shown in FIG. 3, an insulating layer (not shown) is formed to completely cover the source 140a and the drain 140b, and a first opening 150'a and a first layer are formed in the insulating layer. The two openings 150'b expose a portion of the source 140a and a portion of the drain 140b, respectively. Of course, in practical applications, the number and position of the openings of the pattern insulating layer 150 are not limited to those illustrated in FIGS. 2B and 3 .

In step 60, the oxide semiconductor layer 160 is formed to contact the portion of the source 140a and the portion of the drain 140b as shown in FIG. 2A-2B. The oxide semiconductor layer 160 may be a single layer or a multilayer structure, and may be made of, for example, zinc oxide (ZnO), zinc tin oxide (ZnSnO), chromium tin oxide (CdSnO), gallium tin oxide (GaSnO), or titanium oxide tin (TiSnO). ), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), copper aluminum oxide (CuAlO), copper bismuth oxide (SrCuO), Beryllium oxysulfide (LaCuOS), other suitable materials or combinations thereof. For example, a sputtering semiconductor (Sputtering) process may be used to form an oxide semiconductor material layer (not shown) to completely cover the portion of the pattern insulating layer 150, the source 140a, and the drain 140b, and then perform a photolithography process to form an oxide. Semiconductor layer 160.

In step 70, the oxide semiconductor layer 160 is subjected to an annealing process. Specifically, the laminated structure including the oxide semiconductor layer 160 and the source 140a and the drain electrode 140b coated with the pattern insulating layer 150 is placed in a high temperature furnace for annealing treatment, whereby an electrically stable oxide can be obtained. Semiconductor layer 160. The temperature of the annealing process is, for example, from about 350 ° C to about 400 ° C.

It is worth mentioning that, since the embodiment of the present invention sequentially forms the source 140a and the drain 140b, forms the pattern insulating layer 150, forms the oxide semiconductor layer 160, and performs an annealing process, the annealed oxide semiconductor layer 160 is completed. The wet process is not directly contacted, and the electrical properties of the oxide semiconductor layer 160 can be prevented from being affected by the wet process.

In step 80, a protective layer 170 is formed to cover the pattern insulating layer 150 and the oxide semiconductor layer 160 as shown in FIG. 2B. The protective layer 170 has a contact hole 170' exposing a portion of the drain 140b. The protective layer 170 is a single layer or a multilayer structure, and the material thereof may include an organic dielectric material, an inorganic dielectric material, or a combination thereof. Please refer to the material illustrated by the gate dielectric layer 130. For example, a protective material layer (not shown) may be formed by chemical vapor deposition (CVD) or other suitable thin film deposition technique, and the contact hole 170' may be formed by a photolithography process.

In step 90, a transparent electrode 180 is formed on the protective layer 170 and in the contact hole 170', so that the transparent electrode 180 is connected to the drain 140b, such as 2A-2B. The figure shows. The transparent electrode 180 may be a single layer or a multilayer structure, and the material thereof may be, for example, indium tin oxide (ITO), hafnium oxide (HfOx), aluminum zinc oxide (AZO), aluminum oxide tin (ATO), gallium zinc oxide (GZO), Indium titanium oxide (ITiO), indium oxide molybdenum (IMO) or other transparent conductive material. For example, a transparent conductive layer (not shown) may be formed on the protective layer 170 by a sputtering process or other thin film deposition process, and the transparent electrode 180 may be formed by a photolithography process.

Fig. 4 is a schematic cross-sectional view showing a top gate type thin film transistor according to still another embodiment of the present invention. In the method, after forming the oxide semiconductor layer, the gate dielectric layer and the gate are sequentially formed. The manufacturing method sequentially includes the following steps. First, the source 140a and the drain 140b are formed on a substrate 110. The patterned insulating layer 150 partially covers the source 140a and the drain 140b, and exposes a portion of the source 140a and a portion of the drain 140b. The oxide semiconductor layer 160 is formed to contact the portion of the source 140a and the portion of the drain 140b. The gate dielectric layer 130 is formed to cover the oxide semiconductor layer 160 and the pattern insulating layer 150. Gate 120 is formed on gate dielectric layer 130. The protective layer 170 is formed to cover the gate 120, and the protective layer 170 has a contact hole 170' exposing a portion of the drain 140b. A transparent electrode 180 is formed on the protective layer 170 and in the contact hole 170'.

Another aspect of the present invention provides a thin film transistor including a source 140a and a drain 140b, a pattern insulating layer 150, an oxide semiconductor layer 160, a gate 120, and a gate dielectric layer 130, such as 2B, 3, Figure 4 shows. The thin film transistor may be a bottom gate type exemplified in FIGS. 2B and 3 (ie, the gate dielectric layer 130 is located under the source 140a and the drain 140b) or a top gate type (ie, the gate illustrated in FIG. 4). The dielectric layer 130 is located above the source 140a and the drain 140b) a thin film transistor.

The pattern insulating layer 150 partially covers the source 140a and the drain 140b. The pattern insulating layer 150 has at least one opening 150' exposing a portion of the source 140a and a portion of the drain 140b, as shown in FIGS. 2B and 4.

In the present embodiment, the opening 150' is substantially aligned with the gate as shown in Figures 2B and 4. The length d of the opening is greater than the distance L between the source 140a and the drain 140b. L is the channel length.

In another embodiment, as shown in FIG. 3, the opening includes a first opening 150'a and a second opening 150'b exposing the portion of the source 140a and the portion of the drain 140b, respectively. Here, the proportional relationship between the distance L and the length d1 of the first opening 150'a or the length d2 of the second opening 150'b is defined.

As shown in FIGS. 2B, 3, and 4, the oxide semiconductor layer 160 covers the pattern insulating layer 150 and contacts the portion of the source 140a and the portion of the drain 140b. As a result, when the annealing process is performed, the source electrode 140a and the drain electrode 140b are covered by the pattern insulating layer 150 and the oxide semiconductor layer 160, and are not exposed at all. Therefore, oxidation of the source electrode 140a and the drain electrode 140b can be avoided.

In one embodiment, the substrate including the thin film transistor of the embodiment of the present invention may be combined with a counter substrate (not shown) and a display medium layer (not shown) to form a display panel. The display panel is, for example, a non-self-emissive display or a self-emissive display, but is not limited thereto.

In summary, embodiments of the present invention protect source, drain, and peer components by a patterned insulating layer. In this way, when the annealing process is performed, the components of the source, the drain and the same layer are not directly exposed to the high temperature furnace, thereby avoiding oxidation, thereby affecting impedance and signal transmission, and effectively solving the conventional technology. Problems encountered in the field.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

10, 20, 30, 40, 50, 60, 70, 80, 90 ‧ ‧ steps

110‧‧‧Substrate

120‧‧‧ gate

130‧‧‧gate dielectric layer

140a‧‧‧ source

140b‧‧‧汲polar

150‧‧‧graphic insulation

150'‧‧‧ openings

150'a‧‧‧ first opening

150'b‧‧‧ second opening

160‧‧‧Oxide semiconductor

170‧‧‧Protective layer

170'‧‧‧Contact hole

180‧‧‧Transparent electrode

D‧‧‧ opening length

D1‧‧‧ Length of the first opening

D2‧‧‧ Length of the second opening

DL‧‧‧ data line

L‧‧‧The distance between the source and the bungee

SL‧‧‧ scan line

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. Figure.

2A is a top plan view showing a thin film transistor substrate in accordance with an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view showing the thin film transistor along line 2B-2B' of Fig. 2A.

Fig. 3 is a schematic cross-sectional view showing a thin film transistor according to another embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view showing a thin film transistor according to still another embodiment of the present invention.

110‧‧‧Substrate

120‧‧‧ gate

130‧‧‧gate dielectric layer

140a‧‧‧ source

140b‧‧‧汲polar

150‧‧‧graphic insulation

150'‧‧‧ openings

160‧‧‧Oxide semiconductor

170‧‧‧Protective layer

170'‧‧‧Contact hole

180‧‧‧Transparent electrode

D‧‧‧ opening length

L‧‧‧The distance between the source and the bungee

Claims (12)

A method for manufacturing a thin film transistor, comprising the steps of: providing a source and a drain; forming a pattern insulating layer on the source and the drain, partially covering the source and the drain, and exposing a portion Forming an oxide semiconductor layer on the patterned insulating layer and contacting the portion of the source and the portion of the drain; providing a gate; and providing the oxide semiconductor A gate dielectric layer between the layer and the gate. The manufacturing method according to claim 1, further comprising performing an annealing step after the step of forming the oxide semiconductor layer. The manufacturing method of claim 1, wherein the step of providing the gate dielectric layer is performed before the step of providing the source and the drain. The manufacturing method of claim 1, wherein the step of providing the gate dielectric layer is performed after the step of providing the source and the drain. The manufacturing method of claim 1, wherein the forming the patterned insulating layer comprises: forming an insulating layer to completely cover the source and the drain; Forming at least one opening in the insulating layer exposes the portion of the source and the portion of the drain. The manufacturing method of claim 1, wherein the forming the pattern insulating layer comprises: forming an insulating layer covering the source and the drain; and forming a first opening and a second opening in the insulating layer, respectively The portion of the source and the portion of the drain are exposed. A thin film transistor comprising: a source and a drain; a patterned insulating layer on the source and the drain, and partially covering the source and the drain, wherein the patterned insulating layer has at least one opening exposed a portion of the source and a portion of the drain; an oxide semiconductor layer on the patterned insulating layer and contacting the portion of the source and the portion of the drain; a gate; and a gate dielectric layer, Located between the oxide semiconductor layer and the gate. The thin film transistor of claim 7, wherein the opening is substantially aligned with the gate. The thin film transistor of claim 7, wherein the patterned insulating layer has only one opening, the opening having a length greater than the source and the one of the drains spacing. The thin film transistor of claim 7, wherein the gate dielectric layer is located under the source and the drain. The thin film transistor of claim 7, wherein the opening comprises a first opening and a second opening respectively exposing the portion of the source and the portion of the drain. The thin film transistor of claim 7, wherein the gate dielectric layer is above the source and the drain.