TWI507905B - Method of patterning a substrate - Google Patents

Description

Method of patterning a substrate

The present invention relates to a method of patterning a substrate, and more particularly to a method of patterning a substrate using an electron beam lithography system.

The semiconductor integrated circuit (IC) industry has experienced remarkable growth. With the evolution of semiconductor integrated circuits in the technical aspects of materials and design, a generation of semiconductor integrated circuits has been developed, each of which has a smaller volume and higher circuit complexity than the previous generation. In the development of semiconductor integrated circuits, when the geometry (ie, the smallest component or line that can be fabricated in a manufacturing process) is reduced, the functional density (that is, the number of devices connected to each other on a wafer area) is generally Sexual growth. The above-described process of scale reduction is usually accompanied by the increase in production efficiency and the associated cost reduction, and the reduction in scale also increases the complexity of manufacturing semiconductor integrated circuits. Therefore, the development of semiconductor integrated circuits in processes and manufacturing methods also needs to progress at the same time.

For example, the phenomenon of light diffraction generated in a light developing system has hindered the development of semiconductor integrated circuits of smaller generations of the next generation. In order to reduce the effects of the diffraction phenomenon, commonly employed techniques include optical proximity correction, a phase shift mask, and an immersion optical lithography system. An electron beam development system is another option to reduce the scale of future semiconductor integrated circuits. However, using an electron beam development system for manufacturing integrated electricity The production of the road is a challenge.

There is therefore a need for a method to increase the throughput of an electron beam development system.

The present invention provides many different embodiments in light of the disadvantages of the prior art.

A method of forming a pattern by an electron beam lithography system is described in the current disclosure. The method includes: receiving an integrated circuit (IC) design layout data, including a plurality of pattern layers having a polygon and a forbidden pattern; decomposing the polygon to the plurality of sub-domains by using an electronic proximity correction technique (EPC); converting the decomposed polygon To an electron beam writing format data; and writing the electron beam writing format data to a substrate by an electron beam writer. The step of decomposing the polygon includes: finding a modified forbidden graphic as a reference layer, and decomposing the modified polygon by avoiding decomposing the forbidden graphic. The step of modifying the polygon and the inhibiting pattern using the electronic proximity correction technique includes adding or subtracting an offset to the polygon and the inhibiting pattern in a horizontal direction, a vertical direction, or the horizontal direction and the vertical direction. The offset includes a range from 0 nm to 1000 nm. The step of decomposing the modified polygon includes forming an OR layer from the modified polygon and the modified prohibited pattern, and decomposing the modified polygon by avoiding dissolving the prohibited pattern of the OR layer. The step of decomposing the modified polygon includes forming a NOT layer from the modified polygon and the modified forbidden pattern, and decomposing the modified polygon by avoiding dissolving the forbidden pattern of the NOT layer. The step of decomposing the modified polygon includes observing the forbidden graphic setting along a boundary line An exploded line is moved and moved away from the strip boundary line if the strip boundary line spans the modified forbidden pattern. The step of decomposing the modified polygon includes decomposing the modified polygon along a spaced apart boundary line and moving along a boundary line away from the strip, if an exploded point falls within the modified forbidden pattern. The step of avoiding dissolving the forbidden pattern includes setting an exploded line from 0 nm to 200 nm away from the prohibited pattern. The method further includes combining the decomposed polygon to the original polygon, if the polygon is decomposed to be less than 200 nm.

The current disclosure further describes a method of forming a pattern by an electron beam lithography system. The method includes: receiving an integrated circuit (IC) design layout data, including a plurality of pattern layers having a polygon and a forbidden pattern; decomposing the polygon to the plurality of sub-domains by using an electronic proximity correction technique (EPC); converting the decomposed polygon To an electron beam writing format data; and writing the electron beam writing format data to a substrate by an electron beam writer. Decomposing the polygon includes: finding a forbidden pattern as a reference layer; forming an OR layer or a NOT layer with the reference layer; and decomposing the modified polygon by avoiding dissolving the OR layer or the forbidden pattern of the NOT layer . The step of avoiding dissolving the forbidden pattern of the reference layer includes moving an exploded line away from the forbidden pattern from 0 nm to 200 nm. The method further includes combining the decomposed polygon to the original polygon, if the polygon is decomposed to be less than 200 nm.

The current disclosure further describes a method of forming a pattern by an electron beam lithography system. The method includes: receiving an integrated circuit (IC) design layout data, including a plurality of pattern layers having a polygon and a forbidden pattern; decomposing the polygon to the plurality of sub-domains by using an electronic proximity correction technique (EPC); converting the decomposed polygon To an electron beam write format data; and write by an electron beam The electron beam writing format data is written into a substrate. The step of decomposing the polygon includes: finding a forbidden pattern as a reference layer; and decomposing the modified polygon by avoiding dissolving the forbidden pattern of the reference layer, wherein the step of avoiding dissolving the forbidden pattern of the reference layer moves and decomposes The line is far from a boundary line. The method further includes setting an exploded line by observing the prohibited pattern along a boundary line. The decomposition line overlaps the boundary line of the strip, if the strip boundary line does not touch the prohibition pattern, or moves the decomposition line away from the strip boundary line from 0 nm to 200 nm, if the strip boundary line touches the strip line Graphic is forbidden. The method further includes decomposing the modified polygon along the strip boundary line and moving a decomposition point away from the strip boundary line from 0 nm to 200 nm, if the decomposition point falls on the reference layer and the modified prohibited pattern . The method also includes combining the decomposed polygon to the original polygon, if the polygon has been decomposed to be less than 200 nm.

100‧‧‧Electron beam writing system

102‧‧‧Electronic particle source

104‧‧‧electron optical column

106‧‧‧Electron beam

108‧‧‧ cavity

110‧‧‧ pump unit

112‧‧‧ stage

114‧‧‧Substrate

116‧‧‧Resist film

200‧‧‧ method

Steps 202, 204, 206, 208, 210‧‧

300‧‧‧ device

302‧‧‧Fields

304‧‧‧ strips

400‧‧‧Resist pattern error

402‧‧‧ pattern

404‧‧‧ with border line

406‧‧‧ pattern

500‧‧‧ device

502a, 502b‧‧‧ polygon

504a, 504b, 504c‧‧‧ prohibited graphics

506‧‧‧ with boundary line

508‧‧‧ with buffered boundary line

510‧‧‧Decomposition line

600‧‧‧ method

602, 604, 606, 608, 610, 612, 614, 616‧ ‧ steps

650‧‧‧ device

652‧‧‧Poly

654, 656, 658‧ ‧ ban graphics

670‧‧‧OR layer

652a, 652b‧‧‧ offset polygon

654a, 656a, 658a‧‧ ban graphics

662‧‧‧Poly

662a‧‧‧ Decomposed polygon

672a, 672b, 672c‧‧‧ decomposition points

700‧‧‧ method

702, 704, 706, 708, 710, 712, 714, 716 ‧ ‧ steps

750‧‧‧ device

652b‧‧‧ polygon

654b, 656b, 658b‧‧‧NOT pattern

752a, 752b, 752c‧‧‧ decomposition points

800‧‧‧ method

802, 804, 806, 808, 810, 812‧‧ steps

850‧‧‧ device

852a, 852b, 852c‧‧‧ polygon

854a-i‧‧‧ prohibited graphics

900‧‧‧ method

902, 904, 906, 909, 910, 912 ‧ ‧ steps

1 is a schematic diagram of an electron beam lithography system in accordance with one or more embodiments of the present invention.

Fig. 2 is a flow chart showing the flow of design data of an integrated circuit (IC) in an electron beam writing system according to one or more embodiments of the present invention.

Figure 3 is a diagram showing the field in which a device is decomposed in one or more embodiments of the present invention.

Fig. 4 is a view showing an example of a boundary error of boundaries between two fields in an electron beam writing system of one or more embodiments of the present invention.

Figure 5 shows an exemplary decomposition of a device in one or more embodiments of the present invention.

Figure 6 shows a polygon decomposing a device in one or more embodiments of the present invention. Flow chart.

Figure 7 shows an illustration of a polygon that decomposes a device in one or more embodiments of the present invention.

Figure 8 shows an illustration of a polygon that decomposes a device in one or more embodiments of the present invention.

Figure 9 shows an illustration of a polygon incorporating a device in one or more embodiments of the present invention.

Figure 10 is a flow chart showing the decomposition of a polygon of a device in one or more embodiments of the present invention.

Figure 11 shows an illustration of a polygon that decomposes a device in one or more embodiments of the present invention.

Figure 12 is a flow chart showing the decomposition of a polygon of a device in one or more embodiments of the present invention.

Figure 13 shows an illustration of a polygon that decomposes a device in one or more embodiments of the present invention.

Figure 14 is a flow chart showing the decomposition of a polygon of a device in one or more embodiments of the present invention.

The making and using of the preferred embodiments of the invention are described in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in the broad variations of the specific context. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention.

Referring to FIG. 1, an electron beam writing system 100 is the present invention. An exemplary system that can be employed in various embodiments of the present invention. In some embodiments of the present invention, the electron beam writing system 100 includes an electronic particle source 102, an electron optical column 104, an electron beam 106, a cavity 108, a pump unit 110, a stage 112, and a substrate 114. And a resist film 116 formed on the substrate 114, but can be adjusted to other configurations and increase or decrease the number of components. In this embodiment, the electron beam writing system is also referred to as an electron beam writer or e-beam writer. By heating the conductive material to a very high temperature, the electron particle source 102 provides a plurality of electrons emitted by the conductive material, wherein the electrons have sufficient energy to resist the work function barrier and release from the conductive material, or The electrons are blocked by the work function by applying a relatively large electric field (field emission source). The electron optical column 104 includes a plurality of electromagnetic holes, an electrostatic lens, an electromagnetic lens, a shaping deflector, and a cell selection deflector. The electron optical column 104 provides an electron beam 106 to the system, such as a plurality of Gaussian spot electron beams, a plurality of electron beams of a variable shape, and a plurality of unit projection electron beams. The cavity 108 includes a wafer carrier and an unloading unit, and the cavity 108 provides a wafer transport mechanism for loading the wafer to the system and unloading the system without interrupting the operation of the electron beam writing system 100. The pump unit 110 includes a plurality of pumps and filters, and the pump unit 110 provides an electron beam writing system 100 in a high vacuum environment. The stage 112 includes a plurality of motors, roller guides, and countertops. The substrate 114 is fixed to the stage 112 by vacuum suction. When the substrate 114 of the electron beam writing system 100 performs the homogenization, focusing, and exposure operations, the stage 112 provides the substrate 114 with accurate accuracy in the X, Y, and Z directions. Positioning and moving.

The substrate 114 on which the resist film 116 is deposited is mounted on the stage 112 The electron beam 106 is exposed. In the present embodiment, the resist is also referred to as a photoresist, an electron beam resist, a resist film, and a photoresist film. The substrate 114 includes a wafer substrate or a blank mask substrate. The wafer substrate includes a germanium wafer. Alternatively (or additionally), the wafer may include: additional semiconductor elements such as germanium; semiconductor compounds including: tantalum carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or Indium antimonide; semiconductor alloys, including: antimony telluride, gallium arsenide, indium aluminum arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide and/or indium gallium phosphide. In another embodiment, the wafer is an insulator semiconductor (SOI). A plurality of conductive or non-conductive films are deposited on the wafer. For example, the conductive film includes a metal such as aluminum, copper, tungsten, nickel, titanium, gold, platinum, and alloys thereof. The insulating film includes tantalum oxide and tantalum nitride. The blank mask substrate comprises a material having a low coefficient of thermal expansion such as quartz, tantalum, niobium carbide or niobium oxide titanium oxide.

Referring to FIG. 2, a method 200 in accordance with various embodiments of the present invention includes using an electron beam writing system to expose a resist film deposited on a substrate. First, the method 200 begins at step 202 and receives design circuit data from the designer (hereinafter referred to as IC). The designer can create a separate part of the IC product for a separate design unit or for designing layout data from the IC in a semiconductor manufacturing facility. In the current disclosure, the IC design layout data is also referred to as an IC design layout pattern or an IC design layout. The IC design layout includes various IC features (also known as main features), such as active regions, isolation regions, gate electrodes, source or drain electrodes, openings connected by metal lines or intermediate layers, and for bonding multiple pads. An opening of (pad) is formed in the substrate. The IC design layout pattern includes a plurality of pattern layers. A typical IC design layout data is presented by the GDS file format. In the current disclosure, The sign is also called a polygon. The method 200 continues with step 204 to perform an electron proximity correction (EPC). The proximity effect in the electron beam lithography system 100 produces a non-uniform distribution that increases to the actual received exposure in a pattern region due to the uniform exposure provided by the incident beam. The unevenness of the electron beam is caused by an electron beam dispersed from the substrate. Due to the electron beam dispersed from the substrate, the electron proximity correction is a compensation process for a critical dimension. The electronic proximity correction process includes dimensional deviation correction, shape correction, dose correction, and background dose equalization (GHOST) correction. After performing the electronic proximity correction of step 204, the method 200 continues to the decomposition process of step 206. In the decomposition process of step 206, the electronic proximity correction correction design layout data is divided into a plurality of stripes or a plurality of subfields. The subdomain can be further divided into a plurality of subfields. In the current disclosure, to simplify the content, the sub-domain can also be referred to as a plurality of sub-sub-domains. Step 206 also includes assigning an electron beam to each strip or subfield. After the decomposition process of step 206, the method 200 continues to step 208 to perform an electron beam data process. Step 208 includes checking the strip IC design layout data error, and converting the strip IC design layout data into an electron beam writing format data. Step 208 also includes minimizing differences between electron beams assigned to the strip or subfield, such as electron beam dose correction, electron beam offset correction, electron beam scale correction, and electron beam rotation correction. After step 208, the method 200 continues to step 210 by writing an IC design layout pattern to the substrate by the electron beam lithography system 100. In the present disclosure, writing a pattern to a substrate is also referred to as exposing the substrate or scanning the substrate with a patterned electron beam. The remaining steps may be provided before, during, or after the method 200, and some of the steps may be replaced, deleted, or moved as the remaining embodiments of the method 200.

As with the electron beam lithography system 100 shown in Figure 1, the electron beam 106 can be biased by approximately 2 um. In order to write a field or substrate, a plurality of electron beams are employed and the stage 112 of the electron beam lithography system 100 is moved during the writing of the pattern onto the substrate. In the current embodiment, stage 112 is moved in the y-direction and electron beam 106 is simultaneously offset in the x-direction. Each electron beam 106 covers a strip or a subfield. For example, in one embodiment, 13,000 electron beams are used to write an IC circuit having a field of 26 x 33 mm size.

Please refer to FIG. 3, which shows an exemplary decomposition of the apparatus 300 in accordance with one or more embodiments of the present invention. Apparatus 300 includes a field of field 302 and a plurality of strips 304. However, the device may be configured for the rest. In the current embodiment, field 302 includes an arrangement of reticle or an IC circuit field on the wafer substrate. As shown in FIG. 3, field 302 is divided into a plurality of strips 304 or subfields. Each strip 304 is assigned a patterned electron beam. Field 302 is then scanned by a plurality of patterned electron beams. The substrate strip is scanned by a plurality of patterned electron beams within the electron beam lithography system 100, and the IC design layout pattern is written directly on the resist film deposited on the substrate. Scanning continues until all substrates are patterned. Since some patterns extend across strip boundaries or subdomain boundaries, a butting error may occur at the subdomain boundaries.

Referring to Figure 4, there is shown an illustration of an anti-pattern error 400 at the strip boundary or at the sub-domain boundary in accordance with one or more embodiments of the present invention. Pattern 402 is an intended pattern. Pattern 402 spans two strips. A strip line 404 separates the two strips. Pattern 402 is formed by electron beams scanned in two adjacent subfields. Pattern 406 is the actual final pattern of the two electron beam scans. As shown in Figure 4, it should be noted that the pattern 406 includes a critical dimension (CD) and a overlay. Cover the problem.

Please refer to FIG. 5, which shows an exemplary decomposition of a device 500 in accordance with one or more embodiments of the present invention. Apparatus 500 includes a plurality of polygons 502a-b and inhibiting graphics 504a-c. However, the rest of the configuration can be increased or decreased. In the present disclosure, the decomposition of a device is also referred to as a striping device. In the current embodiment, the polygons 502a-b include a metal line, and the inhibiting patterns 504a-c include an opening or a joint that is coupled to the conversion layer metal line. In an embodiment, the inhibit graphics 504a-c are formed prior to the polygons 502a-b, or the graphics 504a-c are prohibited from forming after the polygons 502a-b. In another embodiment, the inhibit graphics 504a-c are formed in the same layer as the polygons 502a-b. As shown in FIG. 5, polygon 502a and polygon 502b span strip boundary line 506. Strip buffer boundary lines 508 are located on either side of the strip boundary line 506, respectively. The strip boundary line 506 is spaced from the strip buffer boundary line 508 by about 10% of the strip width, for example about 0.2 um. The strip buffer zone is then approximately 0.4 um. As shown in Fig. 5, if the device 500 is decomposed along the strip boundary line 506, the inhibit pattern 504b will be split into two different strips. The split prohibition graphic 504b will produce a critical dimension as well as coverage issues, as shown in FIG. Thus, the decomposition line 510 is moved away from the prohibition pattern 504c to avoid the decomposition prohibition pattern 504c (in one example, the decomposition line 510 is spaced from the strip boundary line by 0-200 nm). In the current disclosure, the width of the strip and the width of the associated buffer strip are not fixed, and the IC design layout data and processing optimization are changed. In one example, the strip has a width of about 2 um and the width of the buffer strip is about 10% of the strip width.

Please refer to FIG. 6. FIG. 6 shows a method 600 of decomposing a polygon of the device 650 according to one or more embodiments of the present invention. As shown in Figure 7 Apparatus 650 includes a polygon 652 and a plurality of inhibit patterns 654, 656, 658 of a reference layer. However, the rest of the configuration can be increased or decreased. The method 600 begins at step 602 by looking for a polygon 652 of the device 650 as shown in FIG. 7 and a plurality of forbidden graphics 654, 656, 658 of the reference layer. The method 600 continues with step 604 to add or subtract an offset at polygon 652 or forbidden graphics 654, 656, 658. In the current embodiment, the offset is approximately between 0 and 1000 nm. The offset can be in the x (horizontal) or y (vertical) direction, or in the x and y directions. Step 604 can be performed in an electronic proximity correction process as in step 204 of method 200. The method 600 continues with step 606 by forming an OR layer 670 as shown in FIG. 8 by adding the offset polygon 652a and the offset inhibit patterns 654a, 656a, 658a. The method 600 continues to step 608 where the decomposition point is set on the OR layer 670. In a present embodiment, the decomposition point can be set at decomposition point 672a, decomposition point 672b, or decomposition point 672c, as shown in Fig. 8, as long as decomposition points 672a-c are not set on forbidden patterns 654a, 656a, 658a. In one embodiment, the decomposition points 672a-c are set at 0-200 nm away from the strip boundary line. The method 600 continues to step 610 where the offset polygon 652a is resolved at the decomposition point 672a, the decomposition point 672b, or the decomposition point 672c.

As shown in Figure 9, the offset polygon 662 of device 650 does not overlap any of the inhibit graphics. However, one end of the polygon 662 is near the strip boundary line 506. For example, polygon 662 is decomposed at strip boundary line 506 and produces a small, split polygon 662a. The boundary error as shown in Fig. 4 will result from the small decomposed polygon 662a. The method 600 then proceeds to step 612 to calculate the size of the exploded polygon 662a. If the size X of the decomposed polygon 662a is less than or equal to 200 nm, the method continues to step 614 where the decomposed polygon 662a is merged to form the original polygon 662. Decomposed multilateral The dimension X of the shape 662a is greater than 200 nm, and the method continues to step 616 to complete the decomposition of the polygon 662. The remaining steps may be provided before, during, or after method 600, and some of the steps described may be replaced, deleted, or moved as the remaining embodiments of method 600.

Referring to FIG. 10, a diagram of a method 700 for decomposing a polygon of a device 650 in accordance with one or more embodiments of the present invention is shown. The method 700 begins at step 702 by looking for the polygon 652 of the device 650 as shown in FIG. 7 and the plurality of forbidden graphics 654, 656, 658 of the reference layer. The method 700 continues with step 704 by adding or subtracting an offset to the polygon 652 of the device 650 to form the offset polygon 652b. Step 704 also includes forming NOT patterns 654b, 656b, 658b by reducing the offset of the inhibit patterns 654, 656, 658 from the reference layer of device 650. In the current embodiment, the offset is approximately between 0 and 1000 nm. The offset can be in the x (horizontal) or y (vertical) direction, or in the x and y directions. The method 700 continues with step 706 by forming an OR layer 750 by the offset polygon 652b and the NOT patterns 654b, 656b, 658b as shown in FIG. The OR layer 750 includes an offset polygon 652b and NOT patterns 654b, 656b, 658b. The method 700 continues with step 708 where the decomposition points 752a-c are set on the OR layer 750. In the current embodiment, the decomposition point can be set at the decomposition point 752a, the decomposition point 752b, or the decomposition point 752c, as shown in Fig. 11, as long as the decomposition points 752a-c are not set on the NOT pattern 654b, 656b or 658b. The decomposition points 752a-c are set at 0-200 nm away from the strip boundary line. The method 700 continues to step 710 by decomposing the offset polygon 652b. After step 710, method 700 proceeds to step 712 where the size of the exploded polygon 662a is calculated, as shown in FIG. If the size X of the decomposed polygon 662a is less than or equal to 200 nm, the method 700 continues to step 714 where the decomposed polygon 662a is merged to form The original polygon 662. If the size X of the decomposed polygon 662a is greater than 200 nm, the method continues to step 716 to complete the decomposition of the polygon 662. The remaining steps may be provided before, during, or after method 700, and some of the steps described may be replaced, deleted, or moved as the remaining embodiments of method 700.

Referring to FIG. 12, a diagram of a method 800 for decomposing a polygon of a device 850 in accordance with one or more embodiments of the present invention is shown. Apparatus 850, as shown in Figure 13, includes a plurality of polygons 852a-c from the reference layer and a plurality of inhibit patterns 854a-i from the reference layer. However, the device may also have the possibility of remaining configurations. The method 800 begins at step 802 by looking for polygons 852a-c as shown in FIG. 13 and forbidden graphics 854a-i of the reference layer. The method 800 continues with step 804 to form an exploded line 860 to resolve the polygons 852a, 852b, and 852c. Step 804 includes forming an exploded line 860 along the strip boundary line 506. If the strip boundary line 506 does not span the inhibit pattern, the exploded line 860 overlaps the strip boundary line 506. However, if the strip boundary line 506 spans the inhibit pattern, the exploded line 860 is away from the strip boundary line 506 to avoid decomposition of the inhibit pattern. For example, the strip boundary line 506 spans the inhibit pattern 854b, which is away from the strip boundary line 506, such as a distance from 0 nm to about 200 nm, to avoid disassembling the inhibit pattern 854a as shown in FIG. In an example, when the inhibit pattern 854b as shown in FIG. 12 is decomposed, the strip boundary line 506 does not span the prohibition pattern, and the decomposition line 860 overlaps the strip boundary line 506. In another example, the strip boundary line 506 spans the inhibit pattern 854i, and the exploded line 860 is away from the strip boundary line 506 to avoid disassembling the inhibit pattern 854i as shown in FIG.

As shown in FIG. 12, after step 804, method 800 continues to step 806 by decomposing polygons 852a-c by decomposition line 860 as shown in FIG. The method 800 continues to step 808 where the calculated decomposition is as disassembled as shown in FIG. The size of the edge. If the size X of the exploded polygon 662a is less than or equal to 200 nm, the method 800 proceeds to step 810 where the resolved polygon 662a is merged to form the original polygon 662. If the size X of the decomposed polygon 662a is greater than 200 nm, the method continues to step 812 where the decomposition polygon 662 is completed. The remaining steps may be provided before, during, or after method 800, and some of the steps described may be replaced, deleted, or moved as the remaining embodiments of method 800.

Referring to Figure 14, there is shown a method 900 of decomposing a polygon of apparatus 850 in accordance with one or more embodiments of the present invention. The method 900 begins at step 902 by looking for polygons 852a-c as shown in FIG. 13 and forbidden graphics 854a-i of the reference layer. Step 902 also includes adjusting the polygons 852a-c and the forbidden graphics 854a-i of the reference layer by adding an offset. The offset can be increased in the x direction, the y direction, or the remaining directions. The offset is approximately between 0 nm and 1000 nm. The method 900 continues to method 904 by decomposing the polygon along a strip boundary line 506 as shown in FIG. At the same time, method 900 continues to step 906 to check if the resolution point falls within the forbidden pattern of the reference layer. If the decomposition point falls on the forbidden pattern of the reference layer, the method continues to step 908 where the remaining decomposition points are sought along the strip boundary line 506 and proceeds to step 904 to decompose the polygon. The distance of the decomposition point away from the strip boundary line 506 is approximately between 0 and 200 nm. If the decomposition point does not fall within the forbidden pattern of the reference layer, the method continues to step 910 where the decomposed polygon as shown in Fig. 9 is calculated. If the size X of the decomposed polygon 662a is less than or approximately equal to 200 nm, the method 900 continues to step 912 where the decomposed polygon 662a is merged to form the original polygon 662. If the size X of the decomposed polygon 662a is greater than 200 nm (this value varies with the width of the buffer strip), the method 900 continues to step 914 where the decomposition of the polygon 662 is completed. The remaining steps may be provided before, during, or after method 900, and some The steps described may be replaced, deleted, or moved as the remaining embodiments of method 900.

The foregoing describes various embodiments for decomposing an IC circuit field to expose a resist film deposited on a substrate. Different embodiments may have different advantages, and none of the specific advantages are necessary for any one embodiment.

Although the present invention has been disclosed in its preferred embodiments, it is not intended to limit the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

200‧‧‧ method

Steps 202, 204, 206, 208, 210‧‧

Claims (9)

A method of patterning a substrate, the method comprising: receiving an integrated circuit design layout data, including a plurality of pattern layers having a polygon and a forbidden pattern; modifying the polygon and the forbidden pattern by using an electronic proximity correction technique; and decomposing Modifying the polygon to a plurality of sub-domains, wherein the step of decomposing the modified polygon comprises: using the modified forbidden pattern as a reference layer; setting an exploded line by observing the forbidden pattern along a strip boundary line; The decomposition line is away from the strip boundary line if the strip boundary line spans the modified prohibition pattern; the modified polygon is decomposed by avoiding decomposing the prohibition pattern; and the decomposed polygon is converted to an electron beam writing format Data; and writing the electron beam writing format data to a substrate by an electron beam writer. The method of claim 1, wherein the step of modifying the polygon and the inhibiting pattern by using an electronic proximity correction technique comprises: in a horizontal direction, a vertical direction, or the horizontal direction and the vertical direction, The polygon and the forbidden pattern add or subtract an offset between 0 nm and 1000 nm. The method of claim 1, wherein the step of decomposing the modified polygon comprises forming an OR layer from the modified polygon and the modified prohibited pattern, and further comprising decomposing the modified polygon. Take And avoiding dissolving the forbidden pattern of the OR layer. The method of claim 1, wherein the step of decomposing the modified polygon comprises forming a NOT layer from the modified polygon and the modified prohibited pattern, and further comprising decomposing the modified polygon. And avoiding disabling the prohibited graphics of the NOT layer. A method of patterning a substrate, the method comprising: receiving an integrated circuit design layout data, including a plurality of pattern layers having a polygon and a forbidden pattern; modifying the polygon and the forbidden pattern by using an electronic proximity correction technique; and decomposing Modifying the polygon to a plurality of sub-domains, wherein the step of decomposing the modified polygon comprises: finding a forbidden pattern as a reference layer; forming an OR layer or a NOT layer with the reference layer; by avoiding decomposing the OR layer or The prohibited layer of the NOT layer, decomposing the modified polygon; converting the decomposed polygon to an electron beam writing format data; and writing the electron beam writing format data by an electron beam writer Substrate. The method of claim 5, wherein the step of avoiding dissolving the forbidden pattern of the reference layer comprises moving an exploded line away from the forbidden pattern from 0 nm to 200 nm. A method of patterning a substrate, the method comprising: receiving an integrated circuit design layout data, including having a polygon and a Blocking a plurality of pattern layers of the graphic; modifying the polygon and the forbidden pattern by using an electronic proximity correction technique; and decomposing the modified polygon to the plurality of subfields, wherein the step of decomposing the modified polygon comprises: searching for a forbidden graphic as a a reference layer; decomposing the modified polygon by avoiding dissolving the forbidden pattern of the reference layer, wherein the step of avoiding dissolving the forbidden pattern of the reference layer moves an decomposition line away from a strip boundary line; converting the decomposed polygon To an electron beam writing format data; and writing the electron beam writing format data to a substrate by an electron beam writer. The method of claim 7, further comprising: setting an decomposition line by observing the prohibition pattern along a boundary line, wherein the decomposition line overlaps the boundary line of the strip, if the strip boundary line does not touch Touch the inhibit pattern, or move the decomposition line away from the strip boundary line from 0 nm to 200 nm, if the strip boundary line touches the prohibition pattern. The method of claim 7, further comprising decomposing the modified polygon along the strip boundary line and moving a decomposition point away from the strip boundary line from 0 nm to 200 nm, if the decomposition point falls on the reference The prohibited graphic of the layer has been modified.