TWI506960B - Method,apparatus and system for changing a frequency of a clock signal - Google Patents

Description

Method, device and system for changing a frequency of a clock signal

The present invention relates to the field of electronic devices and, more particularly, to dynamic changes in the frequency of the clock signal.

In modern electronic devices and systems, many signals are transmitted between various functional units and to external devices/systems. Various signals may include data signals, clock signals, radio signals, and the like. The frequency of such signals can vary with respect to each other.

During operation of the device, the frequency of the various signals can be intentionally changed from time to time during operation. For example, the frequency of the timing pulse signal can be reduced to minimize power consumption, or alternatively the frequency can be increased to improve performance. In another example, many wireless communication devices may use a technique known as Frequency Hopping Spread Spectrum (FHSS), in which the frequency of the radio carrier signal is periodically changed. Periodically changing the frequency of the radio carrier signal can be randomized and thus reduce interference from external sources.

Because the electronic systems and devices mentioned above are configured for signal transmission and reception at several different (and varying) frequencies, the circuitry can be implemented to manage the frequency of at least some of the signals.

Various methods and apparatus for dynamically changing one of the frequencies of a clock signal are disclosed. This frequency of the clock signal can be varied to reduce or prevent interference with the frequency of other signals transmitted in an electronic system. The frequency of the clock signal can be selected such that the fundamental frequency of the clock signal and its harmonics do not One of the other signals transmitted in the system is of the same frequency, thereby reducing or eliminating the chance that the clock signal will interfere with the other signals.

An electronic system having a first interface and a second interface is contemplated. The information transmitted on the first interface can be synchronized with a corresponding clock signal. At the second interface, the signals of the plurality of frequencies transmitted thereon may include signals having a particular frequency. The frequency of the signals transmitted on the second interface can be changed periodically and intentionally. In response to changing the frequencies of the signals transmitted on the second interface, the frequency of the clock signal for the first interface can be changed to another frequency that can avoid interfering with signals on the second interface.

In one embodiment, an electronic system includes at least one serial interface and a wireless communication interface. The data transmitted on the serial interface can be synchronized with a clock signal having a first frequency. Information can be transmitted on the second interface based on a carrier signal. The frequency of the carrier signal can be varied periodically (e.g., according to a pseudo-random sequence used in spread spectrum communication). In one embodiment, the frequency of the clock signal may change from the first frequency to the second frequency in response to the change (pending or completed) of the frequency of the carrier signal. In another embodiment, a list of ones of safe and non-secure clock frequencies may be generated based on information of pending frequency changes in the wireless communication interface. The second frequency can be selected such that neither the second frequency nor its associated harmonics coincide with the new frequency of the carrier signal.

The frequency of changing the clock signal can be performed in a manner that avoids the false activity on the signal path of the time-lapse signal transmitted above. In one embodiment, the clock signal output by the clock generation circuit (eg, phase locked loop or PLL) may be suppressed during a change in frequency. In another embodiment, it can be in frequency The PLL is turned off during the change. In some embodiments, the normal clock signal can be replaced with an alternate clock signal during the change. Such embodiments may utilize a glitch-free multiplexer to select a normal clock signal (during normal operation) or an alternate clock signal (during a frequency change of the normal clock signal). The change in the frequency of the clock signal can be initiated by the clock control unit. The clock control unit may initiate the change in response to: receiving, from another unit (eg, a baseband unit in the wireless communication device) information indicating that the carrier signal is to be changed, or indicating which of the potential interferences The clock signal frequency is a change in the list of "non-safe" frequencies.

While the invention is susceptible to various modifications and alternatives, the specific embodiments are illustrated in the drawings and are described in detail herein. It is to be understood, however, that the invention is not intended to All modifications, equivalents, or alternatives within the scope. The headings used herein are for organizational purposes only and are not intended to limit the scope of the description. As used throughout this application, the word "may" is used in the sense of meaning (i.e., meaning possible) rather than mandatory (i.e., meaning necessary). Similarly, the word "comprising" means including but not limited to.

Various units, circuits, or other components may be described as "configured to" perform one or more tasks. In this context, "configured to" is a broad description of the structure, which generally means "having a circuit that performs the one or more tasks during operation." Thus, the unit/circuit/component can be configured to even The task is still executed when the unit/circuit/component is not currently turned on. In general, a circuit forming a structure corresponding to "configured to" may include a hardware circuit. Similarly, various units/circuits/components may be described as performing one or more tasks for ease of description. These descriptions should be interpreted to include the phrase "configured to". A unit/circuit/component that is configured to perform one or more tasks is expressly not intended to invoke the interpretation of the unit/circuit/component of the sixth paragraph of U.S.C. § 112.

Other aspects of the invention will become apparent after reading the <RTIgt;

FIG. 1 illustrates an exemplary device 100 that can implement the embodiments described herein. Device 100 can be any of a variety of devices. For example, device 100 can be a portable or mobile device such as a mobile phone, PDA, audio/video player, and the like. In the embodiments described herein, device 100 can be configured to communicate with other devices (eg, other wireless devices, wireless peripherals, cell towers, access points, etc.) using one or more wireless channels. As used herein, "wireless device" refers to a device that is capable of communicating with other devices or systems using wireless communication. For example, device 100 can be configured to utilize one or more wireless protocols (eg, 802.11x, Bluetooth, WiMax, CDMA, GSM, etc.) to wirelessly communicate with other devices. Device 100 can also be configured to adjust and/or change the input clock signal within device 100 to reduce (or eliminate) interference with communications using the wireless channel.

As also shown in FIG. 1, device 100 can include a display 240 that is operative to display graphics provided by an application executing on device 100. The app can be used for any of a variety of applications, such as Play, Internet browsing applications, email applications, phone applications, productivity apps, and more. The application can be stored in the memory medium of device 100. Device 100 can include a central processing unit (CPU) and a graphics processing unit (GPU) that can collectively execute such applications.

As shown in FIG. 1, device 100 can include a system single-chip (SOC) 200, which can include portions for various purposes, including processor 202, display circuit 204, and pulse circuit 206, which The portions can all be coupled to the serial interface 208 (eg, a high speed serial interface (HSSI), such as the Mobile Industry Processor Interface (MIPI). The HSSI 208 can provide information including the HSSI clock signal to the display 240. For example In other words, display 240 can display graphics based on HSSI clock signals. Other embodiments may use other interfaces such as display interface instead of MIPI interface.

In addition to SOC 200, device 100 can also include various types of memory (eg, including NAND 210), interface interface 220, display 240, and wireless communication circuitry 230 that can perform wireless communication using antenna 235 (eg, for GSM, Bluetooth) , WiFi, etc.). As shown, there may be interference between the signals provided from HSSI 208 to display 240 and the wireless communication using the antenna. For example, an HSSI clock signal (eg, a harmonic of an HSSI clock signal) can interfere with the use of one or more wireless communication channels by the radio 230. Therefore, as described below, this interference can be mitigated or reduced by adjusting the HSSI clock signal.

In one embodiment, communication circuit 230 can operate in accordance with the principles of frequency hopping spread spectrum (FHSS). In FHSS systems, the frequency of the RF (radio frequency) carrier signal is periodically changed to randomize interference from other sources. Frequency The change can occur based on a pseudo-random sequence known to both the transmitter and the receiver. Although the frequency of the RF carrier can be periodically changed to randomize the interference, the close proximity to HSSI 208 (and thus its clock circuit) can still cause some interference with the fundamental frequency of the clock signal and its harmonics. However, the various embodiments discussed herein are expected to dynamically change the clock frequency of the HSSI 208 in response to receiving information regarding changes in the frequency of the RF carrier transmitted between the communication circuit 230 and the antenna 235. Changing the clock frequency of the HSSI 208 to coincide with the frequency change of the RF carrier signal of the communication circuit 230 may reduce or prevent interference from the clock signal and its associated harmonics.

It should be noted that while various embodiments may include components on the SOC 200, other embodiments may implement the components as two or more integrated circuits. In general, the components of SOC 200 can be considered a host of display 240 (e.g., as shown below in Figure 2).

Moreover, although methods are described herein with respect to particular device embodiments, such embodiments are not intended to be limiting. In contrast, the methods described herein are applicable to any device having multiple interfaces in which signals transmitted on one interface can potentially interfere with signals on the other interface and can cause performance degradation.

FIG. 2 illustrates various hardware and software logic that may be used to reduce or remove wireless interference in device 100. In this particular embodiment, the reduction or removal of interference with signals transmitted over the wireless interface can be achieved by varying the frequency of the clock signals transmitted on the other interface. The clock signal frequency can be varied such that its fundamental frequency and its various harmonics do not substantially coincide with the frequency of the signal on the wireless interface (e.g., RF carrier signal).

As shown, the hardware 302 can include a high speed serial interface circuit 208 that can receive a clock signal from the clock generation circuit PLL 304 via the multiplexer 308 (also referred to herein as "first" Clock multiplex, "adjustable clock" or "pll_clk") or receive dsi_clock (also referred to herein as "second clock" or "static clock"), the multiplexer 308 can be a glitch-free waveform Interfere with the multiplexer. In the illustrated embodiment, PLL 304 can be any type of PLL and can generate an output signal (pll_clk signal) based on a PLL reference clock signal received from an external source (eg, an oscillator). The PLL 304 may include components such as a phase detector, a low pass filter, a voltage controlled oscillator (VCO), and a divider ("DIV" in the drawing) implemented in the feedback path. The frequency of the pll_clk signal may depend, at least in part, on the current divisor value of the divider that may be controlled by PLL state machine 310 in this embodiment.

As shown, the output clock of multiplexer 308 can be selected based on the selection of PLL state machine 310, and PLL state machine 310 can also modify the frequency of PLL 304 as needed. PLL state machine 310 can receive vertical sync (VSYNC) notifications and PLL update requests as inputs. PLL state machine 310, PLL 304, and pulse multiplexer 308 may be included in clock circuit 206 shown in FIG.

Core 314 (which may be executed on processor 202) may include a serial interface driver 316 that may provide a PLL update request to PLL state machine 310. In addition, the core may include a baseband driver 318, which may be coupled to the serial interface driver 316 (providing or removing wireless communication interference frequencies also referred to as "victims" or "victim frequencies") and The baseband firmware 312 (in the baseband hardware 311) communicates. In one embodiment, the victim frequency may correspond to an embodiment in which the FHSS is utilized. The frequency of the RF carrier signal transmitted over the wireless interface. The baseband firmware 312 can determine which frequencies will be used during operation using the FHSS. The frequencies may be determined based on a pseudo-random pattern used by the transmitter and receiver (where the baseband hardware 311 may include either or both). The use of a pseudo-random pattern can be synchronized between the transmitter and the receiver such that both the transmitter and the receiver utilize the same RF carrier signal frequency at the same time. Based on the determined frequency change to the RF carrier signal, the baseband firmware 312 can provide an update to the list of victim frequencies to the baseband driver 318. It should be noted that the victim frequency may cover not only the strictly used wireless channel (eg, RF channel), but may also include sufficient margins to avoid harmonics of the serial interface clock.

The clock multiplexer 308 can select dsi_clk when starting up or suspending resume to RAM. The current pulse sets the nominal frequency of the serial interface 208 and the clock frequency of the PLL 304 is close to the nominal frequency. Exemplary frequencies are 256.5 MHz, 342 MHz, and 513 MHz. At this point, the list of victim frequencies maintained by the serial interface driver 316 can be empty, and the list of victim frequencies maintained by the communication center 324 can be cleared to be current. The PLL 304 can be locked to or near the specified frequency of dsi_clk, and then the clock multiplexer 308 can select the PLL output as the clock for the serial interface 208.

When operation continues, in the event that it has been determined that the wireless communication radio will depend on different victim frequencies in the near future, the baseband firmware 312 can transmit an updated list of victim frequencies to the communication center 324 via the baseband driver 318. Communication center 324 can modify the victim update from baseband firmware 312 or pass it to baseband driver 318 as is.

Therefore, the baseband driver can add the victim frequency to the serial interface driver 316 or remove the victim frequency from the serial interface driver 316. The serial interface driver 316 can thus update the list of victim frequencies in its role and then search the list of possible PLL frequencies to find a secure selection (eg, the selection of wireless communication interference to remove or reduce the victim frequency).

The serial interface driver 316 can send a PLL update request to the PLL state machine 310 if the secure selection of the PLL frequency has changed. When the PLL update request is pending in this particular embodiment, the PLL state machine can wait for a VSYNC from under the display subsystem. After receiving the VSYNC signal, PLL state machine 310 can enter an intermediate state by switching clock multiplexer 308 to dsi_clk. While in the intermediate state, PLL state machine 310 can update the PLL settings (eg, divisor) to begin the lockout procedure. After the PLL 304 has locked to the new frequency, the clock multiplexer 308 can change back to the PLL 304, thereby exiting the intermediate state and resume normal operation by the clock signal provided to the HSSI 208 from the PLL 304 (at the new frequency). . While the actual lock time is dependent on the PLL design, it can occur in 100 μs in various embodiments.

In some cases, at least a portion of the conversion of PLL 304 over the next secure PLL frequency can be effectively cut off. In one embodiment, this can be accomplished by the gated PLL reference clock. In some embodiments, it is also possible to fully power down the PLL 304 during at least a portion of the transition. In such embodiments, PLL 304 may maintain the power off for a predetermined time before power is turned back on to lock to the new frequency.

In other cases, PLL 304 may remain active, but the pll_clk signal may be suppressed as a clk signal to HSSI 208 (by multiplexer) 308, other gate control circuits or both). This situation may allow PLL 304 to begin locking to the new frequency without delay when PLL state machine 310 has provided information to select a new frequency.

In general, the gating of pll_clk can be implemented in any suitable manner to prevent false activity on the clk signal path in order to prevent erroneous operation in HSSI 208.

Figure 3 is a timing diagram illustrating changes for an embodiment. As can be seen, PLL state machine 310 can change the old clock frequency to dsi_clock (256.5 in this example) in response to an indication that the old clock frequency of PLL 304 is no longer safe (or expected to be unsafe based on a list of victim frequencies). MHz). Changing the clock frequency to dsi_clock (by changing the selected input of the clock multiplexer 308) may include 3 to 4 missing clock cycles between changes. The dsi_clock signal can be provided as an alternate clock signal for a predetermined period of time during which the PLL 304 can lock to a new frequency deemed safe. In the illustrated example, the VSYNC provided to display 240 may be consistent with the hardware in an intermediate state (eg, when pll_clk is not provided as a clock signal). After the PLL 304 has locked to the new frequency, switching from dsi_clk to PLL 304 may occur by 3 to 4 missing clock signals during the change of the selected input of the clock multiplexer 308. Changing the frequency of the clock signal in this manner can occur in the absence of false activity that causes display 240 to display information in an erroneous manner.

4 is a flow diagram of an embodiment of a method for dynamically changing the frequency of a clock signal in response to a frequency change of a wireless channel/interface. Performing a frequency change on the clock signal to reduce or eliminate the connection to the wireless interface Interference from signals transmitted or transmitted from the wireless interface.

In the illustrated embodiment, method 400 begins by receiving information regarding the frequency to be used by the wireless channel (block 405). In one embodiment, the frequencies may be frequencies of RF carrier signals that undergo periodic changes in accordance with FHSS operation. According to the embodiment of Figure 2, the manifest can be generated by the baseband firmware operating on the baseband unit and forwarded to the baseband driver. Alternatively, other hardware, software, or firmware can be used to generate this list.

The provision of this list may result in updating the list of frequencies that are safe and non-secure for the clock signal operation (block 410). The unsecure frequency may be the frequency at which the clock signaling operation may cause interference with signals transmitted over the wireless channel. In addition, the unsecure frequency can be the frequency at which the fundamental frequency or harmonics of the clock signal can potentially interfere with signals transmitted over the wireless channel. In contrast, the safe frequency can be the frequency of unanticipated interference. In some embodiments, the manifest may be limited to a secure frequency or a non-secure frequency.

In response to an update to the list of safe and/or non-secure clock frequencies, a decision can be made to change the frequency of the clock signal. In particular, this change can be made if one of the upcoming frequencies of wireless operation corresponds to the current operating frequency of the clock signal or to one of its associated harmonics. If a decision is made to change the frequency of the clock signal, the clock control unit can change the selection of the multiplexer from the output of the clock generator (eg, PLL) configured to provide the clock to select the alternate clock signal (block 415). The alternate clock signal can have a fixed frequency and can be used only during a predetermined period between discontinuous operation of the old clock frequency and resume operation of the new clock frequency.

Changing the multiplexer selection from the normal clock signal to the alternate clock signal Thereafter, the clock control unit can initiate a frequency change to the normal clock signal output by the PLL (block 420). In one embodiment, the clock control unit can change the divisor of the divider in the PLL to cause a change in frequency. After the clock control unit has changed the divisor, the PLL can eventually lock to the new frequency (block 425). When the current control unit causes the multiplexer to select the output of the PLL, a resume of operation of the normal clock signal at the new frequency can then occur (block 430). The operation of the clock at the new frequency can continue until the frequency is no longer indicated as a safe frequency.

It should be noted that various methods and apparatus embodiments for dynamically changing the clock frequency in response to changing the frequency of signals transmitted at other interfaces are possible and contemplated. For example, in one embodiment, the clock signal can be changed in response to any pending changes to the RF carrier of the wireless interface. Moreover, the method of handling the clock generation circuit during the conversion can vary from one embodiment to the next. For example, in one embodiment, the output of the PLL can be gated, but the PLL can continue to operate. In another embodiment, the PLL can be briefly turned off to lock to the new frequency before power is turned back on again. Moreover, while some embodiments may provide an alternate clock signal to the serial interface during conversion, other embodiments are possible and contemplated where the clock signal is not provided during the transition, resulting in a brief abort of operation.

Turning next to Figure 5, a block diagram of an embodiment of system 150 is shown. In the illustrated embodiment, system 150 includes at least one instance of IC 5 coupled to external memory 152. The IC 5 in the illustrated embodiment may be an IC that includes such features as the SOC 200 shown in FIG. The IC 5 is also coupled to one or more peripheral devices 154. A power supply 156 is also provided, which The supply voltage is supplied to the IC 5 and one or more supply voltages are supplied to the memory 152 and/or the peripheral device 154. In some embodiments, more than one instance of IC 5 (and may also include more than one external memory 152) may be included.

Peripheral device 154 can include any desired circuitry depending on the type of system 150. For example, in one embodiment, system 150 can be a mobile device (eg, a personal digital assistant (PDA), smart phone, etc.), and peripheral device 154 can include various types of wireless communication (such as wifi) , Bluetooth, cellular, GPS, etc.) devices. Peripheral device 154 may also include additional storage, including RAM storage, solid state storage, or disk storage. Peripheral device 154 may include user interface devices such as a display screen (including a touch display screen or a multi-touch display screen), a keyboard or other input device, a microphone, a speaker, and the like. In other embodiments, system 150 can be any type of computing system (eg, a desktop personal computer, laptop, workbench, desktop top, etc.).

Although the embodiments have been described in considerable detail, the various changes and modifications will become apparent to those skilled in the art. The scope of the following patent application is intended to be construed as covering all such changes and modifications.

5‧‧‧Integrated Circuit (IC)

100‧‧‧ devices

150‧‧‧ system

152‧‧‧External memory

154‧‧‧ peripheral devices

156‧‧‧Power supply

200‧‧‧System Single Chip (SOC)

202‧‧‧ processor

204‧‧‧Display circuit

206‧‧‧ clock circuit

208‧‧‧High Speed Serial Interface (HSSI)/High Speed Serial Interface Circuit

210‧‧‧ "NAND" gate

220‧‧‧Connecting interface

230‧‧‧Wireless communication circuits/radio

235‧‧‧Antenna

240‧‧‧ display

302‧‧‧ Hardware

304‧‧‧ phase-locked loop (PLL)

308‧‧‧clock multiplexer

310‧‧‧ phase-locked loop (PLL) state machine

311‧‧‧Base frequency hardware

312‧‧‧Base frequency firmware

314‧‧‧ core

316‧‧‧Serial interface driver

318‧‧‧Base frequency driver

400‧‧‧Method for dynamically changing the frequency of a clock signal in response to a frequency change of a radio channel/interface

1 is a block diagram of a system including a serial interface and a wireless communication interface.

2 is an exemplary block diagram of the system of FIG. 1 including hardware and software components, in accordance with an embodiment.

FIG. 3 is an exemplary timing diagram in accordance with an embodiment.

Figure 4 is a diagram for dynamically changing based on frequency changes in an interface A flowchart of an embodiment of a method of frequency of a clock signal of another interface.

Figure 5 is a block diagram of an embodiment of an illustrative system.

208‧‧‧High Speed Serial Interface (HSSI)/High Speed Serial Interface Circuit

302‧‧‧ Hardware

304‧‧‧ phase-locked loop (PLL)

308‧‧‧clock multiplexer

310‧‧‧ phase-locked loop (PLL) state machine

311‧‧‧Base frequency hardware

312‧‧‧Base frequency firmware

314‧‧‧ core

316‧‧‧Serial interface driver

318‧‧‧Base frequency driver

Claims (20)

A method for changing a frequency of a clock signal, comprising: providing a first clock signal for a first interface; and responding to the determining signal to be transmitted at a third frequency on a second interface Changing a frequency of the first clock signal from a first frequency to a second frequency; wherein changing the frequency of the first clock signal is included during the transition from the first frequency to the second frequency One of the first clock signals is placed in an intermediate state. The method of claim 1, wherein changing the frequency of the first clock signal comprises: turning off a phase locked loop (PLL) while in the intermediate state, wherein the PLL is configured to generate the first clock signal. The method of claim 1, wherein changing the frequency of the clock signal comprises: suppressing an output of a phase locked loop (PLL) while in the intermediate state, wherein the PLL is configured to generate the first clock signal. The method of claim 3, wherein suppressing the output of the PLL comprises a multiplexer selecting a second clock signal having a fourth frequency to be transmitted on the signal path, and wherein changing to the second frequency comprises The multiplexer selects the output of the PLL after selecting the second clock signal. The method of claim 4, further comprising selecting the second clock signal at the fourth frequency to avoid interference of the second clock signal and its harmonics with the signal transmitted on the second interface. The method of claim 1, further comprising placing the signal path of the first clock signal in the intermediate state for a predetermined period of time. The method of claim 6, further comprising providing an alternate clock signal for the one of the serial interfaces during the predetermined time period. The method of claim 6, further comprising gating the clock signal during the predetermined time period. The method of claim 1, further comprising setting the frequency of the clock signal based on the frequency of the signal transmitted on the radio interface. An apparatus for changing a frequency of a clock signal, comprising: a first interface, wherein the first interface is coupled to receive a first clock signal from a clock generation circuit, wherein the first interface is on the first interface The data transmission is synchronized with the first clock signal; the clock control circuit is coupled to the clock generation circuit, wherein the clock control circuit is configured to respond to the received signal at a third frequency in the first Transmitting an indication of the first clock signal from a first frequency to a second frequency, wherein the clock control circuit is configured to change the first clock signal The first clock signal is suppressed from being supplied to the first interface on a clock signal path at a frequency. The apparatus of claim 10, wherein the clock control circuit is configured to cause a multiplexer to select a signal to be active during a transition period from the first frequency to the second frequency of the first clock signal One of the second clock signals is provided on the path. The apparatus of claim 11, wherein the clock control circuit is configured to cause the multiplexer to select the first clock signal after transitioning the first clock signal to the second frequency. The device of claim 10, wherein the clock control circuit is configured to The first frequency transitions to the second frequency to turn off a phase locked loop (PLL) for a predetermined time, wherein the PLL is configured to generate the first clock signal. The device of claim 10, further comprising a first interface unit associated with the first interface and a second interface unit associated with the second interface, wherein the second interface unit is configured to transmit information Provided to the first interface unit, the information indicates that the first clock signal is operable without causing a frequency of interference with the signals transmitted on the second interface. The device of claim 10, wherein the first interface is a serial interface, wherein information transmitted on the serial interface is synchronized with the first clock signal, and wherein the second interface is configured to be in a A radio interface transmits information on the carrier signal, wherein one of the carrier signals periodically changes in frequency. The apparatus of claim 15, wherein the clock control circuit is configured to select the frequency of the first clock signal based on the frequency of the carrier signal. The apparatus of claim 15, further comprising: a baseband unit configured to determine a frequency below the carrier signal; and a processing unit configured to respond to the baseband unit A request for a frequency below the carrier signal is provided to transmit a request to change the frequency of the first clock signal to the clock control unit. The apparatus of claim 17, wherein the processing unit is configured to maintain a list of frequencies to which the first clock signal can be safely set without causing interference on the radio interface, and wherein the processing unit Enter The one-step configuration updates the list of frequencies in response to the baseband unit providing the indication of the next frequency of the carrier signal. A system for changing a frequency of a clock signal, comprising: a serial display interface, wherein data transmission on the serial display interface is synchronized with a clock signal; a wireless communication interface configured to A wireless communication channel transmits information on a carrier signal, wherein the wireless communication interface is configured to periodically change a frequency of the carrier signal; a clock generation circuit configured to generate the clock signal; A pulse controller configured to cause a change in a frequency of the one of the clock signals in response to a change in the frequency of the carrier signal transmitted by the wireless communication interface. The system of claim 19, wherein the wireless interface is configured to transmit information including an indication of the one or more frequencies to which the frequency of the carrier signal is to be changed, and wherein the system further includes processing circuitry Configuring to maintain a list of frequencies and further configuring to update the list of frequencies in response to the wireless interface providing information indicating a new frequency to which the carrier signal will change, wherein the processing circuit is configured to The request is transmitted to the clock controller to change the frequency of the clock signal in response to receiving information indicating a new frequency to which the carrier signal will change.