TWI506775B - Silicon germanium heterojunction bipolar transistor structure and method - Google Patents

Description

Heterogeneous junction bipolar transistor structure and method

This invention relates generally to semiconductor structures, and more particularly to improved germanium heterojunction bipolar transistor structures and methods of forming such improved transistors.

New communication and test applications require wafers that can operate at higher frequencies. Although high-frequency transistors can use III-V semiconductor materials (such as germanium arsenic (GaAs), tantalum nitride (GaN), etc.), bismuth-based solutions (such as germanium (SiGe) heterojunction bipolar Transistors (HBTs) are less expensive and can accommodate higher order integration than the Group III-V semiconductor materials used today.

However, the size of the components is also a consideration, and limitations in current process technology have limited dimensions in both the vertical and lateral directions of the heterojunction bipolar transistors. Specifically, narrowing the base and collector space-charge regions of the transistor increases the current-gain cut-off frequency (F _t ), but Since the collector overlaps with the extrinsic base, the maximum oscillation frequency (F _max ) is sacrificed. Therefore, it is preferable to use a selective ion-implanted collector (SIC) pad in accordance with the size of the component (for example, U.S. Patent 6,846,710, issued January 25, 2005 by Yi et al. The description, which is incorporated herein by reference, makes the collector region closer to the base region to enhance the current gain cutoff frequency. However, current process technologies do not allow the SIC pads to be sufficiently narrow to have minimal overlap with the outer base. Furthermore, because the formation process of conventional techniques (ie, ion implantation) will create voids (eg, damage, defects, etc.) at the base-collector interface of the heterojunction bipolar transistor, such that the implant is doped Miscellaneous things have undesired diffusion phenomena.

In view of the above, disclosed herein is an improved germanium heterojunction bipolar transistor having a narrow and substantially void-free SIC pad with minimal overlap with the outer mass, and one of the improved semiconductor structures described above. Design structure. Also disclosed herein is a method of forming a transistor that uses a laser to temper the SIC pad relative to a rapid thermal tempering process to produce a narrow SIC pad and a substantially void-free collector. Therefore, the germanium heterojunction bipolar transistor obtained by the present invention can have a narrow space charge region of the base and the collector compared to the prior art.

More specifically, disclosed herein is an embodiment of an improved multilayer semiconductor structure. The structure includes a first semiconductor layer, and a second semiconductor layer is located below the first semiconductor layer. Specifically, the top surface of the second semiconductor layer is adjacent to the bottom surface of the first semiconductor layer. The first semiconductor layer is doped with a first dopant (eg, a p-type dopant such as boron), and the first dopant has a peak concentration in the first semiconductor layer of about .03 microns above the bottom surface thereof ( That is, above the interface) can be greater than about 1 x 10 ¹⁹ cm ^-3 . The second semiconductor layer includes a diffusion region on the top surface and an implant region below the diffusion region. This implanted region can be doped with a second dopant of uniform concentration (eg, an n-type dopant such as phosphorus, antimony or arsenic). For example, the implanted region can have a uniform second dopant concentration greater than about 1 x 10 ¹⁸ cm ^-3 .

Thus, the diffusion region can include a portion of the first dopant diffused from the first semiconductor layer above it, and a portion of the second dopant diffused from the implant region below it. However, during this formation, a laser tempering process can be performed to activate dopants in the implanted region and remove the second semiconductor resulting from the ion implantation process that forms the implanted region. Defects (ie, voids) in the top surface of the layer. Replacing the rapid thermal tempering process with a laser tempering process will minimize the diffusion of the second dopant from the implanted region. Furthermore, since the top surface of the second semiconductor is almost free of defects, the phenomenon that the first dopant from the first semiconductor layer diffuses to the second semiconductor layer is minimized.

Therefore, since there is no gap in the interface, the diffusion region of the second semiconductor layer, especially the second semiconductor layer, may include a first dopant concentration profile having a first dopant concentration located below the interface. , which is less than 100 times smaller than the peak concentration of the first dopant in the first semiconductor layer located above the interface (ie, the peak concentration of the first dopant above the interface is at least 100 times greater than the interface) The concentration of the first dopant below). For example, if the peak concentration of the first dopant in the first semiconductor layer is greater than about 1 x 10 ¹⁹ cm ^-3 at about .03 microns above its interface, there is no void in the interface, so below the interface The first dopant concentration can be less than about 1 x 10 ¹⁷ cm ^-3 and is significantly reduced toward the implanted area.

Furthermore, since the diffusion of the second dopant from the implanted region is minimized, the second semiconductor layer may further comprise a second dopant concentration profile, wherein the concentration of the second dopant is in the implanted region The middle system is generally uniform, but the entire diffusion area is significantly reduced toward the interface. For example, the concentration of the second dopant in the implanted region can be greater than about ten times the concentration of the second dopant on the top surface of the second semiconductor layer (ie, just below the interface). For example, the concentration of the second dopant in the implanted region may be uniform and may be greater than about 1×10 ¹⁸ cm ⁻³ ; however, in the diffusion region, the concentration of the second dopant may be from the second semiconductor layer the top surface is less than about 1x10 ¹⁷ cm ^-3 concentration is increased to an implanted region (e.g., below the top surface of about .02 microns) concentration of about 1x10 ¹⁸ cm ^-3.

The semiconductor structure can be incorporated, for example, into a heterojunction bipolar transistor to simultaneously improve the current gain cutoff frequency and the maximum oscillation frequency. That is, the bipolar transistor may include a base layer (eg, an epitaxially grown germanium base layer) that is in situ with a first dopant (eg, a p-type dopant such as boron). Doping. The peak concentration of this first doping in the base layer can be greater than about 1 x 10 ¹⁹ cm ^-3 at about .03 microns above the interface (i.e., above its top surface). The base layer may be formed over a collector layer (eg, a collector layer). In particular, the top surface of the collector layer can be adjacent to the bottom surface of the base layer. The collector layer can include a diffusion region on the top surface and an implant region below the diffusion region. The implanted region can be doped with a second dopant of uniform concentration (eg, an n-type dopant such as phosphorus, antimony or arsenic). For example, the implanted region can have a uniform second dopant concentration that is greater than a concentration of about 1 x 10 ¹⁸ cm ^-3 .

Thus, the diffusion region can include a portion of the first dopant diffused from the upper base layer and a portion of the second dopant diffused from the underlying implant region. However, during this formation, a laser tempering process can be performed to activate dopants in the implanted region and remove the top from the collector layer caused by the ion implantation process that forms the implanted region. Defects on the surface. Replacing the rapid thermal tempering process with a laser tempering process will minimize the diffusion of the second dopant from the implanted region. Furthermore, since the top surface of the collector layer is almost free of defects, the phenomenon that the first dopant from the base layer diffuses to the collector layer below it will be minimized.

Therefore, due to the lack of voids in the interface, the collector layer, and in particular the diffusion region of the collector layer, may comprise a first dopant concentration profile having a first dopant below the interface between the base and collector layers. The concentration is at least less than 100 times the peak concentration of the first dopant above the interface (eg, about .03 microns above the interface). That is, the peak concentration of the first dopant above the interface may be greater than at least 100 times the concentration of the first dopant below the interface. For example, the first dopant may have a peak concentration above the interface of greater than about 1×10 ¹⁹ cm ⁻³ , and the first dopant may have a first dopant concentration below the interface of less than about 1×10 ¹⁷ cm ^{− 3} . This first dopant concentration profile can be significantly reduced between the interface and the implanted region.

Furthermore, since the diffusion of the second dopant from the implanted region is minimized, the collector layer may further comprise a second dopant concentration profile, wherein the concentration of the second dopant is in the implanted region The middle system is generally uniform, but is significantly reduced toward the interface between the base and the collector layer throughout the diffusion region. For example, the concentration of the second dopant in the implanted region can be greater than about ten times the concentration of the second dopant at the top surface of the collector layer (ie, just below the interface). For example, the concentration of the second dopant in the implanted region may be uniform and may be greater than about 1×10 ¹⁸ cm ⁻³ ; however, in the diffusion region, the concentration of the second dopant may be close to the collector layer the top surface (i.e., in the interface) is less than a concentration of about 1x10 ¹⁷ cm ^-3, an implanted region to increase (e.g., below the top surface of about .02 microns) concentration of about 1x10 ¹⁸ cm ^-3.

A bipolar transistor having the aforementioned dopant concentration profile can have a current gain cutoff frequency greater than about 365.00 GHz and a maximum oscillation frequency greater than about 255.00 GHz, which is an effect that is not achievable by the general technique, and which may further include less than A collector-base capacitance of about 3.40 fF and a base sheet resistance of less than about 110.00 ohms.

Likewise, embodiments of a method of forming an improved semiconductor structure are disclosed herein, particularly to form the improved bipolar transistor structure described above. this The method includes providing a substrate (eg, a semiconductor wafer) and forming a starting semiconductor layer on the wafer. The starting semiconductor layer can be formed by epitaxial growth of a semiconductor layer over a semiconductor wafer using conventional process techniques.

Thereafter, a dopant (ie, a second dopant) can be implanted into a predetermined depth in the starting semiconductor layer (eg, about .03 microns below the top surface of the starting semiconductor layer) to form substantially uniform An implanted region of a second dopant concentration (eg, a uniform second dopant concentration greater than about 1 x 10 ¹⁸ cm ^-3 ). This second dopant may, for example, comprise an n-type dopant such as phosphorus, antimony or arsenic.

After the implantation process, a second radiant of the implanted region can be activated by performing a laser tempering process (such as a laser thermal process or a laser tempering process), and will be activated by the implantation process. Any defects formed at the top surface of the starting semiconductor layer are removed. The laser tempering is carried out at a temperature greater than about 1100 ° C and using a technique that avoids melting of the starting semiconductor layer and a heat balance of less than about 10 megaseconds in the starting semiconductor layer (ie, using millisecond lasers) A tempering process) to minimize diffusion of the second dopant from the implanted region, thereby maintaining the distribution of the second dopant in a narrow state. In particular, the use of this laser tempering process minimizes the diffusion of the second dopant such that the concentration distribution of the second dopant outside the implanted region is reduced (eg, from below the top surface of the starting semiconductor layer. The concentration at the micron is greater than 1 x 10 ¹⁸ cm ^{-3 to} a concentration close to the top surface of less than about 1 x 10 ¹⁷ cm ^-3 ). The use of such a laser tempering process can prevent the occurrence of point defects on the top surface of the semiconductor and the formation of extended defects and poorly arranged circles during subsequent processing. This laser thermal process method does not affect the impact of subsequent process conditions.

Once the laser tempering process is performed, an additional semiconductor layer is formed on the top surface of the starting semiconductor layer and heavily doped with a different dopant (ie, the first dopant). This first dopant may be different from the second dopant and may, for example, comprise a p-type dopant such as boron. This additional semiconductor layer can be formed, for example, by epitaxial growth of an additional semiconductor layer while simultaneously doping with a first dopant. Doping of the additional semiconductor layer may be performed such that the peak concentration of the first dopant in the additional semiconductor layer is about .03 microns above the top surface of the starting semiconductor layer below it (ie, above the interface between the two semiconductor layers) It is a concentration greater than about 1 x 10 ¹⁹ cm ^-3 .

Due to the defect removal process (as described above), the phenomenon that the first dopant from the additional semiconductor layer diffuses to the starting semiconductor layer will be minimized. That is, removing the defect of the top surface of the starting semiconductor layer by the laser tempering process will minimize the undesired defect-enhanced diffusion phenomenon of the first dopant and thereby maintain the first dopant Distributed in a narrow state. Specifically, the phenomenon that the first dopant from the additional semiconductor layer diffuses to the underlying semiconductor layer below is minimized by reducing defects (ie, voids) in the interface, so that the first dopant is in the additional semiconductor layer The peak concentration of the adjacent bottom surface may be the same as the concentration of the first dopant at the starting semiconductor layer Less than 100 times or more.

For example, the phenomenon that the first dopant from the additional semiconductor layer diffuses to the starting semiconductor layer can be minimized such that the peak concentration of the first dopant in the additional semiconductor layer can be maintained greater than that of the starting semiconductor layer A concentration of about 1×10 ¹⁹ cm ⁻³ at about .03 μm above the top surface (ie, just at the interface), and a concentration distribution of the first dopant in the diffusion region of the starting semiconductor layer is below the interface. It is less than about 1 x 10 ¹⁷ cm ^-3 and is significantly reduced toward the implanted area.

The foregoing method can be used, for example, to form a heterojunction bipolar transistor that will have an improved current gain cutoff frequency and a maximum oscillation frequency compared to such a transistor formed using conventional methods.

These and other aspects of the embodiments of the present invention will be better appreciated and appreciated. However, the following description of the preferred embodiments of the invention, The various modifications and variations of the present invention are intended to be included within the scope of the embodiments of the invention.

The detailed description of the embodiments of the invention and the various features and advantages thereof Specific implementations are set forth in the accompanying drawings and are described in detail in the description below. It is to be noted that the various features of the present invention are not necessarily to scale, and the description of the components and process techniques are omitted to avoid obscuring the embodiments of the present invention. The examples used herein are merely for the purpose of promoting the understanding of the embodiments of the invention. Therefore, the examples are not to be considered as limiting the scope of the embodiments of the invention.

As noted above, limitations in current process technologies also limit the vertical and lateral dimensions of the above-described heterojunction bipolar transistors. Specifically, narrowing the space charge region of the base and collector of the transistor increases the current gain cutoff frequency, but since the collector overlaps with the external base, this will sacrifice the maximum oscillation frequency. Thus, in conjunction with the size of the component, a selective ion-implanted collector (SIC) pad is described in U.S. Patent No. 6,846,710, issued to Jan et al. It has been applied to the above-described germanium heterojunction bipolar transistor such that the collector region is closer to the base region and thereby the current gain cutoff frequency is enhanced. However, current process technologies do not allow the SIC pads of the above-described heterojunction bipolar transistors to be sufficiently narrow to have minimal overlap with the outer base. Furthermore, conventional techniques for forming processes (ie, ion implantation and subsequent high temperature rapid thermal tempering (RTA) steps) will create voids in the base-collector interface of the heterojunction bipolar transistor. (such as intervals, defects, etc.). More specifically, SICs are typically formed using an ion implantation process that causes many damage in the germanium lattice, and then a high temperature rapid thermal tempering process is used to remove the ion implants. The damage caused by the process, and more to the base dopant atoms (such as boron) enough energy to move to the electrically active site. However, the thermal cycling of the rapid thermal tempering process is typically on the order of seconds, which would allow for excessive diffusion of the base dopant and broaden the dopant distribution of the base. Defects caused by ion implantation will enhance this diffusion phenomenon, which will result in an increase in junction depth and deactivation of the dopant, thus causing an increase in sheet resistance. . Furthermore, the thermal cycling of a typical rapid thermal tempering process allows for the accumulation of point defects and the formation of extended defects and differential ferrules, which can cause carrier mobility at the electrical junction defects and differential routing. Reduced and increased leakage current and degraded component benefits.

Accordingly, the present invention discloses an improved germanium heterojunction bipolar transistor comprising a narrow and substantially void-free SIC pad with minimal overlap with the outer mass. In contrast to a rapid thermal tempering process, the present invention also discloses a method of forming a transistor that utilizes a laser tempered SIC pad to produce a narrow SIC pad and a substantially void-free collector. Therefore, the germanium heterojunction bipolar transistor obtained by the present invention can have a narrow space charge region of the base and the collector compared to the prior art.

Referring to FIG. 1, disclosed herein is an embodiment of an improved multilayer semiconductor structure 150. The structure 150 includes a first semiconductor layer 103 and a second semiconductor layer 102 under the first semiconductor layer 103. Specifically, the top surface 112 of the second semiconductor layer 102 and the bottom of the first semiconductor layer 103 Surface 113 is adjacent.

The first semiconductor layer 103 is doped with the first dopant 181 (eg, about 1×10 ¹⁹ at about .03 micrometers (μm) above the interface between the bottom surface of the first semiconductor layer 103 and the top surface of the second semiconductor layer 102). The peak concentration of cm ^-3 , and the second semiconductor layer 102 may further comprise a diffusion region 130 at its top surface 112 (ie, just below the interface between layers 102 and 103), and in diffusion. Implanted region 120 below region 130. For example, the implanted region 120 can be doped with a uniform concentration of a second dopant 182 (such as an n-type dopant such as phosphorus (P), antimony (Sb) or arsenic (As)). For example, a concentration greater than about 1 x 10 ¹⁸ cm ^-3 .

Therefore, the diffusion region 130 may include not only a portion of the first dopant 181 diffused from the first semiconductor layer 103 above it, but also a portion of the diffusion region from the implant region 120 below it. Two dopants 182. However, during this formation, a laser tempering process can be performed to remove defects from the top surface 112 of the second semiconductor layer 102. More specifically, this laser tempering process is performed to remove defects caused by the ion implantation process that forms the implanted region 130 and to activate the dopants 182 in the implanted region 130. Replacing the rapid thermal tempering process with this laser tempering process will minimize the diffusion of the second dopant 182 from the implanted region 120 into the diffusion region 130.

Therefore, since there is no defect (i.e., void) in the interface, the diffusion between the layers 102 and 103 will be minimized, and the peak concentration of the first dopant near the bottom surface 113 of the first semiconductor 103 may be the same. The first dopant is at least 100 times greater than the concentration in the diffusion region 130 of the second semiconductor layer 102. For example, as described above, the first semiconductor layer 103 may be doped with a first dopant 181 (eg, a p-type dopant such as boron), and the first dopant is in the first semiconductor layer 103 The peak concentration may be greater than a concentration of about 1 x 10 ¹⁹ cm ^-3 at about .03 microns above its bottom surface 113. Moreover, since the interfaces 112-113 between the layers 102 and 103 have no voids, the peak concentration of the first dopant in the first semiconductor layer 103 may still be greater than about 1 x 10 ¹⁹ cm ^-3 , and the second semiconductor The diffusion region 130 of the layer 102 may then comprise a first dopant concentration profile having a first dopant concentration located below the interface at a concentration less than about 1 x 10 ¹⁷ cm ^-3 and decreasing with depth (see Figure 2). That is, the peak concentration of the first dopant above the interface is at least 100 times greater than the concentration of the first dopant below the interface.

Moreover, due to the minimized diffusion of the second dopant 182 from the implanted region 120, the second semiconductor layer 102 can further comprise a second dopant concentration profile, wherein the concentration of the second dopant 182 It is approximately uniform within the implanted region 120, but is significantly reduced within the diffusion region 130 of the implanted region 120 to the interfaces 112-113 of the two semiconductor layers 102 and 103. For example, the concentration of the second dopant 182 at the implanted region 120 can be greater than about ten times greater than the concentration of the second dopant 182 at the top surface 112 of the second semiconductor layer 102. For example, the concentration of the second dopant 182 in the implanted region 120 can be uniform and can be greater than about 1 x 10 ¹⁸ cm ^-3 ; however, in the diffusion region 130, this concentration can be self-adhesive to the second semiconductor layer 102. a top surface 112 (i.e. just below the interface) is less than about 1x10 ¹⁷ cm ^-3 concentration is increased to the implant region 120 (e.g., at about .02 microns below the interface) from about 1x10 ¹⁸ cm ^-3 (see FIG. 3) concentration.

Furthermore, the semiconductor structure 150 can be incorporated, for example, into a heterojunction bipolar transistor 100 to simultaneously improve the current gain cutoff frequency and the maximum oscillation frequency. In particular, the bipolar transistor structure 100 of FIG. 1 is similar to a conventional bipolar transistor structure, which may include a semiconductor substrate 101 doped with a first conductivity type dopant 181 (eg, doped with a boron such as boron) Substrate of the type of dopant). The top layer 106 of the substrate 101 may be further doped with a second conductivity type dopant 182 (eg, an n-type dopant such as phosphorus, antimony or arsenic), thereby forming a heavily doped sub-collector (ie, a buried collector). Layer 106 is on top of substrate 101.

The bipolar transistor structure 100 may further include a collector layer 102 (eg, an epitaxially grown germanium layer) over the buried collector layer 106. Impurity ions from buried collector layer 106 may diffuse into collector layer 102 such that the collector layer is slightly doped by second conductivity type dopant 182. The collector layer 102 can further comprise a selective implant collector (SIC) pad 120 doped with a second conductivity type dopant such that the collector layer 102 is heavily doped in this limited pad region.

The bipolar transistor structure 100 can also include an in-situ doped with a first conductivity type dopant 181 (eg, a p-type dopant such as boron). The crystal grows into the endoplasmic base 103. That is, the base layer 103 can be formed such that the top surface 112 of the collector layer 102 is adjacent to the bottom surface 113 of the base layer 103.

Finally, the bipolar transistor 100 may further comprise an emitter 105 doped with a second conductivity type dopant 182 (eg, an n-type dopant such as phosphorus, antimony or arsenic) and a shot above the base layer 103. The outer base 104 is external to either side of the pole 105.

However, the bipolar transistor structure 100 can be distinguished from the prior art germanium heterojunction bipolar transistor because the technique used to form the structure will result in the SIC pad 120 being substantially void free and externally primed. There is minimal overlap, so that a space charge region with a narrow base and collector relative to the prior art can be obtained.

More specifically, referring to FIG. 1, the bipolar transistor 100 can include a base layer 103 (eg, epitaxially doped) in situ with a first dopant (eg, a p-type dopant such as boron). Growing up to the base layer). The peak concentration of the first dopant 181 in the base layer 103 may be greater than 1 x 10 ¹⁹ cm ^-3 at about .03 μm above the interface between the bottom surface 113 of the base layer 103 and the top surface 112 of the collector layer 102. (See Figure 2). The base layer 103 can be formed (eg, epitaxially grown and in-situ doped) over the collector layer 102 (eg, a collector layer). In particular, the top surface 112 of the collector layer 102 can be adjacent to the bottom surface 113 of the base layer 103. The collector layer 102 can include a diffusion region 130 at its top surface 112 (i.e., just below the interface between layers 102 and 103), and a selective implant collector region (SIC) 120 can be positioned below the diffusion region 130. The implanted region 120 can be doped with a uniform concentration of a second dopant 182 (e.g., an n-type dopant such as phosphorus, antimony or arsenic), for example, having a concentration greater than about 1 x 10 ¹⁸ cm ^-3 .

Therefore, the diffusion region 130 may include a portion of the first dopant 181 diffused from the base layer 103 above it, and a portion of the second dopant 182 diffused from the SIC region 120 therebelow. However, during this formation, a laser tempering process can be implemented, and the laser tempering process is performed to activate the dopant 182 in the implanted region 120 and the top surface of the self-collector layer 102. 112 removes defects caused by the ion implantation process that forms implanted region 120. Replacing the conventional rapid thermal tempering process with a laser tempering process will minimize the diffusion of the second dopant 182 from the implanted region 120 and the first dopant between the layers 102 and 103.

Therefore, since the interface 112-113 between the layers 102 and 103 lacks a gap, the diffusion region 130 of the collector layer 102 may include a first dopant concentration distribution having a first dopant concentration located at the base and the set. Below the interface between the pole layers, the concentration is less than 100 times the peak concentration of the first dopant above the interface layer (e.g., about .03 microns above the interface). That is, the peak concentration of the first dopant above the interface is greater than at least 100 times the concentration of the first dopant below the interface. For example, if the peak concentration of the first dopant 181 at about .03 microns above the interface is about 1 x 10 ¹⁹ cm ^-3 , then the first dopant concentration below the interface can be less than about 1 x 10 ¹⁷ cm ^{-3 .} And decrement with depth (see Figure 2).

Moreover, because of the minimized diffusion of the second dopant 182 from the implanted region 120, the collector layer 102 can further comprise a second dopant concentration profile, wherein the concentration of the second dopant 182 is The implanted region 120 is approximately uniform, but is significantly reduced in the diffusion region 130 of the implanted region 120 to the interface 112-113 between the base and collector layers 102-103. For example, the concentration of the second dopant 182 at the implanted region 120 can be greater than about ten times greater than the concentration of the second dopant 182 at the top surface 112 of the collector layer 102 (ie, just below the interface). For example, the concentration of the second dopant in the implanted region can be uniform and can be greater than about 1 x 10 ¹⁸ cm ^-3 ; however, in the diffusion region 130, the concentration of the second dopant can be close to the collector The top surface 112 of the layer 102 (i.e., just below the interface) has a concentration of less than about 1 x 10 ¹⁷ cm ^-3 and is increased to about 1 x 10 ¹⁸ in the implanted region 120 (e.g., about .02 microns below the top surface 112). The concentration of cm ^-3 (see Figure 3).

As depicted in FIG. 4, the bipolar transistor 100 having the aforementioned dopant concentration profile can simultaneously exhibit a current gain cutoff frequency greater than about 365.00 GHz, and a maximum oscillation frequency greater than about 255.00 GHz, which is hitherto not possible with conventional techniques. The effect, and which may further comprise a collector-base capacitance (Ccb) of less than about 3.40 fF and a base sheet resistance (Rbb) of less than about 110.00 ohms (Ohm).

Embodiments of the method of forming the improved semiconductor structure 150 are also disclosed below, and in particular the improved bipolar transistor structure 100 described above.

More particularly, referring to FIG. 5 in conjunction with FIG. 1, one embodiment of the method includes providing a substrate (eg, a semiconductor wafer) (block 501) and forming a starting semiconductor layer 102 on the wafer (block 502). The starting semiconductor layer 102 can be formed by epitaxial growth of a semiconductor over a semiconductor wafer using conventional process techniques.

Thereafter, a dopant 182 (ie, a second dopant) can be implanted to a predetermined depth in the starting semiconductor layer (eg, about .03 microns below the top surface of the semiconductor layer) to form, for example, greater than about An implant region 120 of substantially uniform second dopant concentration of 1 x 10 ¹⁸ cm ^-3 (block 503). This second dopant 182 can, for example, comprise an n-type dopant such as phosphorus, antimony or arsenic. The implanted region 120 can be exposed by a general masked ion implantation process (eg, by depositing a photoresist layer, patterning the photoresist layer to expose a desired portion of the semiconductor layer 102, and implanting the selected dopant. The 182 to the exposed portion of the semiconductor layer 102 are formed in a desired region of the semiconductor layer 102.

After the implantation process, a laser tempering process (e.g., laser thermal process (LTP) or laser tempering process (LSA)) (block 504) can be implemented to activate the second in implanted region 120. The dopant 182 is removed and any defects formed at the top surface 112 of the starting semiconductor layer 102 due to the implantation process are removed. The laser tempering process is carried out at a temperature greater than about 1100 ° C and uses techniques that avoid melting of the starting semiconductor layer and achieving a thermal equilibrium of less than about 10 megaseconds (ps) in the starting semiconductor layer (ie, Use millisecond laser anneal process). That is to say, the laser interacts with the crucible and transfers its energy to the crystal lattice, thereby causing an increase in the vibration of the crystal lattice. The increased lattice vibration will generate heat and thus allow the thermal balance to reach a state of less than 10 ps. This rapid thermal balance will minimize the diffusion of the second dopant from the implanted region, thereby maintaining the distribution of the second dopant in a narrow state. In particular, the diffusion phenomenon of the second dopant 182 is minimized, for example, using a laser tempering process, such that the concentration profile of the second dopant 182 outside the implanted region 120 falls to the implanted region 120 and begins. between the top surface 112 of the semiconductor layer 102 (e.g., a concentration of about .02 microns probably downward from the top surface of the semiconductor layer is 1x10 ¹⁸ cm ^-3 to near the top surface 112 is less than a concentration of about 1x10 ¹⁷ cm ^-3). The use of such a laser tempering process can prevent the occurrence of point defects on the top surface of the semiconductor layer and the formation of extended defects and poorly arranged circles during subsequent processing.

Once the laser tempering process is performed, an additional semiconductor layer 103 is formed on the top surface of the starting semiconductor layer 102 and heavily doped with a different dopant 181 (ie, the first dopant) ( Block 505). This first dopant 181 can be different from the second dopant and can comprise, for example, a p-type dopant such as boron. This additional semiconductor layer 103 can be grown, for example, by epitaxial growth of the starting semiconductor layer 102, and simultaneously doped with the first dopant 181 (eg, such that the first semiconductor layer 103 The peak concentration of a dopant 181 is greater than the concentration of about 1x10 ¹⁹ cm ^-3 at about .03 microns above the top surface 112 of the semiconductor layer 102 below it (ie, above the interface between layers 102 and 103). ). The phenomenon in which this first dopant 181 diffuses from the additional semiconductor layer 103 into the underlying semiconductor layer 102 will be minimized due to the defect removal process (as discussed in block 504 above). That is to say, the removal of defects will minimize the undesired defect-enhanced diffusion phenomenon of the first dopant 181, and thereby maintain the desired dopant concentration in the additional semiconductor layer, and more maintain the dopant distribution. Narrow state. In particular, since there is no defect (ie, lack of voids) at the interfaces 112-113, the phenomenon that the first dopant 181 diffuses from the additional semiconductor layer 103 to the underlying semiconductor layer 102 below it is minimized, thus The peak concentration of the first dopant adjacent the bottom surface 113 of the additional semiconductor layer 103 can be maintained at least 100 times greater than the concentration of the same first dopant in the starting semiconductor layer 102.

For example, the diffusion of the first dopant can be minimized such that the peak concentration of the first dopant 181 in the additional semiconductor layer 103 can be maintained at about .03 microns above the top surface 112 of the starting semiconductor layer 102. (i.e., just above the interface) is greater than a concentration of about 1 x 10 ¹⁹ cm ^-3 , and the concentration distribution of the first dopant 181 in the starting semiconductor layer 102 is less than at the top surface 112 (i.e., just below the interface) The concentration is about 1 x 10 ¹⁷ cm ^-3 and is significantly reduced toward the implanted region 120 (see Figure 2-3).

Referring to Figure 6 in conjunction with Figure 1, the foregoing method can be used, for example, to form a heterojunction bipolar transistor (see transistor 100 of Figure 1), as compared to the general The transistor formed by the method has an improved current gain cutoff frequency and a maximum oscillation frequency.

Specifically, a semiconductor substrate 101 (for example, a substrate doped with a p-type dopant such as boron (B)) doped with a first conductivity type dopant 181 is provided (block 601, see FIG. 7). Thereafter, the top layer 106 of the substrate 101 is doped with a second conductivity type dopant (eg, an n-type dopant such as phosphorus, antimony or arsenic) (eg, by a general ion implantation process), thereby forming a heavily doped A hetero-collector (ie buried collector) layer 106 is on top of the substrate 101 (block 602, see Figure 7).

Thereafter, a collector collector layer 102 is formed over the buried collector layer 106 (block 603, see FIG. 7), and the tantalum collector layer 102 can be formed, for example, using a general epitaxial deposition process. Impurity ions from the buried collector layer 106 may diffuse into the collector layer 102 such that the collector layer 102 will be lightly doped by the second conductivity type dopant 182.

Next, a dopant (ie, the second dopant 182) can be implanted into the germanium collector layer 102 at a predetermined depth (eg, about .03 microns below the top surface of the germanium collector layer) to form A selective implanted collector (SIC) pad 120 having a substantially uniform second dopant concentration (block 604, see FIG. 8), which may be, for example, greater than a uniform concentration of about 1 x 10 ¹⁸ cm ^-3 .

As described above for the semiconductor structure, the second dopant 182 can be packaged, for example. Contains an n-type dopant such as phosphorus, antimony or arsenic. The implanted region 120 can be exposed by a general masked ion implantation process (eg, by depositing a photoresist layer 125, patterning the photoresist layer 125 to expose a desired portion 126 of a collector layer 102, and implanting The selected dopant 182 to the exposed portion 126 of the collector layer 102 is formed in the desired region of the collector layer 102.

After the implantation process, a laser tempering process (eg, a laser thermal process (LTP) or a laser transient tempering process (LSA)) (block 605, see FIG. 9) can be implemented to activate the SIC pad 120. The second dopant 182 removes any defects formed on the top surface 112 of the tantalum collector layer 102 due to the implantation process. The laser tempering process is carried out at a temperature greater than about 1100 ° C and uses a technique that avoids melting of the tantalum collector layer 102 and provides a thermal balance of less than about 10 ps in the tantalum collector layer 102 (ie, using millisecond laser tempering) The process) is to minimize the diffusion phenomenon of the second dopant 182 from the SIC pad and thereby maintain the distribution of the second dopant in a narrow state. Specifically, the diffusion phenomenon of the second dopant 182 is minimized, for example, by using a laser tempering process, such that the concentration of the second dopant 182 outside the SIC pad 120 is distributed in the implanted region and the collector layer 102. There will be a significant reduction between the top surfaces 112 (e.g., from a concentration of about .02 microns below the top surface 112 of the collector layer 102 to a concentration of about 1 x 10 ¹⁸ cm ^{-3 to} a concentration near the top surface 112 of less than about 1 x 10 ¹⁷ cm ^-3 ( See Figure 3)). The use of such a laser tempering process prevents the top surface 112 of the collector layer 102 from accumulating point defects and forming extended and poorly entangled circles during subsequent processing. Those skilled in the art will appreciate that the use of such laser tempering processes in place of rapid thermal tempering processes can be easily integrated into current forming techniques. In particular, the laser process technology approach does not disturb previous or subsequent process models or steps.

Once the laser tempering process is performed, a germanium base layer 103 is formed over the top surface 112 of the germanium collector layer 102 and is doped with a different dopant 181 (ie, the first dopant). ) (block 606, see Figure 10). This first dopant 181 can be different from the second dopant and can comprise, for example, a p-type dopant such as boron. This base layer 103 can be formed, for example, by epitaxial growth techniques, and simultaneously doped in situ with the first dopant 181.

During the in-situ doping process, for example, the base layer 103 can be doped such that the peak concentration of the first dopant 181 in the germanium layer 103 is greater than the top surface 112 of the germanium collector layer 102 below it. (i.e., above the interface of layers 102-103) is about 1 x 10 ¹⁹ cm ^-3 at about .03 microns. The phenomenon in which the first dopant 181 diffuses from the ruthenium base layer 103 to the underlying ruthenium collector layer 102 will be minimized due to the defect removal process (as discussed in block 605 above). That is to say, the removal of defects will minimize the undesired defect-enhanced diffusion phenomenon of the first dopant 181, and thereby maintain the desired dopant concentration in the base layer 103, and more maintain the dopant. Distributed in a narrow state.

In particular, since there is no defect (ie, no void) at the interfaces 112-113, the phenomenon that the first dopant 181 diffuses from the base layer 103 to the collector layer 102 located thereunder is minimized, thus The peak concentration of the first dopant 181 adjacent the bottom surface 113 of the base layer 103 (ie, just above the interface) can be maintained at least greater than the concentration of the same first dopant 181 in the collector layer 102. Times. For example, the diffusion of the first dopant can be minimized such that the peak concentration of the first dopant 181 in the base layer 103 can be maintained at about .03 microns above the top surface 112 of the collector layer 103. A concentration greater than about 1 x 10 ¹⁹ cm ^-3 , and the concentration distribution of the first dopant in the collector layer is less than about 1 x 10 ¹⁷ cm ^-3 at the top surface 112 and is significantly reduced toward the implanted region 120 (see Figure 2-3).

After the germanium base layer 103 is formed, a heterojunction bipolar transistor structure can be completed using general process techniques (block 607, see FIG. 1) including, but not limited to, the insulating structure of the component, the emitter 105, and the outer The formation of the base electrode 104 and the like.

The germanium heterojunction bipolar transistor 100 formed by this means has the advantage of completely removing defects (such as point defects) from the surface of the collector layer, and can simultaneously reduce the doping of the SIC and the base layer. Over-diffusion of the object, which will result in a narrower base, a narrower collector-base junction, lowering the collector-base capacitance (Ccb), and increasing the maximum oscillation frequency. The resulting narrow endogenous boron distribution reduces the base transfer time and increases the current gain cutoff frequency. Furthermore, the removal of point defects reduces the likelihood of forming extended defects, such as poor alignment, and improves component yield. More specifically, referring again to FIG. 1, the germanium heterojunction bipolar transistor 100 formed by this means simultaneously diffuses the second dopant 182 from the SIC pad 120 and diffuses to the collector. The diffusion of the first dopant 181 in the layer 102 is minimized (i.e., the distribution of the base layer 102 and the SIC pad 120 is simultaneously narrowed), and thereby the formed bipolar transistor 100 has a greater than about 365.00. The current gain cutoff frequency of GHz, the maximum oscillation frequency greater than about 255.00 GHz, the collector-base capacitance of less than about 3.40 fF, and the base sheet resistance of less than about 110.00 ohms (see Figure 4).

Embodiments of the method of the present invention are described above and illustrated in FIG. 6, which implements SIC implant process 604 and laser tempering process 605 prior to process 606 forming the base layer. However, when the collector layer is formed in process 602 and then the base layer 606 is formed, the SIC pad 604 is formed, and finally the laser tempering process 605 is performed, similar results (ie, simultaneously improved current gain cutoff frequency and improved) The maximum oscillation frequency can also be achieved. That is, the results are verified via the SIC implantation process 604 and the laser tempering process 605 prior to forming the base layer 606, and also via the SIC implantation process 604 and laser after forming the base layer 606. Confirmed by the tempering process 605.

FIG. 11 shows a block diagram of an example design flow 1100. Design flow 1100 can vary with the type of IC being designed. For example, the design flow 1100 for constructing a particular application specific IC (ASIC) may be different from the design flow 1100 of designing a standard component. Design structure 1120 is preferably an input unit of design program 1110 and may be from an IP provider, core developer, or other design company, or may be generated by an operator of the design process or from other sources. Design structure 1120 The circuit 100 may be embodied in the form of a circuit diagram or a hardware description language (HDL) (e.g., Verilog, VHDL, C, etc.). Design structure 1120 can be included in one or more machine readable mediums. For example, design structure 1120 may be a text file or illustration of circuit 100. The design program 1110 preferably synthesizes (or translates) the circuit 100 into the form of a netlist 1180, wherein the net list 1180 is a form such as a line, a transistor, a logic gate, a control circuit, an I/O, a model, or the like. It describes a connection to an integrated circuit design and other components or circuits recorded in at least one machine readable medium. This may be a repetitive procedure in which the net list 1180 can be resynthesized one or more times depending on the design specifications and parameters of the circuit.

The design program 1110 can include the use of a variety of different inputs, such as input from a library element 1130, which can be for a particular fabrication technique (eg, different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specification 1140, Feature table 1150, verification material 1160, design rule 1170, and test data file 1185 (which may include test patterns and other test information), and store a set of common components, circuits, and components, including modules, layouts, and symbolic representations. The design program 1110 may further include, for example, standard circuit design programs such as timing analysis, verification, design rule validation, placement, and routing operations. Those skilled in the art of circuit design will appreciate that the design structure of the present invention is not limited to any particular one, without departing from the scope and spirit of the present invention, when the scope and application of the electronic automation machine that can be used in the design program 1110 can be understood. Design process.

The design program 1110 preferably translates an embodiment of the invention as shown in FIG. 11 and any additional integrated circuit design or material (if appropriate) to the second design structure 1190. The second design structure 1190 is stored in a data format on a storage medium for exchanging layout data of the integrated circuit (eg, stored in GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). data). For example, design structure 1190 can include, for example, test data files, design content files, manufacturing materials, layout parameters, wiring, metal layers, vias, graphics, routing production lines, and any other semiconductor manufacturer needed to make The material of the embodiment of the invention as shown in FIG. Design structure 1190 can then proceed to stage 1195, for example, design structure 1190 can be made to tape-out, release manufacturing, release to a mask factory, delivery to another design factory, and return to customer And other stages.

Thus, what has been disclosed above is an improved semiconductor structure (e.g., a heterojunction bipolar transistor) having a SIC pad that is minimally narrow and substantially void free from the outer base. Similarly, it discloses a method of forming a transistor that uses a laser tempered SIC pad to create a narrow SIC pad and a substantially void-free collector relative to a rapid thermal tempering process, and thus obtained The final SiGe HBT transistor will have a narrower space and collector space charge region than conventional techniques.

The foregoing description of the specific embodiments will present the general features of the present invention so that others can implement the present invention without departing from the general concepts. The various modifications and/or adaptations of the specific embodiments of the present invention are intended to be modified and/or modified, and such modifications or modifications are intended to be included within the meaning and scope of the disclosed embodiments. Thus, it will be understood by those skilled in the art that the embodiments of the invention can be practiced in the modifications and the scope of the scope of the appended claims.

100‧‧‧Bipolar transistor/circuit

101‧‧‧Substrate

102‧‧‧Semiconductor layer/collector layer/starting semiconductor layer/矽 collector layer

103‧‧‧Semiconductor/base layer/endogenous base/矽锗 base layer

104‧‧‧Equivalent base

105‧‧‧射极

106‧‧‧Top/Second Collector/buried collector

112‧‧‧ top surface

113‧‧‧ bottom surface

112-113‧‧ Interface

120‧‧‧ Implanted area/selective implant collector pad/SIC area

125‧‧‧ photoresist layer

126‧‧‧ exposed parts of the collector layer

130‧‧‧Diffusion area

150‧‧‧Semiconductor structure

181‧‧‧First dopant/first conductivity type dopant

182‧‧‧Second dopant/second conductivity dopant

LTP‧‧‧Laser thermal process

RTA‧‧‧Quick heat tempering

HBT‧‧‧Hoided junction bipolar transistor

SIC‧‧‧Selective ion implantation collector

The embodiments of the present invention will be better understood by the following detailed description and the drawings, wherein: FIG. 1 is a schematic block diagram showing an embodiment of the structure of the present invention; FIG. 2 is a schematic diagram illustrating Using different laser tempering temperatures, the boron concentration distribution achieved by the structure of Figure 1; Figure 3 is a schematic diagram showing the phosphorus concentration distribution achieved by the structure of Figure 1 using different laser tempering temperatures; Figure 4 is a table comparing FIG. 5 is a flow chart illustrating an embodiment of the method of the present invention; FIG. 6 is a flow chart illustrating another embodiment of the present invention; FIG. FIG. 7 is a schematic block diagram showing a part of the completed structure of the present invention; FIG. 8 is a schematic block diagram showing a part of the completed structure of the present invention; and FIG. 9 is a schematic block diagram showing a partially completed Figure 10 is a schematic block diagram showing a portion of the completed structure of the present invention; Figure 11 illustrates a first-class design, fabrication, and/or testing of semiconductors. Cheng Tu.

Claims (42)

A semiconductor structure comprising: a first semiconductor layer having a bottom surface and comprising germanium and a first dopant having a first conductivity type; and a second semiconductor layer disposed on the first semiconductor layer And adjacent to the first semiconductor layer, the second semiconductor layer comprises germanium and a second dopant of a second conductivity type different from the first conductivity type; and located in the second semiconductor layer And a third semiconductor layer adjacent to the second semiconductor layer, the third semiconductor layer comprising germanium and the second dopant; wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are Undoped carbon; wherein the second semiconductor layer has a top surface adjacent to the bottom surface, and the top surface includes a diffusion region, and the second semiconductor layer further includes an implant under the diffusion region a region adjacent to the third semiconductor layer and extending perpendicularly from the third semiconductor layer toward the top surface of the second semiconductor layer, the implant region further and the top surface of the second semiconductor layer Separate approximately 0.03 Micrometer, the implanted region being narrower in width than the diffused region and comprising a second dopant having a higher concentration than any other region of the second semiconductor layer; wherein the diffusion region comprises the first dopant And the second dopant; wherein the top surface is substantially free of defects such that a concentration of the first dopant in the first semiconductor layer adjacent to the bottom surface is greater than the first dopant At least 100 times the concentration of one of the diffusion regions of the second semiconductor layer; Wherein a concentration distribution of the second dopant in the second semiconductor layer is substantially uniform in the implanted region, and is reduced by the diffusion region, such that the second dopant in the implanted region The concentration is greater than about 10 times the concentration of the second dopant at the top surface. The semiconductor structure of claim 1, wherein the concentration of the first dopant of the first semiconductor layer increases from about 1×10 ¹⁷ cm ⁻³ at the bottom surface to about 0.03 μm above the bottom surface. The peak concentration, the peak concentration of the first dopant in the first semiconductor layer is greater than a concentration of about 1 x 10 ¹⁹ cm ^-3 . The semiconductor structure of claim 1, wherein the concentration of the first dopant in the diffusion region is less than a concentration of about 1 x 10 ¹⁶ cm ^-3 . The semiconductor structure of claim 1, wherein the first dopant comprises a p-type dopant, the p-type dopant comprises boron, and the second dopant comprises an n-type dopant, The n-type dopant includes one of phosphorus, antimony, and arsenic. The semiconductor structure of claim 1, wherein a concentration of the second dopant in the implant region is greater than 1 x 10 ¹⁸ cm ^-3 and is more uniform, and wherein the second blend in the diffusion region a concentration of debris from the area adjacent the implant is greater than about 1x10 ¹⁸ cm ^-3 for the first semiconductor layer is reduced less than about of the top surface of the second semiconductor layer is 1x10 ¹⁷ cm ^-3. A bipolar transistor comprising: a base layer having a bottom surface and comprising germanium and a first dopant having a first conductivity type; and a collector layer located at the base layer And next to the base layer, the collector layer comprises a second dopant having a second conductivity type different from the first conductivity type; and a primary collector layer located in the episode The bottom layer is adjacent to the collector layer; the second collector layer comprises germanium and the second dopant; wherein the base layer, the collector layer and the sub-collector layer are all undoped with carbon; The collector layer has a top surface adjacent to the bottom surface of the base layer, and the top surface includes a diffusion region, and the collector layer further includes an implant region located below the diffusion region. The implanted region is adjacent to the secondary collector layer and extends perpendicularly from the secondary collector layer toward the top surface of the collector layer, the implanted region being further separated from the top surface of the collector layer by about 0.03 micrometers. The implanted region is narrower in width than the diffused region and includes the second having a higher concentration than any other region of the collector layer a dopant; wherein the diffusion region comprises the first dopant and the second dopant; wherein the top surface is substantially free of defects such that the first dopant in the base layer is adjacent to the bottom surface The peak concentration is greater than at least 100 times a concentration of the first dopant in the diffusion region of the collector layer; and wherein a concentration distribution of the second dopant in the collector layer is at the implant The region is substantially uniform and is reduced by the diffusion region such that the concentration of one of the second dopants in the implanted region is greater than 10 times the concentration of the second dopant at one of the top surfaces. The bipolar transistor of claim 6, wherein the concentration of the first dopant in the base layer increases from about 1 x 10 ¹⁷ cm ^-3 at the bottom surface to about 0.03 μm above the bottom surface. The peak concentration of the first dopant in the base layer is greater than about 1 x 10 ¹⁹ cm ^-3 . The bipolar transistor of claim 6, wherein the concentration of the first dopant in the diffusion region is less than about 1 x 10 ¹⁶ cm ^-3 . The bipolar transistor of claim 6, wherein the implanted region further comprises a selectively implanted collector region. The bipolar transistor of claim 6 having a current gain cutoff frequency greater than about 365.00 GHz and a maximum oscillation frequency greater than about 255.00 GHz. The bipolar transistor of claim 6 having a collector-base capacitance of less than about 3.40 fF and a base sheet resistance of less than about 110.00 ohms. The bipolar transistor of claim 6, wherein a concentration of the second dopant in the implanted region is greater than 1 x 10 ¹⁸ cm ^-3 and is more uniform, and wherein the first portion of the diffusion region A concentration of the dopant is reduced from greater than about 1 x 10 ¹⁸ cm ^-3 adjacent the implanted region to less than about 1 x 10 ¹⁷ cm ^-3 adjacent the base layer of the top surface of the collector layer. The bipolar transistor of claim 6, wherein the second dopant comprises an n-type dopant, the n-type dopant comprising one of phosphorus, antimony and arsenic, and wherein the first doping The impurity comprises a p-type dopant comprising boron. A bipolar transistor comprising: a protruding outer base layer having a first and a second portion separated by a space; an emitter layer disposed in the space between the first and second portions, The emitter layer has opposing sidewalls; sidewall spacers adjacent to the opposing sidewalls and separating the emitter layer from the first and second portions; at the emitter layer, the sidewall spacers, and the like a base layer under the first and second portions, the base layer having a bottom surface and comprising germanium and a p-type dopant; a collector layer under the base layer; a primary collector layer below the collector layer, the collector layer and the collector layer each comprising germanium and an n-type dopant; wherein the base layer, the collector layer and the collector layer are not Doping carbon; wherein the collector layer has a top surface adjacent to the bottom surface of the base layer, the top surface being substantially free of defects; wherein the collector layer further comprises: the top surface adjacent to the base a diffusion region comprising the p-type dopant and the n-type dopant; and being located under the diffusion region An implanted region adjacent to the secondary collector layer and extending perpendicularly from the secondary collector layer toward the top surface of the collector layer, the implanted region being further associated with the collector layer The top surface is separated by about 0.03 micrometers; the implanted region is aligned with the emitter layer and is narrower in width than the space such that the outer edge of the implanted region is not lower than the raised outer base layer Laterally extending; and the implanted region comprises a second dopant having a higher concentration than any other region of the collector layer; wherein a concentration of the p-type dopant in the diffusion region is less than about 1×10 ¹⁶ cm ^-3 ; wherein the p-type dopant of the base layer has a peak concentration of about 0.03 μm above the bottom surface of about 1×10 ¹⁹ cm ⁻³ ; wherein the n-type doping in the implanted region One concentration of the impurities is greater than about 1 x 10 ¹⁸ cm ^-3 and is more uniform; and wherein a concentration of the n-type dopant in the diffusion region is greater than about 1 x 10 ¹⁸ cm ^-3 from adjacent the implanted region Reducing to the base layer adjacent to the top surface of the collector layer is less than about 1 x 10 ¹⁷ cm ^-3 . The bipolar transistor of claim 14, wherein the concentration of the first dopant in the base layer increases from about 1 x 10 ¹⁷ cm ^{-3 of} the bottom surface to the peak concentration. The bipolar transistor of claim 14, wherein the concentration of the p-type dopant in the diffusion region is less than about 1 x 10 ¹⁶ cm ^-3 . The bipolar transistor of claim 14 having a current gain cutoff frequency greater than about 365.00 GHz and a maximum oscillation frequency greater than about 255.00 GHz. The bipolar transistor of claim 14 having a collector-base capacitance of less than about 3.40 fF and a base sheet resistance of less than about 110.00 ohms. The bipolar transistor of claim 14, wherein the n-type dopant comprises one of phosphorus, antimony and arsenic, and the p-type dopant comprises boron. A design structure for a semiconductor structure, wherein: the design structure includes at least layout parameters, test patterns, and other test information and manufacturing line information for the semiconductor structure; the design structure is set in a machine readable storage In the medium, the machine readable storage medium is accessible by a machine that can process the design structure to produce the semiconductor structure; and the semiconductor structure includes: a first semiconductor layer having a bottom surface and including And a first dopant having a first conductivity type; and a second semiconductor layer under the first semiconductor layer and adjacent to the first semiconductor layer, the second semiconductor layer comprising germanium And a third semiconductor layer under the second semiconductor layer and adjacent to the second semiconductor layer; wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor The layer is undoped with carbon; wherein the second semiconductor layer has a diffusion region adjacent to a top surface of the bottom surface and is included in the top surface; wherein the diffusion region comprises the first dopant and has The first conductivity type is different from a second dopant of the second conductivity type; wherein the top surface is substantially free of defects such that the first dopant in the first semiconductor layer is adjacent to the bottom surface The peak concentration is greater than at least 100 times the concentration of the first dopant in the diffusion region of the second semiconductor layer; wherein the third semiconductor layer comprises germanium and the second dopant; and wherein the second The semiconductor layer further includes an implant region under the diffusion region, the implant region is adjacent to the third semiconductor layer, and extends perpendicularly from the third semiconductor layer toward the top surface of the second semiconductor layer, the implant The in-region is further separated from the top surface of the second semiconductor layer by about 0.03 micrometers, the implanted region being narrower in width than the diffused region, and comprising a higher concentration than any other region of the second semiconductor layer a second dopant, wherein the A concentration distribution of one of the second dopants in the second semiconductor layer is substantially uniform in the implanted region, and is reduced by the diffusion region such that a concentration of the second dopant in the implanted region is Greater than about 10 times the concentration of the second dopant at one of the top surfaces. The design structure of claim 20, wherein the design structure includes a network description describing a circuit. The design structure of claim 20, wherein the design structure is left in a On the storage medium, as a data format for the layout data used to exchange integrated circuits. The design structure of claim 20, wherein the design structure comprises at least one of a test data file, a feature data, a verification data, and a design specification. The design of claim 20, wherein the peak concentration of the first dopant in the first semiconductor layer is greater than about 1 x 10 ¹⁹ cm ^-3 at about 0.03 microns above the bottom surface. The design of claim 20, wherein the concentration of the first dopant in the diffusion region is less than about 1 x 10 ¹⁷ cm ^-3 . The design structure of claim 20, wherein the first dopant comprises a p-type dopant, the p-type dopant comprises boron, and the second dopant comprises an n-type dopant, The n-type dopant comprises one of phosphorus, antimony and arsenic. A design structure for a bipolar transistor, wherein: the design structure includes at least layout parameters, test patterns, and other test information and manufacturing line information for the bipolar transistor; the design structure is set in a machine In a readable storage medium, the machine readable storage medium is accessible by a machine that processes the design structure to produce the bipolar transistor; and the bipolar transistor comprises: a base layer having a bottom surface and comprising germanium and a first dopant having a first conductivity type; and a collector layer below the base layer and adjacent to the base a layer, the collector layer comprising germanium; and a primary collector layer under the collector layer and adjacent to the collector layer; wherein the base layer, the collector layer and the collector layer are undoped Carbon; wherein the collector layer has a diffusion region adjacent to a top surface of the bottom surface and included in the top surface; wherein the diffusion region comprises the first dopant and has a different conductivity from the first conductivity type a second dopant of a second conductivity type; wherein the top surface is substantially free of defects such that a peak concentration of the first dopant in the base layer adjacent to the bottom surface is greater than the first The dopant is at least 100 times a concentration in the diffusion region of the collector layer; wherein the sub-collector layer comprises germanium and the second dopant; and wherein the collector layer further comprises a site in the diffusion An implanted region below the region, the implanted region being adjacent to the collector layer and facing from the secondary collector layer The top surface of the pole layer extends perpendicularly, the implanted region being further separated from the top surface of the collector layer by about 0.03 microns, the implanted region being narrower in width than the diffusing region and comprising the collector layer a second dopant having a high concentration in any other region, wherein a concentration distribution of the second dopant in the collector layer is substantially uniform within the implant region and is reduced by the diffusion region The concentration of the second dopant in the implanted region is greater than about 10 times the concentration of the second dopant at the top surface. The design structure of claim 27, wherein the design structure includes a network list describing a circuit. The design structure of claim 27, wherein the design structure is left on a storage medium as a data format for exchanging layout data of the integrated circuit. The design structure of claim 27, wherein the design structure comprises at least one of a test data file, a feature data, a verification data, and a design specification. The design of claim 27, wherein the concentration of the first dopant in the base layer increases from about 1 x 10 ¹⁷ cm ^-3 at the bottom surface to about 0.03 μm above the bottom surface. The peak concentration, the peak concentration of the first dopant in the base layer is greater than about 1 x 10 ¹⁹ cm ^-3 . The design of claim 27, wherein the concentration of the first dopant of the diffusion region is less than about 1 x 10 ¹⁷ cm ^-3 . The design structure of claim 27 has a current gain cutoff frequency greater than about 365.00 GHz and a maximum oscillation frequency greater than about 255.00 GHz. The design of claim 27 has a collector-base capacitance of less than about 3.40 fF and a base sheet resistance of less than about 110.00 ohms. A design structure for a bipolar transistor, wherein: the design structure includes at least layout parameters, test patterns, and other test information and manufacturing line information for the bipolar transistor; the design structure is set in a machine In a readable storage medium, the machine readable storage medium is accessible by a machine that processes the design structure to produce the bipolar transistor; and the bipolar transistor comprises: a base layer, a first dopant having a bottom surface and comprising germanium and having a first conductivity type; and a collector layer located below the base layer and adjacent to the base layer, the collector The layer includes germanium; and a primary collector layer located below the collector layer and adjacent to the collector layer; wherein the base layer, the collector layer, and the collector layer are undoped with carbon; The pole layer has a diffusion region adjacent to a top surface of the bottom surface and included in the top surface; wherein the diffusion region includes the first dopant and has a second conductivity different from the first conductivity type a second dopant of the type; and wherein the top surface Relying without defects such that a peak concentration of the first dopant in the base layer adjacent to the bottom surface is greater than at least a concentration of the first dopant in the diffusion region of the collector layer 100 times; wherein the collector layer comprises germanium and the second dopant; Wherein the collector layer further comprises an implanted region below the diffusion region, the implanted region is adjacent to the secondary collector layer, and extends perpendicularly from the secondary collector layer toward the top surface of the collector layer The implanted region is further separated from the top surface of the collector layer by about 0.03 microns, the implanted region being narrower in width than the diffused region and comprising a higher concentration in any other region than the collector layer The second dopant, the implant region further includes a selectively implanted collector region, wherein a concentration distribution of the second dopant in the collector layer is substantially uniform within the implant region, and The diffusion region is lowered such that a concentration of the second dopant in the implant region is greater than about 10 times the concentration of the second dopant at the top surface. The design structure of claim 35, wherein the design structure includes a network list describing a circuit. The design structure of claim 35, wherein the design structure is left on a storage medium as a data format for exchanging layout data of the integrated circuit. The design structure of claim 35, wherein the design structure comprises at least one of a test data file, a feature data, a verification data, and a design specification. The design of claim 35, wherein the concentration of the first dopant in the base layer increases from about 1 x 10 ¹⁷ cm ^-3 at the bottom surface to about 0.03 μm above the bottom surface. The peak concentration, the peak concentration of the first dopant in the base layer is greater than about 1 x 10 ¹⁹ cm ^-3 . The design of claim 35, wherein the concentration of the first dopant of the diffusion region is less than about 1 x 10 ¹⁷ cm ^-3 . The design of claim 35 has a current gain cutoff frequency greater than about 365.00 GHz and a maximum oscillation frequency greater than about 255.00 GHz. The design of claim 35 has a collector-base capacitance of less than about 3.40 fF and a base sheet resistance of less than about 110.00 ohms.